TWI842043B - Memory device and computing method thereof - Google Patents

Abstract

The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit, coupled to the at least one memory sub-array. The memory array includes at least one memory sub-array, the at least one memory sub-array including: a plurality of memory cells, a plurality of first signal lines, a plurality of second signal lines and a plurality of third signal lines coupled to the memory cells. The memory cells receives the input values via the second signal lines and the third signal lines, the memory cells generate a plurality of source currents, the source currents flowing through the first signal lines to generate a plurality of common source currents, the common source currents flowing into the at least one calculation unit, a first part of the memory cells generate a first part of the common source currents, a second part of the memory cells generate a second part of the common source currents; the first part of the memory cells store a plurality of first part coefficients of the interact coefficients, and the second part of the memory cells store a plurality of second part coefficients of the interact coefficients, wherein the first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array; and the first part of the common source currents is for calculating a first part of a local field energy of the model computation; and the second part of the common source currents is for calculating a second part of the local field energy of the model computation.

Description

Memory device and operation method thereof

The present invention relates to a semiconductor device and a calculation method using the semiconductor device, and in particular to a memory device and a calculation method using the memory device to process model calculations.

In today's booming technology, daily life is closely related to big data; models can be constructed based on various parameters in big data, and then model calculations can be used to provide solutions to target problems.

On the other hand, in the field of electronics or semiconductor technology, model calculations are often used to adjust the process parameters or condition factors of electronic devices or semiconductor components. However, complex electronic devices or semiconductor components involve a large number of parameters or factors, so complex model calculations need to be performed, resulting in time-consuming, energy-consuming or hardware-cost-consuming model calculations.

For example, the Ising model with multiple spin states can be used to perform annealing operations. The Ising model can be applied to the traveling salesman problem (TSP) to obtain the optimal solution with the minimum travel distance. When the temperature of the annealing operation of the Ising model is reduced and the minimum energy value of the Ising model is reached, the optimal solution of the configuration of the spin state can be obtained.

For a fully-connected Yishin model, the annealing operation of the Yishin model can be performed in parallel, which can quickly reach the minimum energy value of the Yishin model. During the annealing operation, the spin state needs to be updated. However, when the dimension of the Yishin model is large and has a large number of spin states, a large amount of computing resources and a long computing time are required. In addition, defects in the hardware device that executes the Yishin model also lead to calculation errors in the annealing operation.

Therefore, technical personnel in related industries in this technical field are committed to developing technical solutions to more efficiently execute model calculations in order to increase the speed of annealing calculations.

According to one aspect of the present invention, a memory device is provided, including: a memory array for processing a model operation, the model operation having a plurality of input values and a plurality of interaction coefficients. The memory array includes at least one memory sub-array and at least one operation unit coupled to the at least one memory sub-array. The at least one memory sub-array includes: a plurality of memory cells; and a plurality of first signal lines, a plurality of second signal lines, and a plurality of third signal lines coupled to the memory cells. The memory cells receive the input values through the second signal lines and the third signal lines. The memory cells generate a plurality of source currents. The source currents flow through the first signal lines to generate a plurality of common source currents. The common source currents are sent to the at least one operation unit. A first portion of the memory cells generates a first portion of the common source currents, and a second portion of the memory cells generates a second portion of the common source currents. The first portion of the memory cells stores a plurality of first values of the interaction coefficients. The first part of the memory cells and the second part of the memory cells store a plurality of the interaction coefficients. The second part of the memory cells and the second part of the memory cells are electrically isolated based on a diagonal of the memory array; and the at least one operation unit calculates a first part of a local energy of the model operation according to the first part of the common source currents, and calculates a second part of the local energy of the model operation according to the second part of the common source currents.

According to another aspect of the present invention, a method for operating a memory device is provided for processing a model operation having a plurality of input values and a plurality of interaction coefficients. The method comprises: storing a plurality of first part coefficients of the interaction coefficients in a first part of a plurality of memory cells of at least one memory sub-array of a memory array of the memory device, and storing a plurality of second part coefficients of the interaction coefficients in a second part of the memory cells, wherein the first part of the memory cells and the second part of the memory cells are electrically isolated based on a diagonal line of the memory array. ; inputting the input values to the memory cells, the memory cells generate a plurality of source currents, the source currents flow through a plurality of first signal lines of the memory device to generate a plurality of common source currents, the first part of the memory cells generates a first part of the common source currents, the second part of the memory cells generates a second part of the common source currents; and calculating a first part of a local energy of the model operation according to the first part of the common source currents, and calculating a second part of the local energy of the model operation according to the second part of the common source currents.

In order to better understand the above and other aspects of the present invention, the following is a specific example and a detailed description with the attached drawings as follows:

30: Memory cells

Ma, Mb: transistor

Ga, Gb: Gate

Da, Db: Drain

Sa, Sb: source

50: Memory cells

1000:Memory device

1005:Memory array

1020: Arithmetic unit

1030:Conversion unit

1040: Bit line driver

1050: word line driver

1010:Memory subarray

1-1~N-(N+1): memory cells

SL ₁ ~SL _(N+1) : Common source line

WL ₁ ~WL _N : word line

SL' ₃ ~SL' _(N-1) , SL" ₃ ~SL" _(N-1) : Common source line

BL ₁ ~BL _(2N+2) : Bit line

1100: Memory device

1110, 1120, 1130: memory subarray

1200: Memory device

1210-1~1210-M, 1220-1~1220-M, 1230-1~1230-M: memory subarray

1240: Arithmetic unit

1250:Conversion unit

1300: Memory device

1310-1~1310-M, 1320-1~1320-M, 1330-1~1330-M: memory subarray

1340: Arithmetic unit

1350:Conversion unit

1360:Switching circuit

1400: Memory device

1410-1~1410-M, 1420-1~1420-M, 1430-1~1430-M: memory subarray

1440-1~1440-3: Arithmetic unit

1450-1~1450-3: Conversion unit

1460:Switching circuit

M0, M1…Mn: metal layer

1610-1675: Steps

1710-1730: Steps

Figures 1A and 1B show schematic diagrams of the Yixin model with input values.

Figure 2A shows a schematic diagram of energy calculation using the Yixin model.

Figure 2B shows a schematic diagram of using the Yixin model to simulate quantum annealing.

Figure 3 shows a circuit diagram of a memory cell in an embodiment of the present invention.

Figures 4A to 4D show schematic diagrams of the operation of a memory cell according to an embodiment of the present invention.

Figure 5 shows a circuit diagram of a memory cell in an embodiment of the present invention.

Figures 6A to 6H show schematic diagrams of the operation of a memory cell according to an embodiment of the present invention.

FIG. 7 is a schematic diagram showing the operation of using memory cells to calculate local energy ^Li according to an embodiment of the present invention.

Figures 8A and 8B show the determination coefficient according to an embodiment of the present case.

Figure 9A shows a schematic diagram of the programmed operation according to an embodiment of the present invention.

Figure 9B shows a schematic diagram of an erase operation according to an embodiment of the present invention.

Figure 10 shows a circuit diagram of a memory device according to an embodiment of the present invention.

Figure 11 shows a circuit diagram of a memory device according to an embodiment of the present invention.

Figure 12 shows a circuit diagram of a memory device according to an embodiment of the present invention.

Figure 13 shows a circuit diagram of a memory device according to an embodiment of the present invention.

Figure 14 shows a circuit diagram of a memory device according to an embodiment of the present invention.

Figures 15A and 15B show schematic diagrams of connecting memories in series.

Figure 16 is a flow chart of the operation method of the memory device of an embodiment of the present invention.

Figure 17 shows a flow chart of the operation method of the memory device according to an embodiment of the present invention.

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

FIG. 1A and FIG. 1B are schematic diagrams of an Ising model with a spin state. Please refer to FIG. 1A first. The Ising model has two input values σ ₁ and σ ₂ , wherein the first input value σ ₁ is the first spin state of the Ising model, and the second input value σ ₂ is the second spin state. The first input value σ ₁ is a logical value "1" indicating that the spin state is "positive spin" (the upward arrow in FIG. 1A ), and the second input value σ ₂ is a logical value "0" indicating that the spin state is "reverse spin" (the downward arrow in FIG. 1A ). The first input value σ ₁ has a self-power coefficient h ₁ , and the second input value σ ₂ has a self-power coefficient h ₂ , and there is an interaction coefficient J ₁₂ between the two input values σ ₁ and σ ₂ .

Furthermore, referring to FIG. 1B , an Yixin model having three input values σ ₁ , σ ₂ and σ ₃ is taken as an example, and the logical values of the input values σ ₁ , σ ₂ , σ ₃ are, for example, "1, 0, 0". The input values σ ₁ , σ ₂ , σ ₃ have self-power coefficients h ₁ , h ₂ , h ₃ , respectively; and, there is an interaction coefficient J ₁₂ between the input values σ ₁ , σ ₂ , an interaction coefficient J ₁₃ between the input values σ ₁ , σ ₃ , and an interaction coefficient J ₂₃ between the input values σ ₂ , σ ₃ .

FIG. 2A is a schematic diagram showing the calculation of energy using the Yi Xin model. Referring to FIG. 2A, the Yi Xin model can be used to calculate a cost function and locate the minimum value of the cost function. For example, the Yi Xin model uses the energy H of a specific material (e.g., a magnetic material) as the cost function and locates the minimum energy H _min . Taking the Yi Xin model with two input values σ ₁ and σ ₂ in FIG. 1A as an example, according to the Yi Xin model operation shown in formula (1), different logical values of the input values σ ₁ and σ ₂ corresponding to different values of energy H can be calculated: H=Σ _{i =1~2} h _i σ _i +Σ _{i < j} J _ij (σ _i ＊σ _j )=h ₁ σ ₁ +h ₂ σ ₂ +J ₁₂ (σ ₁ *σ ₂ ) (1)

The operator "*" in formula (1) represents a logical exclusive negative OR (XNOR) operation. If the input values σ _i and σ _j are the same logical value (for example, "1, 1" or "0, 0"), the result of the logical "XNOR" operation is "1". If the input values σ _i and σ _j are different logical values (for example, "1, 0" or "0, 1"), the result of the logical "XNOR" operation is "0". In the embodiment shown in FIG. 2A, according to the operation of formula (1), it can be located that when the input values σ ₁ and σ ₂ are the logical values "1, 1", this material has the lowest energy H _min . Similarly, if the Yi Xin model has three input values σ ₁ , σ ₂ , σ ₃ , the energy H can be calculated according to the Yi Xin model of equation (2): H = h ₁ σ ₁ +h ₂ σ ₂ +h ₃ σ ₃ +J ₁₂ (σ ₁ *σ ₂ )+J ₁₃ (σ ₁ *σ ₃ ) +J ₂₃ (σ ₂ *σ ₃ ) (2)

FIG. 2B is a schematic diagram of using the I-Sim model operation to simulate quantum annealing. Referring to FIG. 2B , a computing device (e.g., a complementary metal oxide semiconductor (CMOS) semiconductor device) can perform I-Sim model operations to simulate quantum annealing to locate the minimum value (minimum energy H _min ) of the cost function (energy H). The I-Sim model operation of the embodiment of FIG. 2B , for example, has N input values σ ₁ , σ ₂ , ..., σ _N , and the input values σ ₁ , σ ₂ , ..., σ _N of different logical values correspond to different configurations 200 , 202 , 204 , and 206 , etc. Among them, configuration 200 indicates that the input values σ ₁ , σ ₂ , ..., σ _N are logical values "0, 1, ..., 1", and configuration 204 indicates that the input values σ ₁ , σ ₂ , ..., σ _N are logical values "1, 1, ..., 0", and so on. The moving path of the Yixin model operation is as follows: it can move from configuration 200 to configuration 202 and then to configuration 204, and then locate the configuration 204 with the lowest energy H _min . On the other hand, the quantum annealing operation moves from configuration 206 to configuration 204 and locates the lowest energy H _min . From the above, the result of the operation device executing the Yixin model operation is the same as the result of the quantum annealing operation.

The energy difference △H of the Yixin model can be expressed as follows (3): △ H = H ( -σi ₎ -H ( σi ₎ ( 3)

(4-1) The energy difference △H between the second-order and third-order Yi Xin models can be expressed as follows (4-1) and (4-2):

(4-1)

From the above equations (4-1) and (4-2), we can see that the energy difference is related to the input value σ and the local energy (local field).

與2階局部能 量

可表示如下式(5-1)與(5-2)：

For example, in the above formula (4-1), the first-order local energy

and the second-order local energy

It can be expressed as the following equations (5-1) and (5-2):

、2階局部能量

與 3階局部能量

可表示如下式(6-1)、(6-2)與(6-3)：

In the above formula (4-2), the first-order local energy

, second-order local energy

and the third-order local energy

It can be expressed as the following equations (6-1), (6-2) and (6-3):

After obtaining the local energy, it can be used to decide whether to flip the spin state (i.e., whether to flip the input value) or whether to update the spin state (i.e., whether to update the input value) to obtain the best solution.

An embodiment of this case discloses a method of using a semiconductor memory device to calculate local energy to process Yixin model operations.

FIG. 3 shows a circuit diagram of a memory cell 30 of an embodiment of the present invention. The memory cell 30 includes a first transistor Ma and a second transistor Mb. Here, for example but not limited to, the first transistor Ma is an N-type transistor, and the second transistor Mb is a P-type transistor.

The first gate Ga of the first transistor Ma receives a gate voltage V _G , the first drain Da receives a first drain voltage V _D1 , the second gate Gb of the second transistor Mb receives a gate voltage V _G , the second drain Db receives a second drain voltage V _D2 , and the first source Sa of the first transistor Ma and the second source Sb of the second transistor Mb are directly connected to each other in a common source connection manner.

From the perspective of logical operation, the gate voltage V _G can be corresponded to the input value σ _j of the Yi Xin model, where the parameter "j" represents the j-th input value σ _j (i.e., the j-th spin state of the Yi Xin model). When the input value σ _j is a logical value "+1", the gate voltage V _G is a first gate voltage V _GN to turn on the first transistor Ma; and, when the input value σ _j is a logical value "-1", the gate voltage V _G is a second gate voltage -V _GP to turn on the second transistor Mb.

Similarly, the first drain voltage V _D1 and the second drain voltage V _D2 correspond to the input value σ _k , where the parameter "k" represents the k-th input value σ _k (i.e., the k-th spin state of the Yishin model). When the input value σ _k is a logical value "+1", the first drain voltage V _D1 and the second drain voltage V _D2 are voltage values +V _DN and -V _DP , respectively; and, when the input value σ _k is a logical value "-1", the first drain voltage V _D1 and the second drain voltage V _D2 are voltage values -V _DN and +V _DP , respectively.

From the perspective of logical operation, the source current I _S of the memory cell 30 can be expressed as I _S =Jσ _j σ _k .

FIG. 4A to FIG. 4D are schematic diagrams showing the operation of the memory cell 30 according to an embodiment of the present invention. As shown in FIG. 4A, when the input value σ _j is a logical value "+1" and the input value σ _k is a logical value "+1", the source current I _S of the memory cell 30 is =Jσ _j σ _k =+J. As shown in FIG. 4B, when the input value σ _j is a logical value "+1" and the input value σ _k is a logical value "-1", the source current I _S of the memory cell 30 is =Jσ _j σ _k =-J. As shown in FIG. 4C, when the input value σ _j is a logical value "-1" and the input value σ _k is a logical value "+1", the source current I _S of the memory cell 30 is =Jσ _j σ _k =-J. As shown in FIG. 4D , when the input value σ _j is a logical value “-1” and the input value σ _k is a logical value “-1”, the source current I _S =Jσ _j σ _k =+J of the memory cell 30. The direction of the positive current is defined as flowing from the drain to the source, and the direction of the negative current is defined as flowing from the source to the drain.

In an embodiment of the present case, when the input value σ _k is fixed to the logical value "+1", the source current I _S =Jσ _j σ _k =Jσ _j of the memory cell 30, as shown in FIGS. 4A and 4C .

In an embodiment of the present case, when the input value σ _j and the input value σ _k are the same value, the source current I _S =Jσ _j σ _k =J of the memory cell 30, as shown in FIG. 4A and FIG. 4D .

Therefore, it can be seen from FIG. 3 and FIG. 4A to FIG. 4D that I _S =J (J is a constant), I _S =Jσ _j and I _S =Jσ _j σ _k can be realized through the memory cell 30.

FIG. 5 shows a circuit diagram of a memory cell 50 according to an embodiment of the present invention. The memory cell 50 includes two memory cells 30 connected in series. As shown in FIG. 5 , two drains of the other memory cell 30 receive a third drain voltage V _D3 and a fourth drain voltage V _D4 , respectively. The third drain voltage V _D3 and the fourth drain voltage V _D4 correspond to an input value σ _l , where the parameter “l” represents the lth input value σ _l (i.e., the lth spin state of the Yishin model). When the input value σ _l is a logic value "+1", the third drain voltage V _D3 and the fourth drain voltage V _D4 are voltage values +V _DN and -V _DP respectively; and, when the input value σ _l is a logic value "-1", the third drain voltage V _D3 and the fourth drain voltage V _D4 are voltage values -V _DN and +V _DP respectively. From the perspective of logical operation, the source current I _S of the memory cell 50 can be expressed as I _S =Jσ _j σ _k σ _l . When connected in series, the common source of one of the memory cells 30 is coupled to the gate of another of the memory cells 30.

FIG. 6A to FIG. 6H are schematic diagrams showing the operation of the memory cell 50 according to an embodiment of the present invention. As shown in FIG. 6A , when the input value σ _j is a logical value "+1", the input value σ _k is a logical value "+1", and the input value σ _l is a logical value "+1", the source current I _S of the memory cell 50 is =Jσ _j σ _k σ _l =+J. As shown in FIG. 6B , when the input value σ _j is a logical value "+1", the input value σ _k is a logical value "-1", and the input value σ _l is a logical value "+1", the source current I _S of the memory cell 50 is =Jσ _j σ _k σ _l =-J. As shown in FIG6C, when the input value _σj is a logical value "+1", the input value _σk is a logical value "+1", and the input value _σl is a logical value "-1", the source current I _S of the memory cell 50 is = _{Jσj σk σl} =-J. As shown in FIG6D, when the input value _σj is a logical value "+1", the input value _σk is a logical value "-1", and the input value _σl is a logical value "-1", the source current I _S of the memory cell 50 _{is =Jσj σk σl = +} J. As shown in FIG. 6E, when the input value σ _j is a logical value "-1", the input value σ _k is a logical value "+1", and the input value σ _l is a logical value "+1", the source current I _S of the memory cell 50 is =Jσ _j σ _k σ _l =-J. As shown in FIG. 6F, when the input value σ _j is a logical value "-1", the input value σ _k is a logical value "-1", and the input value σ _l is a logical value "+1", the source current I _S of the memory cell 50 is =Jσ _j σ _k σ _l =+J. As shown in FIG6G, when the input value _σj is a logical value "-1", the input value _σk is a logical value "+1", and the input value _σl is a logical value "-1", the source current I _S of the memory cell 50 is =Jσj _{σk σl} =+J. As shown in FIG6H, when the input value _σj is a logical value "-1", the input value _σk is a logical value "-1" _, and the input value _σl is a logical value "-1", the source current I _S of the memory cell 50 is = _{Jσj σk σl} =-J.

Therefore, it can be seen from the above that in one embodiment of the present invention, by connecting more stages of memory cells 30 in series, it can be obtained that the source current _IS of the memory cell can be related to more stages of input values.

In one embodiment of the present invention, the local energy _Li associated with the input value _σi can be expressed as follows:

可 利用單階的記憶胞30來求得。如第4A圖與第4B圖，1階局部 能量

可利用單階的記憶胞30來求得。如第4A圖與第4B圖， 2階局部能量

可利用單階的記憶胞30來求得。同樣地，如第5 圖所示，3階局部能量

可利用兩階串聯記憶胞30來求得。由此 類推，更高階的局部能量

可利用更多階串聯記憶胞30來求得。 如第7圖所示，輸入值σ_r乃是對應到汲極電壓V_D(2n-3)與汲極電 壓V_D(2n-2)；以及，輸入值σ_s乃是對應到汲極電壓V_D(2n-1)與汲極電壓V_D2n。 FIG. 7 is a schematic diagram showing the operation of using the memory cell 30 to calculate the local energy _Li according to an embodiment of the present invention. As shown in FIG. 4A and FIG. 4B, the constant

It can be obtained using a single-order memory cell 30. As shown in Figures 4A and 4B, the first-order local energy

It can be obtained using a single-order memory cell 30. As shown in Figures 4A and 4B, the second-order local energy

can be obtained using a single-order memory cell 30. Similarly, as shown in FIG5 , the third-order local energy

It can be obtained by using two-order cascade memory cells 30. By analogy, the higher-order local energy

It can be obtained by using more order series memory cells 30. As shown in FIG. 7 , the input value σ _r corresponds to the drain voltage V _{D (2n-3)} and the drain voltage V _{D (2n-2)} ; and the input value σ _s corresponds to the drain voltage V _{D (2n-1)} and the drain voltage V _D2n .

Now, it will be described how to determine the value of coefficient J in an embodiment of the present invention. FIG. 8A and FIG. 8B show the determination of coefficient J according to an embodiment of the present invention. In an embodiment of the present invention, the value of coefficient J can be determined by adjusting the critical voltage of the first transistor Ma and the second transistor Mb.

As shown in FIG. 8A , when the critical voltage V _TN of the N-type transistor (such as the first transistor Ma) and the critical voltage V _TP of the P-type transistor (such as the second transistor Mb) are the reference critical voltages V _L and -V _L , respectively, the coefficient J is 1. When the gate voltage V _G =V _GN , the N-type transistor (such as the first transistor Ma) is turned on and the P-type transistor is turned off. When the gate voltage V _G =-V _GP , the N-type transistor (such as the first transistor Ma) is turned off and the P-type transistor is turned on.

As shown in FIG. 8B , when the critical voltage V _TN of the N-type transistor (such as the first transistor Ma) and the critical voltage V _TP of the P-type transistor (such as the second transistor Mb) are the reference critical voltages V _H and -V _H , respectively, the coefficient J is 0, where V _H >V _L . When the gate voltage V _G =V _GN , both the N-type transistor and the P-type transistor are turned off. When the gate voltage V _G =-V _GP , both the N-type transistor and the P-type transistor are turned off.

Figures 8A and 8B show the case where the coefficient J has two orders, but the present invention is not limited thereto. In other possible embodiments of the present invention, by fine-tuning the critical voltage of the N-type transistor and/or the P-type transistor, J can have more orders, or can be an analog value.

FIG. 9A shows a schematic diagram of a programming operation according to an embodiment of the present invention. FIG. 9B shows a schematic diagram of an erase operation according to an embodiment of the present invention.

As shown in FIG. 9A , when programming is performed, a positive voltage is applied to the gate (+V _G ) and a positive voltage is applied to the first drain voltage (+V _D1 ), and 0V is applied to the second drain voltage and the output terminal (V _D2 =V _out =0), which can form a channel hot electron effect (CHE) to change the critical voltage V _TN of the N-type transistor (such as the first transistor Ma) from the reference critical voltage V _L to the reference critical voltage V _H to program the N-type transistor; and a negative voltage is applied to the gate (-V _G ) and a negative voltage is applied to the second drain voltage (-V _D2 ), and 0V is applied to the first drain voltage and the output terminal (V _D1 =V _out =0), a channel hot hole effect (CHH) can be formed to change the critical voltage V _TP of the P-type transistor (such as the second transistor Mb) from the reference critical voltage -V _L to the reference critical voltage -V _H to program the P-type transistor.

As shown in FIG. 9B , when erasing, a negative voltage (-V _G ) is applied to the gate and a positive voltage (+V _D1 ) is applied to the first drain voltage, and 0V is applied to the second drain voltage and the output terminal (V _D2 =V _out =0), which can form a band-to-band tunneling hot hole injection effect (BBTHHI) to change the critical voltage V _TN of the N-type transistor (such as the first transistor Ma) from the reference critical voltage V _H to the reference critical voltage V _L to erase the N-type transistor; and, a positive voltage (+V _G ) is applied to the gate and a negative voltage is applied to the second drain voltage (-V _D2 ), and applying 0V to the first drain voltage and the output terminal (V _D1 =V _out =0), a band to band tunneling hot electron injection (BBTHEI) effect can be formed to change the critical voltage V _TP of the P-type transistor (such as the second transistor Mb) from the reference critical voltage -V _H to the reference critical voltage -V _L to erase the P-type transistor.

FIG. 10 shows a circuit diagram of a memory device according to an embodiment of the present invention. As shown in FIG. 10 , the memory device 1000 includes: a memory array 1005, an operation unit 1020, a conversion unit 1030, a bit line driver 1040, and a word line driver 1050. Here, the memory device 1000 can calculate the local energy L ₁ (as shown in the following formula (8)) as an example for explanation. Those who are familiar with this technology should know how to use it to calculate other local energies, or calculate higher-order local energies.

The memory array 1005 includes a memory sub-array 1010. The memory sub-array 1010 includes a plurality of memory cells 1-1 to N-(N+1), a plurality of common source lines SL ₁ to SL _(N+1) (first signal lines), a plurality of word lines WL ₁ to WL _N (second signal lines), and a plurality of bit lines BL ₁ to BL _(2N+2) (third signal lines). The memory cells 1-1 to N-(N+1) arranged in an array may be implemented by the memory cell 30. The common source lines SL ₁ to SL _(N+1) are coupled to the source terminals of the memory cells 1-1 to N-(N+1), the word lines WL ₁ to WL _N are coupled to the gate terminals of the memory cells 1-1 to N-(N+1), and the bit lines BL ₁ to BL _(2N+2) are coupled to the first drain terminals and the second drain terminals of the memory cells 1-1 to N-(N+1). The common source lines SL ₃ to SL _(N-1) are electrically isolated into two parts based on a diagonal line of the memory array 1005, so that the common source lines SL” ₃ to SL” _(N-1) in the upper part are electrically isolated from the common source lines SL' ₃ to SL' _(N-1) in the lower part.

The operation unit 1020 is coupled to the memory sub-array 1010 to calculate a plurality of source currents transmitted from the memory sub-array 1010 to generate an operation result. For example but not limited to, the operation unit 1020 is a subtractor.

The conversion unit 1030 is coupled to the operation unit 1020 to convert the operation result of the operation unit 1020 to generate local energy. For example but not limited to, the conversion unit 1030 is an analog-to-digital converter (ADC).

The bit line driver 1040 is coupled to the memory sub-array 1010 for driving the bit lines BL ₁ -BL _(2N+2) .

The word line driver 1050 is coupled to the memory sub-array 1010 for driving word lines WL ₁ -WL _N .

As shown in FIG. 10 , the word line driver 1050 outputs gate voltages related to input values σ ₂ to σ _N to the gates of the memory cells 1-1 to N-(N+1). Similarly, the bit line driver 1040 outputs drain voltages related to input values σ ₁ (=logic value “+1”), input values σ ₂ to σ _N , and input value σ ₁ (=logic value “+1”) to the first drain and the second drain of the memory cells 1-1 to N-(N+1).

。相似地，記憶胞N-N的閘極電壓、第一汲極電壓與第二汲極電壓皆相關於輸入值σ_N，故而，記憶胞N-N的 源極電流為

。故而，將記憶胞1-2的源極電流(

) 相減於記憶胞N-N的源極電流(

)可以得到：

。 As shown in FIG. 10 , the gate voltage, the first drain voltage, and the second drain voltage of the memory cell 1-2 are all related to the input value σ ₂ . Therefore, the source current of the memory cell 1-2 is

Similarly, the gate voltage, first drain voltage and second drain voltage of memory cell NN are all related to the input value σ _N , so the source current of memory cell NN is

Therefore, the source current of memory cell 1-2 (

) is less than the source current of the memory cell NN (

) can be obtained:

.

。相似地， 記憶胞2-1的閘極電壓相關於輸入值σ₃、記憶胞2-1的第一汲極電壓與第二汲極電壓皆相關於輸入值σ₁(=邏輯值「+1」)，故而， 記憶胞2-1的源極電流為

。其餘記憶胞3-1~N-1的源 極電流可依此類推。由於共源極線SL₁共同耦接至該些記憶胞1-1~N-1的源極，故而，可得知共源極線SL₁上的共源極電流為：

。依此類推，由於共源極線SL_(N+1)共同耦接至該些記 憶胞1-(N+1)~N-(N+1)的源極，故而，可得知共源極線SL_(N+1) 上的共源極電流為：

。將共源極線SL₁上的共源極電流 (

)相減於共源極線SL_(N+1)上的共源極電流 (

)可以得到：

。 The gate voltage of memory cell 1-1 is related to the input value σ ₂ , and the first drain voltage and the second drain voltage of memory cell 1-1 are both related to the input value σ ₁ (= logical value "+1"). Therefore, the source current of memory cell 1-1 is

Similarly, the gate voltage of the memory cell 2-1 is related to the input value σ ₃ , and the first drain voltage and the second drain voltage of the memory cell 2-1 are both related to the input value σ ₁ (= logical value “+1”). Therefore, the source current of the memory cell 2-1 is

The source currents of the remaining memory cells 3-1 to N-1 can be deduced in the same way. Since the common source line _SL1 is commonly coupled to the sources of the memory cells 1-1 to N-1, it can be known that the common source current on the common source line _SL1 is:

By analogy, since the common source line SL _(N+1) is commonly coupled to the sources of the memory cells 1-(N+1) to N-(N+1), it can be known that the common source current on the common source line SL _(N+1) is:

. The common source current on the common source line _SL1 (

) is subtracted from the common source current on the common source line SL _(N+1) (

) can be obtained:

.

。相似地，記憶胞N-2 的閘極電壓相關於輸入值σ_N、記憶胞N-2的第一汲極電壓與第二汲極電壓皆相關於輸入值σ₂，故而，記憶胞N-2的源極電流為

。其餘記憶胞3-2~(N-1)-2的源極電流可依此類推。 由於共源極線SL₂共同耦接至該些記憶胞2-2~N-2的源極，故而， 可得知共源極線SL₂上的共源極電流為：

。依此類推， 由於共源極線SL_N共同耦接至該些記憶胞1-N~(N-1)-N的源極， 故而，可得知共源極線SL_N上的共源極電流為：

。將 共源極線SL₂上的共源極電流(

)相減於共源極線SL_N 上的共源極電流(

)可以得到：

。 Similarly, the gate voltage of the memory cell 2-2 is related to the input value σ ₃ , and the first drain voltage and the second drain voltage of the memory cell 2-2 are both related to the input value σ ₂ . Therefore, the source current of the memory cell 2-2 is

Similarly, the gate voltage of memory cell N-2 is related to the input value σ _N , and the first drain voltage and the second drain voltage of memory cell N-2 are both related to the input value σ ₂ . Therefore, the source current of memory cell N-2 is

The source currents of the remaining memory cells 3-2 to (N-1)-2 can be deduced in the same way. Since the common source line _SL2 is commonly coupled to the sources of the memory cells 2-2 to N-2, it can be known that the common source current on the common source line _SL2 is:

By analogy, since the common source line SL _N is commonly coupled to the sources of the memory cells 1-N to (N-1)-N, it can be known that the common source current on the common source line SL _N is:

. The common source current on the common source line _SL2 (

) is subtracted from the common source current on the common source line SL _N (

) can be obtained:

.

By analogy, the common source currents on the common source lines SL ₁ to SL _(N+1) can be obtained.

Since the common source currents on the common source lines SL ₁ to SL _(N+1) are all input to the operation unit 1020, the operation unit 1020 can obtain local energy.

The conversion unit 1030 can further convert the local energy _L1 into a digital signal.

In FIG. 10 , the memory subarray 1010 can be viewed as being divided into two parts, the first part being used to store the first part coefficient J ⁽⁺⁾ of the interaction coefficient J (such as J ₁ ⁽¹⁺⁾ , J ₁₂ ⁽²⁺⁾ , etc.), and the second part being used to store the second part coefficient J ^(-) of the interaction coefficient J (such as J ₁ ^(1-) , J ₁₂ ^(2-) , etc.), so as to obtain the full range of the interaction coefficient J=J ⁽⁺⁾ +J ^(-) . As described above, the critical voltages of the N-type transistor and the P-type transistor can be adjusted by an erase or programming operation to change the first part coefficient J ⁽⁺⁾ of the interaction coefficient J and the second part coefficient J ^(-) of the interaction coefficient J.

The first part of the memory sub-array 1010 is used to calculate _{the first part of the local energy L 1 (} ⁺⁾ , and the second part of the memory sub-array 1010 is used to calculate the second part of the local energy _{L 1 (} ^-) to obtain the local energy L ₁ =L ₁ ⁽⁺⁾ +L ₁ ^(-) .

In addition, in FIG. 10 , the first portion of the memory sub-array 1010 and the second portion of the memory sub-array 1010 are electrically isolated.

FIG. 11 shows a circuit diagram of a memory device according to an embodiment of the present invention. In FIG. 11, the memory array of the memory device 1100 includes: a first memory sub-array 1110, a second memory sub-array 1120, and a third memory sub-array 1130. The first memory sub-array 1110 and the second memory sub-array 1120 can be regarded as equivalent to the memory sub-array 1010 of the memory device 1000 shown in FIG. 10. Of course, the memory device 1100 can further include: an operation unit, a conversion unit, a bit line driver, a word line driver and other components.

The first memory sub-array 1110 can be used to store the first-order coefficient J ₁ ⁽¹⁾ (=J ₁ ⁽¹⁺⁾ +J ₁ ^(1-) ) and the third-order coefficient J ₃ ⁽³⁾ (=J ₃ ⁽³⁺⁾ +J ₃ ^(3-) ), that is, the first memory sub-array 1110 can be used to store a plurality of single-order interaction coefficients. That is, the first memory sub-array 1110 can be regarded as equivalent to the memory cells 1-2~1-N, 2-2~2-N, ... N-2~NN in FIG. 10. The first memory sub-array 1110 is located at the diagonal position of the memory array.

The second memory sub-array 1120 can be used to store the second-order coefficient J ₂ ⁽²⁾ (=J ₂ ⁽²⁺⁾ +J ₂ ^(2-) ). That is, the second memory sub-array 1120 can be used to store a plurality of even-order interaction coefficients. The second memory sub-array 1120 can be regarded as equivalent to the memory cells 1-1 to N-1 and 1-(N+1) to N-(N+1) in FIG. 10 . The second memory sub-array 1120 is located on both sides of the memory array.

The plurality of memory cells in the third memory sub-array 1130 are programmed to have high critical voltages ( _VH and _-VH ) for both N-type transistors and P-type transistors, that is, the memory cells in the third memory sub-array 1130 are closed in normal operation. The third memory sub-array 1130 is located between the diagonal of the memory array and the two sides of the memory array.

The memory device 1100 of FIG. 11 has scalability of the array, i.e. mapping coefficients of a low spin-count with a small partition in a large array.

FIG12 is a circuit diagram of a memory device according to an embodiment of the present invention. In FIG12, the memory device 1200 includes: a plurality of first memory sub-arrays 1210-1 to 1210-M, a plurality of second memory sub-arrays 1220-1 to 1220-M, and a plurality of third memory sub-arrays 1230-1 to 1230-M. Among them, the first memory sub-array 1210-1, the second memory sub-array 1220-1 and the third memory sub-array 1230-1 belong to the first group, and the first memory sub-array 1210-2, the second memory sub-array 1220-2 and the third memory sub-array 1230-2 belong to the second group, and the rest can be deduced in the same way. The first memory sub-array 1210-M, the second memory sub-array 1220-M and the third memory sub-array 1230-M belong to the Mth group.

Of course, the memory device 1200 may further include: an operation unit 1240, a conversion unit 1250, a bit line driver, a word line driver and other components.

Each of the first memory sub-arrays 1210-1 to 1210-M can be used to store a first-order coefficient J ₁ ⁽¹⁾ (=J ₁ ⁽¹⁺⁾ +J ₁ ^(1-) ) and a third-order coefficient J ₃ ⁽³⁾ (=J ₃ ⁽³⁺⁾ +J ₃ ^(3-) ). That is, the first memory sub-arrays 1210-1 to 1210-M can be used to store a plurality of single-order interaction coefficients. Each of the first memory sub-arrays 1210-1 to 1210-M is considered to be equivalent to the first memory sub-array 1110 in FIG. 11 . Each of the first memory sub-arrays 1210-1 to 1210-M is located at a diagonal position of the memory array.

Each of the second memory sub-arrays 1220-1 to 1220-M can be used to store a second-order coefficient J ₂ ⁽²⁾ (=J ₂ ⁽²⁺⁾ +J ₂ ^(2-) ). That is, the second memory sub-arrays 1220-1 to 1220-M can be used to store a plurality of even-order interaction coefficients. Each of the second memory sub-arrays 1220-1 to 1220-M is considered to be equivalent to the second memory sub-array 1120 in FIG. 11 . The second memory sub-arrays 1220-1 to 1220-M are located on both sides of the memory array.

Each of the third memory sub-arrays 1230-1 to 1230-M is considered to be equivalent to the third memory sub-array 1130 in FIG. 11. The memory cells in the third memory sub-arrays 1230-1 to 1230-M are closed under normal operation. The third memory sub-arrays 1230-1 to 1230-M are located between the diagonal of the memory array and the two sides of the memory array.

In Figure 12, during the calculation, the first to Mth groups can be calculated independently, and local energy calculations are performed group by group. That is, only one group performs local energy calculations at the same time. In other words, the input value is input to the selected group, and the input value is not input to the unselected group.

The word lines corresponding to the unselected groups can be grounded (0V), and the bit lines corresponding to the unselected groups can be floating or grounded.

The memory device 1200 of FIG. 12 can be considered as an extension of the memory device 1100 of FIG. 11.

FIG. 13 shows a circuit diagram of a memory device according to an embodiment of the present invention. In FIG. 13, the memory device 1300 includes: a plurality of first memory sub-arrays 1310-1~1310-M, a plurality of second memory sub-arrays 1320-1~1320-M and a plurality of third memory sub-arrays 1330-1~1330-M. Of course, the memory device 1300 may further include: an operation unit 1340, a conversion unit 1350, a bit line driver, a word line driver and other components. In addition, the memory device 1300 further includes: a switch circuit 1360 coupled to the common source lines.

The first memory sub-arrays 1310-1~1310-M, the second memory sub-arrays 1320-1~1320-M, the third memory sub-arrays 1330-1~1330-M, the operation unit 1340, and the conversion unit 1350 can be as described above and will not be repeated here.

In Figure 13, the input value is input to all groups, and the switch circuit 1360 selects the common source pole to select which group to output the local energy. Similarly, only one group can be selected at a time for local energy calculation.

FIG. 14 shows a circuit diagram of a memory device according to an embodiment of the present invention. In FIG. 14 , the memory device 1400 includes: a plurality of first memory sub-arrays 1410-1 to 1410-M, a plurality of second memory sub-arrays 1420-1 to 1420-M, and a plurality of third memory sub-arrays 1430-1 to 1430-M. Of course, the memory device 1400 may further include: a plurality of operation units 1440-1 to 1440-3, a plurality of conversion units 1450-1 to 1450-3, a bit line driver, a word line driver, and other components. In addition, the memory device 1400 further includes: Switch circuit 1460, coupled to the common source lines.

The first memory sub-arrays 1410-1~1410-M, the second memory sub-arrays 1420-1~1420-M, the third memory sub-arrays 1430-1~1430-M, the operation units 1440-1~1440-3 and the conversion units 1450-1~1450-3 can be as described above and will not be repeated here.

In FIG. 14, the switch circuit 1460 selects the common source line to select one or more groups to output local energy. Taking FIG. 14 as an example, since there are three operation units 1440-1~1440-3 and three conversion units 1450-1~1450-3, a maximum of three groups can be selected at a time to output local energy.

In the above-mentioned embodiment of the present case, the N-type transistor and the P-type transistor of the memory cell 30 are, for example but not limited to, floating gate devices, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) thin film transistors, ferroelectric field effect transistors (FeFET), etc.

Figures 15A and 15B show schematic diagrams of connecting memory cells in series in one embodiment of the present invention. As shown in Figure 15A, through three-dimensional integration, multiple memory cells on different metal layers (M0, M1...Mn) can be connected in series.

As shown in Figure 15B, when connecting memory cells in series, the control signal line (CSL) is inserted between different metal layers (M0, Mn) through three-dimensional integration to achieve an effective programming and erasing design, in which the memory cells in the top layer (Mn) do not need to be programmed and erased.

FIG. 16 is a flow chart of the operation method of the memory device of an embodiment of the present invention. The operation method can be applied to the above-mentioned memory device. In step 1610, the configuration of the plurality of input values (σ ₁ ...) for the model operation is initialized. In step 1620, it is determined whether the update status of the input values converges. If the result of the determination is convergence, the optimized configuration of the input values is obtained (step 1625), and the operation method can be terminated. If the result of the determination is not converged, step 1630 is performed to randomly select an input value from the input values.

In step 1640, the selected input value is flipped. In step 1650, it is determined whether the energy difference (ΔH _i ) associated with the selected input value is less than 0. If the energy difference (ΔH _i ) is less than 0, the input value flip is accepted (step 1665). If the energy difference (ΔH _i ) is not less than 0, in step 1660, it is determined whether exp(-(ΔH _i /T)) is greater than a random value (the random value is between 0 and 1), where the parameter T represents temperature.

If step 1660 is yes, the process goes to step 1665. If step 1660 is no, the process goes to step 1670 to reject the input value flip. In step 1675, the input values are updated.

FIG. 17 is a flow chart showing an operation method of a memory device according to an embodiment of the present invention. The operation method can be applied to the above-mentioned memory device. The operation method of the memory device is used to process a model operation having a plurality of input values and a plurality of interaction coefficients. The operation method includes: storing a plurality of first part coefficients of the interaction coefficients in a first part of a plurality of memory cells of at least one memory sub-array of a memory array of the memory device, storing a plurality of second part coefficients of the interaction coefficients in a second part of the memory cells, wherein the first part of the memory cells and the second part of the memory cells are electrically isolated based on a diagonal of the memory array (1710); inputting the input values to the memory cells, the memory cells generating a plurality of source currents, The source currents flow through a plurality of first signal lines of the memory device to generate a plurality of common source currents, the first part of the memory cells generates a first part of the common source currents, and the second part of the memory cells generates a second part of the common source currents (1720); and a first part of a local energy of the model operation is calculated based on the first part of the common source currents, and a second part of the local energy of the model operation is calculated based on the second part of the common source currents (1730).

The above-mentioned embodiments of this case can quickly execute complex model operations through hardware design, reducing the time and energy consumption of model operations. When the dimension of the Yixin model is larger and has a larger number of spin states, the embodiments of this case can still complete the operation quickly.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

1710-1730: Steps

Claims (10)

A memory device includes: a memory array for processing a model operation, the model operation having a plurality of input values and a plurality of interaction coefficients, the memory array including at least one memory sub-array, the at least one memory sub-array including: a plurality of memory cells, and a plurality of first signal lines, a plurality of second signal lines, and a plurality of third signal lines coupled to the memory cells. memory cells; and at least one operation unit coupled to the at least one memory sub-array, wherein the memory cells receive the input values via the second signal lines and the third signal lines, the memory cells generate a plurality of source currents, the source currents flow through the first signal lines to generate a plurality of common source currents, the common source currents are sent to the at least one operation unit, the memory cells A first part of the memory cells generates a first part of the common source currents, and a second part of the memory cells generates a second part of the common source currents; the first part of the memory cells stores a plurality of first part coefficients of the interaction coefficients, and the second part of the memory cells stores a plurality of second part coefficients of the interaction coefficients, wherein the first part of the memory cells and the second part of the memory cells are electrically isolated based on a diagonal of the memory array; and the at least one operation unit calculates a first part of a local energy of the model operation according to the first part of the common source currents, and calculates a second part of the local energy of the model operation according to the second part of the common source currents. The memory device as claimed in claim 1, wherein the at least one memory subarray comprises: a first memory subarray, the first memory subarray being used to store a plurality of single-order interaction coefficients, the first memory subarray being located on a diagonal of the memory array; a second memory subarray, the second memory subarray being The second memory sub-array is used to store a plurality of even-order interaction coefficients, and the second memory sub-array is located at both sides of the memory array; and a third memory sub-array is closed under normal operation, and the third memory sub-array is located between the diagonal line of the memory array and the two sides of the memory array. A memory device as described in claim 1, wherein the at least one memory subarray comprises: a plurality of first memory subarrays, the first memory subarrays are used to store a plurality of single-order interaction coefficients, the first memory subarrays are located on a diagonal of the memory array; a plurality of second memory subarrays, the second memory subarrays are used to store a plurality of second-order interaction coefficients, the second memory subarrays are located on both sides of the memory array; and a plurality of third memory subarrays, the third memory subarrays are used to store a plurality of single-order interaction coefficients, the first memory subarrays are located on a diagonal of the memory array; The three memory subarrays are closed in normal operation, and the third memory subarrays are located between the diagonal of the memory array and the two sides of the memory array; the first memory subarrays, the second memory subarrays and the third memory subarrays form a plurality of groups. During operation, the groups are operated independently, and one of the groups is selected at a time to calculate the local energy of the model operation. The input values are input to the selected group, and the input values are not input to the unselected groups. The memory device as claimed in claim 1, wherein the at least one memory subarray comprises: a plurality of first memory subarrays, the first memory subarrays are used to store a plurality of single-order interaction coefficients, the first memory subarrays are located on a diagonal of the memory array; a plurality of second memory subarrays, the second memory subarrays are used to store a plurality of second-order interaction coefficients, the second memory subarrays are located on both sides of the memory array; and a plurality of third memory subarrays, the third memory subarrays are used to store a plurality of single-order interaction coefficients in a normal operation. The third memory sub-arrays are located between the diagonal of the memory array and the two sides of the memory array; the first memory sub-arrays, the second memory sub-arrays and the third memory sub-arrays form a plurality of groups, and the groups are operated independently during operation. Wherein, the memory device further includes: a switch circuit coupled between the first signal lines and the groups, the input values are input to all the groups, and the switch circuit selects at least one of the groups to output the local energy. A memory device as described in claim 4, wherein the memory device includes a plurality of operation units coupled to the first signal lines, and the switch circuit selects two or more of the groups at a time to output the local energy. An operating method of a memory device is used to process a model operation, wherein the model operation has a plurality of input values and a plurality of interaction coefficients. The operating method comprises: storing a plurality of first part coefficients of the interaction coefficients in a first part of a plurality of memory cells of at least one memory sub-array of a memory array of the memory device, and storing a plurality of second part coefficients of the interaction coefficients in a second part of the memory cells, wherein the first part of the memory cells and the second part of the memory cells are electrically isolated based on a diagonal of the memory array; inputting the plurality of first part coefficients of the interaction coefficients into a first part of a plurality of memory cells of at least one memory sub-array of a memory array of the memory device; and storing the plurality of second part coefficients of the interaction coefficients in a second part of the memory cells. Input values to the memory cells, the memory cells generate a plurality of source currents, the source currents flow through a plurality of first signal lines of the memory device to generate a plurality of common source currents, the first part of the memory cells generates a first part of the common source currents, the second part of the memory cells generates a second part of the common source currents; and Calculate a first part of a local energy of the model operation based on the first part of the common source currents, and calculate a second part of the local energy of the model operation based on the second part of the common source currents. The operating method of the memory device as described in claim 6, wherein the at least one memory sub-array includes: a first memory sub-array, a second memory sub-array and a third memory sub-array, and the operating method further includes: storing a plurality of single-order interaction coefficients in the first memory sub-array, the first memory sub-array being located at the memory A diagonal line of the memory array; storing a plurality of even-order interaction coefficients in the second memory sub-array, the second memory sub-array being located at both sides of the memory array; and in normal operation, closing the third memory sub-array, the third memory sub-array being located between the diagonal line of the memory array and the two sides of the memory array. The operating method of the memory device as described in claim 6, wherein the at least one memory sub-array includes: a plurality of first memory sub-arrays, a plurality of second memory sub-arrays, and a plurality of third memory sub-arrays, and the operating method further includes: storing a plurality of single-order interaction coefficients in the first memory sub-arrays, the first memory sub-arrays being located on a diagonal of the memory array; storing a plurality of second-order interaction coefficients in the second memory sub-arrays, the second memory sub-arrays being located on both sides of the memory array; and Under normal operation, the third memory subarrays are closed, and the third memory subarrays are located between the diagonal of the memory array and the two sides of the memory array; wherein the first memory subarrays, the second memory subarrays and the third memory subarrays form a plurality of groups, and during operation, the groups are operated independently, and one of the groups is selected at a time to calculate the local energy of the model operation, and the input values are input to the selected group, and the input values are not input to the unselected groups. The operating method of the memory device as described in claim 6, wherein the at least one memory sub-array includes: a plurality of first memory sub-arrays, a plurality of second memory sub-arrays, and a plurality of third memory sub-arrays, and the operating method further includes: storing a plurality of single-order interaction coefficients in the first memory sub-arrays, the first memory sub-arrays being located on a diagonal of the memory array; storing a plurality of second-order interaction coefficients in the second memory sub-arrays, the second memory sub-arrays being located on both sides of the memory array; and Under normal operation, the third memory sub-arrays are closed, and the third memory sub-arrays are located between the diagonal of the memory array and the two sides of the memory array; wherein, the first memory sub-arrays, the second memory sub-arrays and the third memory sub-arrays form a plurality of groups, and during operation, the groups are operated independently, wherein the memory device further includes: a switch circuit, the input values are input to all of the groups, and the switch circuit selects at least one of the groups to output the local energy. The operating method of the memory device as described in claim 9, wherein the memory device includes a plurality of operation units coupled to the first signal lines, and the switch circuit selects two or more of the groups at a time to output the local energy.

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