TWI840958B - Data transmission method of cascade drive circuit - Google Patents

Abstract

A data transmission method for a cascade driver circuit, the cascade driver circuit includes a plurality of display driver chips in a cascade configuration, each of the display driver chips having a first data transmission end for transmitting display data with a display driver chip cascaded in front, and a second data transmission end for transmitting the display data with a display driver chip cascaded in the rear. The method is characterized in that: each of the display driver chips can set the first data transmission end as an input end and the second data transmission end as an output end when it is detected that the display data is input to the first data transmission end; and set the second data transmission end as an input end and the first data transmission end as an output end when it is detected that the display data is input to the second data transmission end.

Description

Data transmission method of cascade drive circuit

The present invention relates to the field of LED display technology, and more particularly to a data transmission method of a cascade drive circuit used in an LED display device.

Light-emitting diodes (LEDs) have many advantages such as small size, light weight, long service life, and high luminous efficiency. They are currently widely used in lighting devices and display devices. LED display devices are self-luminous flat display devices with bright colors, wide dynamic range, high brightness, long service life, and high reliability. LED display devices with large screens have been widely used in large squares, commercial advertisements, stadiums, information dissemination, news releases, and stock exchanges as a public display medium.

FIG1 shows a block diagram of a known LED scanning display device. As shown in FIG1 , the known LED display device 1a includes: an LED display panel 11a and an LED display driver circuit, wherein the LED display driver circuit includes a plurality of display driver chips 131a cascaded to each other and a display control unit 14a. Electronic engineers familiar with the design and manufacture of LED displays must know that the display control unit 14a controls all display driver chips 131a to light up the entire display area of the LED display panel 11a at the same time according to different image display requirements, or only controls part of the display driver chips 131a to light up at least one display area of the LED display panel 11a.

In addition, as shown in FIG1, the prior art adopts a single-line transmission form to cascade multiple display driver chips 131a, simplifying the connection between multiple chips and eliminating the need for a shared clock chip. The prior art also establishes a single-line transmission protocol, whose encoding format is shown in the following table (1), and FIG2A, FIG2B and FIG2C show the working timing diagrams of encoding "0", encoding "1" and encoding "Reset". Table (1) Name describe Min (μs) Typ (μs) Max (μs) T0H Code “0” high level time 0.1 0.8 1.0 T1H Code “1” high level time 1.4 1.6 - TL Low level time 0.2 0.4 8 Tcode Total time of high/low level time 2.0 2.5 8 Treset Encode “Reset” low level time twenty four twenty four -

According to this design, each of the display driver chips 131a uses the local oscillator contained therein to cooperate with the data decoder, data buffer and data regenerator to decode, buffer and regenerate an input display data (i.e., D1, D2, ..., DN), thereby realizing the single-line cascade long-distance transmission of the display data. FIG3 shows the working timing diagram of N input display data. As can be seen from FIG1 and FIG3, D1 is the first input display data received by the first display driver chip 131a, and after the first display driver chip 131a decodes and buffers the first group of 24 bits of data, it generates (i.e., data regeneration) the first input display data D2 and transmits it to the second display driver chip 131a (i.e., data continuation). By analogy, single-line cascade data communication of N display driver chips 131a is achieved.

However, the single-line cascade data communication method used in the prior art has shown many disadvantages in practical applications. First, as shown in FIG1 , among the N cascaded display driver chips 131a, if one chip is abnormal or damaged, all other chips in the cascade cannot receive display data. Second, each display driver chip 131a directly receives 24 bits of data, which is easily disturbed by noise, resulting in abnormal data decoding. Third, the 24 bits of data include 8 bits of red grayscale data, 8 bits of green grayscale data, and 8 bits of blue grayscale data. In other words, the grayscale is only 8 bits, and the display effect is average.

From the above description, it can be seen that a novel data transmission method of cascade drive circuit is urgently needed in the field.

The main purpose of the present invention is to provide an LED display driver circuit, which includes N display driver chips cascaded with each other. The present invention particularly adds a first input-output unit, a second input-output unit, a third input-output unit, and a fourth input-output unit to the display driver chip. In this way, the first input-output unit, the second input-output unit, the third input-output unit, and the fourth input-output unit can be determined by switching the levels of a first selection signal and a second selection signal to receive or transmit the input display data of the display driver chip cascaded before, and to receive or transmit the input display data of the display driver chip cascaded before, so that each display driver chip has a bidirectional transmission function. According to this design, even if one chip is abnormal or damaged, all other chips can still receive display data, realizing the function of breakpoint resumption.

In addition, the channel drive data (i.e., grayscale data) of all display driver chips can be increased to 16 bits, greatly improving the display effect. On the other hand, the present invention also adds frame header data and register configuration data to the display data, so that the data processing module of the display driver chip is not easily disturbed by noise and glitches during data decoding and caching.

In order to achieve the above-mentioned purpose, a data transmission method of a cascade driver circuit is proposed. The cascade driver circuit includes a plurality of display driver chips in a cascade configuration. Each of the display driver chips has a first data transmission terminal for transmitting display data with the display driver chip cascaded in front, and a second data transmission terminal for transmitting the display data with the display driver chip cascaded in the rear. The method is characterized in that: Each of the display driver chips can set the first data transmission end as an input end and the second data transmission end as an output end when it is detected that the first data transmission end has input the display data; and set the second data transmission end as an input end and the first data transmission end as an output end when it is detected that the second data transmission end has input the display data.

In one embodiment, the display data includes: frame header data, register configuration data, display data, end code and control code.

In one embodiment, each of the display driver chips has a detection unit to detect whether the first data transmission end has input the display data and whether the second data transmission end has input the display data, thereby determining the transmission direction of the display data between the first data transmission end and the second data transmission end.

In one embodiment, each of the display driver chips further has a multiplexer, and the multiplexer outputs the display data input from the first data transmission end to the second data transmission end, or outputs the display data input from the second data transmission end to the first data transmission end according to the control of the detection unit.

To achieve the above-mentioned purpose, the present invention further proposes a data transmission method for a cascade driver circuit, wherein the cascade driver circuit includes a plurality of display driver chips in a cascade configuration, each of the display driver chips having a first data transmission terminal and a second data transmission terminal for transmitting display data with the two display driver chips cascaded in front, and a third data transmission terminal and a fourth data transmission terminal for transmitting the display data with the two display driver chips cascaded in the back. The method is characterized in that: Each of the display driver chips can set the first data transmission end as an input end and the third data transmission end as an output end when it is detected that the first data transmission end has input the display data; set the second data transmission end as an input end and the fourth data transmission end as an output end when it is detected that the second data transmission end has input the display data; set the third data transmission end as an input end and the first data transmission end as an output end when it is detected that the third data transmission end has input the display data; and set the fourth data transmission end as an input end and the second data transmission end as an output end when it is detected that the fourth data transmission end has input the display data.

In one embodiment, the display data includes: frame header data, register configuration data, display data, end code and control code.

In one embodiment, each of the display driver chips has a detection unit to detect whether the display data is input into the first data transmission end, the second data transmission end, the third data transmission end, and the fourth data transmission end, thereby determining the transmission direction of the display data between the first data transmission end and the third data transmission end, or determining the transmission direction of the display data between the second data transmission end and the fourth data transmission end.

In one embodiment, each of the display driver chips further has a multiplexer, which outputs the display data input from the first data transmission end to the third data transmission end, or outputs the display data input from the third data transmission end to the first data transmission end, or outputs the display data input from the second data transmission end to the fourth data transmission end, or outputs the display data input from the fourth data transmission end to the second data transmission end according to the control of the detection unit.

In order to enable the Review Committee to further understand the structure, features and purpose of the present invention, the following are attached with drawings and detailed descriptions of preferred specific embodiments.

In order to enable the Review Committee to further understand the structure, features, purpose, and advantages of the present invention, the following are attached with drawings and detailed descriptions of preferred specific embodiments.

FIG4 shows a schematic diagram of an LED scanning display device of the present invention. As shown in FIG4, the LED display device 1 of the present invention includes: an LED display panel 11 and an LED display driver circuit, wherein the LED display driver circuit includes a plurality of display driver chips 131 cascaded to each other and a display control unit 14. Electronic engineers familiar with the design and manufacture of LED displays must know that the display control unit 14 controls all display driver chips 131 to light up the entire display area of the LED display panel 11 at the same time according to different image display requirements, or only controls part of the display driver chips 131 to light up at least one display area of the LED display panel 11.

FIG5 is a block diagram of a plurality of display driver chips 131 and a display control unit 14 shown in FIG4 . As shown in FIG4 and FIG5 , N display driver chips 131 are cascaded to each other, and N is a positive integer of at least 2. It is particularly noted that five display driver chips 131 are exemplarily drawn in FIG5 , thereby representing the information connection relationship between the N display driver chips 131 and the display control unit 14. In a feasible embodiment, the LED display panel 11 includes X×Y LED elements, and the LED elements are selected from conventional LED elements, quantum dot LED elements, calcium titanium LED elements, Mirco-LED elements or Mini-LED elements. In other words, the present invention does not particularly limit the type of LED elements used to constitute the LED display panel 11.

FIG6 is an internal block diagram of the display driver chip 131 shown in FIG5. As shown in FIG5 and FIG6, the N display driver chips 131 all include: a first input-output unit 1311, a second input-output unit 1312, a data processing module, a third input-output unit 1313, and a fourth input-output unit 1314. According to the design of the present invention, the j-th display driver chip 131 receives a j-th first input display data Sj from the j-1-th display driver chip 131 through its first input-output unit 1311, or transmits the j-th first input display data Sj to the j-1-th display driver chip 131, wherein j=1,2,3...,N. For example. In the case of j=2, the second display driver chip 131 receives the second first input display data S2 from the first display driver chip 131 , or transmits the second first input display data S2 to the first display driver chip 131 .

On the other hand, according to the design of the present invention, the j-th display driver chip 131 receives a j-1-th second input display data Pj-1 from the j-2-th display driver chip 131 through its second input-output unit 1312, or transmits the j-1-th second input display data Pj-1 to the j-2-th display driver chip 131, where j=1,2,3…,N. For example, when j=3, the third display driver chip 131 receives the second second input display data P2 from the first display driver chip 131 through its second input-output unit 1312, or transmits the second second input display data P2 to the first display driver chip 131.

Furthermore, according to the design of the present invention, the jth display driver chip 131 transmits a j+1th first input display data Sj+1 to the j+1th display driver chip 131 through its third input/output unit 1313, or receives the j+1th first input display data Sj+1 from the j+1th display driver chip 131, wherein j=1, 2, 3…, N. For example, when j=2, the second display driver chip 131 transmits the third first input display data S3 to the third display driver chip 131, or receives the third first input display data S3 from the third display driver chip 131.

On the other hand, according to the design of the present invention, the jth display driver chip 131 transmits the j+1th second input display data Pj+1 to the j+2th display driver chip 131 through its fourth input/output unit 1314, or receives the j+1th second input display data Pj+1 from the j+2th display driver chip 131. For example, when j=3, the third display driver chip 131 transmits the fourth second input display data P4 to the fifth display driver chip 131 through its second input/output unit 1312, or receives the fourth second input display data P4 from the fifth display driver chip 131.

FIG7 shows a working timing diagram of N first input display data Sj, and FIG8 shows a working timing diagram of N-1 second input display data Pj. As shown in FIG7 and FIG8, the j-th first input display data Sj and the j-th second input display data Pj both include: frame header data, register configuration data, N-j+1 display data, end code, and control code. For example, the first input display data S1 includes: 48 bits of header data, 48 bits of register configuration data, N display data, 1 bit of binary end code (2'b0), and control code, wherein each display data includes 16 bits of red grayscale data, 16 bits of green grayscale data, and 16 bits of blue grayscale data, and the control code is a low level of 20μs. For another example, the third first input display data S3 includes: 48 bits of header data, 48 bits of register configuration data, N-3+1 display data, 1 bit of end code, and control code.

On the other hand, the first second input display data P1 includes: 48 bits of header data, 48 bits of register configuration data, N display data, 1 bit of end code, and control code. And, the third second input display data P3 includes: 48 bits of header data, 48 bits of register configuration data, N-3+1 display data, 1 bit of end code, and control code.

FIG9 shows a partial working timing diagram of the first/second input display data. As shown in FIG9 , each bit of the first input display data Sj and the second input display data Pj is a unipolar return-to-zero code, so that the encoding "1" includes data and data clock information, and the encoding "0" also includes data and data clock information. In FIG9 , T1h is the high level time of encoding "1", which is greater than 220ns, and the typical duration value (Typ) is 330ns. On the other hand, T0h is the high level time of encoding "0", which is greater than 60ns and less than 160ns (i.e., 60ns＜T0h＜160ns), and the typical duration value is 1100ns. It should be understood that, since Ts is a minimum data period, it can be known that the low level time of the encoded "1" is greater than 110ns, and the low level time of the encoded "0" is greater than 330ns.

As shown in FIG6 , each of the display driver chips 131 includes a main data processing module, which receives the first display data DI_I, the second display data FI_I, the third display data DO_I, and the fourth display data FO_I, and generates the j-th output display data DO to transmit to the first input-output unit 1311, the second input-output unit 1312, the third input-output unit 1313, and the fourth input-output unit 1314, and generates a j-th channel driving data OUT_Gj and the j-th output display data DO. To explain in more detail, the data processing module includes: a detection unit 1315, a multiplexer 1316, a first oscillator 1317, a data decoder 1318, a data buffer 1319, a data regenerator 131B, a first latch 131C, a second latch 131D, a second oscillator 131E, a PWM generator 131F, and a channel driver 131G.

As shown in FIG. 5 and FIG. 6 , for the j-th display driver chip 131, it utilizes the coupling of the first input-output unit 1311, the second input-output unit 1312, the third input-output unit 1313 and the fourth input-output unit 1314, and generates the first control signal NEG_EN1, the second control signal NEG_EN2, the third control signal POS_EN1 and the third control signal POS_EN1 according to the first display data DI_I, the second display data FI_I, the third display data DO_I, and/or the fourth display data FO_I, and simultaneously generates a first selection signal DIR_SEL and a second selection signal IN_SEL. Furthermore, the multiplexer 1316 is coupled to the first selection signal DIR_SEL, the second selection signal IN_SEL, the first display data DI_I, the second display data FI_I, the third display data DO_I, and the fourth display data FO_I. Furthermore, the oscillator 1317 is used to generate a first clock signal DCLK.

According to the design of the present invention, the data decoder 1318 is coupled to the first oscillator 1317 and the multiplexer 1316, wherein the multiplexer 1316 outputs a fifth display data DIN according to the first selection signal DIR_SEL and the second selection signal IN_SEL, so that the data decoder 1318 performs a decoding operation on the fifth display data DIN according to the first clock signal DCLK. In other words, by switching the level of the first selection signal DIR_SEL and the second selection signal IN_SEL, each display driver chip 131 determines whether to receive or transmit the jth first input display data Sj, the jth second input display data Pj, the j+1th second input display data Sj+1, and the j+1th second input display data Pj+1. The level adjustment method of the first selection signal DIR_SEL and the second selection signal IN_SEL is shown in the following table (2). Table (2) Level control method DIR_SEL 0 The first/second input/output unit is switched to the input interface and the third/fourth input/output unit is switched to the output interface 1 The third/fourth I/O unit is switched to the input interface and the first/second I/O unit is switched to the output interface IN_SEL 0 Main input mode 1 Assisted input mode

With reference to FIG. 6 and the above table (2), it can be understood that when the first selection signal DIR_SEL is at a low level, the display driver chip 131 receives input display data through its first input output unit 1311 and second input output unit 1312, and sends output display data through its third input output unit 1313 and fourth input output unit 1314. That is, the N display driver chips 131 cascaded with each other receive input display data from the preceding chip, and receive and send output display data to the succeeding chip. On the contrary, when the first selection signal DIR_SEL is at a high level, the display driver chip 131 receives input display data through its third input output unit 1313 and fourth input output unit 1314, and sends output display data through its first input output unit 1311 and second input output unit 1312. That is, the N display driver chips 131 cascaded with each other receive input display data from the subsequent chip, and receive and transmit output display data to the previous chip.

Furthermore, with reference to FIG. 6 and the above table (2), it can be understood that when the first selection signal DIR_SEL and the second selection signal IN_SEL are both at a low level, the display driver chip 131 operates in the main input mode. At this time, the j-th display driver chip 131 receives the j-th input display data Sj from the j-1-th display driver chip 131 through its first input-output unit 1311, and transmits the j+1-th input display data Sj+1 to the j+1-th display driver chip 131 through its third input-output unit 1313. On the other hand, when the first selection signal DIR_SEL and the second selection signal IN_SEL are both at high levels, the display driver chip 131 operates in the auxiliary input mode. At this time, the j-th display driver chip 131 receives the j+1-th second input display data Pj+1 from the j+2-th display driver chip 131 through its fourth input-output unit 1314, and transmits the j-1-th second input display data Pj-1 to the j-1-th display driver chip 131 through its second input-output unit 1312.

As shown in FIG5 and FIG6, the data decoder 1318 performs a decoding operation on the fifth display data DIN according to a first clock signal DCLK generated by the first oscillator 1317. Then, the data buffer 1319 performs a data buffering operation on the first data output by the data decoder 1318. Continuously, the data regenerator 131B generates the jth output display data DO after accessing a buffered data of the data buffer 1319.

To explain in more detail, the first latch 131C is coupled to the data register 1319 and accesses the cached data of the data register 1319, and then performs a configuration data lock operation on the register configuration data. Furthermore, the second latch 131D is coupled to the first latch 131C, thereby accessing the cached data of the data register 1319 through the first latch 131C, and then performs a display data lock operation on the display data. As shown in FIG. 5 and FIG. 6 , the second oscillator 131E is used to generate a second clock signal GCLK, and the PWM generator 131F is coupled to the second oscillator 131E and the second latch 131D, thereby accessing the latch data DATA_Gj of the second latch 131D according to the second clock signal GCLK, and further generating a PWM signal PWM_Gj. Finally, the channel driver 131G generates a driving current OUT_Gj according to the PWM signal PWM_Gj, thereby using the driving current OUT_Gj to drive the LED display panel 11 for display. At the same time, the third input-output unit 1313 receives the second display data DO_I transmitted from the first input-output unit 1311 and the j-th output display data DO transmitted from the data processing module, thereby outputting the j+1-th first input display data Sj+1 to the j+1-th display driver chip 131.

According to this design, even if one of the N cascaded display driver chips 131 is abnormal or damaged, all other chips can still receive display data to achieve the function of breakpoint resumption. For example, as shown in Figures 5, 7 and 8, when the third driver chip 131 (i.e., j=3) is abnormal or damaged, although the fourth driver chip 131 cannot receive the j+1=4th first input display data S4 from the third driver chip 131, the fourth driver chip 131 can still receive the third second input display data P3 from the second driver chip 131.

It is worth noting that the Nth display driver chip 131 outputs the Nth first input display data SN, and the N-1th display driver chip 131 outputs the N-1th second input display data PN-1. According to the design of the present invention, the Nth first input display data SN should be transmitted to the N+1th display driver chip 131, and the N-1th second input display data PN-1 should be transmitted to the N+2th display driver chip 131. However, in the absence of the N+1th and N+2th display driver chips 131, as shown in FIG4 and FIG5 , the Nth first input display data SN output by the Nth display driver chip 131 and the N-1th second input display data PN-1 output by the N-1th display driver chip 131 are both returned to the display control unit 14. On the other hand, the third display driver chip 131 receives the second second input display data P2 from the first display driver chip 131, and the first and second display driver chips 131 simultaneously receive the second second input display data P1 from the display control unit 14.

It is to be noted that the present invention uses the 48-bit header data to be composed entirely of coded "1" and the 48-bit register configuration data to be composed entirely of coded "1", thereby utilizing the header data and the register configuration data to form a control command to achieve control of the data processing module of each display driver chip 131. In the process of receiving the j-th first input display data Sj and/or the j-th second input display data Pj, the control command shown in the following table (3) can be implemented by counting the number of consecutive data coded as "1". Table (3) The number of consecutive data coded as "1" Description of control commands Number = 48 Locking and displaying data 64＞Number≧56 Buffer and lock reset 68＞Number≧64 Force channel driver 72＞Number≧68 Chip enters sleep mode 32≦Number＜48 Wake-up chip Number ≦72 Chip enters test mode

According to the above description, the present invention proposes a data transmission method for a cascade driver circuit, wherein the cascade driver circuit includes a plurality of display driver chips in a cascade configuration, each of the display driver chips having a first data transmission terminal for transmitting display data with at least one of the display driver chips cascaded in front, and a second data transmission terminal for transmitting display data with at least one of the display driver chips cascaded in the rear. The method is characterized in that:

Each of the display driver chips can set the first data transmission end as an input end and the second data transmission end as an output end when it is detected that the first data transmission end has input display data; and set the second data transmission end as an input end and the first data transmission end as an output end when it is detected that the second data transmission end has input display data.

In the above method, the display data may include frame header data, register configuration data, display data, end code and control code; each of the display driver chips may have a detection unit to detect whether the display data is input to the first data transmission end and whether the display data is input to the second data transmission end, thereby determining the transmission direction of the display data between the first data transmission end and the second data transmission end; and each of the display driver chips may have a multiplexer, which outputs the display data input from the first data transmission end to the second data transmission end, or outputs the display data input from the second data transmission end to the first data transmission end according to the control of the detection unit.

According to the above description, the present invention also proposes another data transmission method for a cascade driver circuit, wherein the cascade driver circuit includes a plurality of display driver chips in a cascade configuration, each of which has a first data transmission terminal and a second data transmission terminal for transmitting display data with the two display driver chips cascaded in front, and a third data transmission terminal and a fourth data transmission terminal for transmitting the display data with the two display driver chips cascaded in the back. The method is characterized in that: Each of the display driver chips can set the first data transmission end as an input end and the third data transmission end as an output end when it is detected that the first data transmission end has input the display data; set the second data transmission end as an input end and the fourth data transmission end as an output end when it is detected that the second data transmission end has input the display data; set the third data transmission end as an input end and the first data transmission end as an output end when it is detected that the third data transmission end has input the display data; and set the fourth data transmission end as an input end and the second data transmission end as an output end when it is detected that the fourth data transmission end has input the display data.

In the above method, the display data may include frame header data, register configuration data, display data, end code and control code; each of the display driver chips may have a detection unit to detect whether the first data transmission end, the second data transmission end, the third data transmission end and the fourth data transmission end have inputted the display data, thereby determining the transmission direction of the display data between the first data transmission end and the third data transmission end, or determining the transmission direction of the display data between the second data transmission end and the fourth data transmission end. The display driving chip may have a multiplexer, and the multiplexer outputs the display data input from the first data transmission end to the third data transmission end, or outputs the display data input from the third data transmission end to the first data transmission end, or outputs the display data input from the second data transmission end to the fourth data transmission end, or outputs the display data input from the fourth data transmission end to the second data transmission end according to the control of the detection unit.

Thus, the above description has completely and clearly explained the data transmission method of the cascade drive circuit of the present invention; and, from the above description, it can be known that the present invention has the following advantages:

(1) Each display driver chip can have a bidirectional transmission function. Thus, even if one chip is abnormal or damaged, the other chips can still receive the display data, thereby realizing the function of breakpoint resumption; and

(2) The channel drive data (i.e., grayscale data) can be increased to 16 bits, which greatly improves the display effect. On the other hand, the present invention also adds frame header data and register configuration data to the first/second input display data, so that the display driver chip data processing module is not easily disturbed by noise and glitches during data decoding and caching.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are very different from the known technology, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely request the review committee to examine this carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1a: LED display device 11a: LED display panel 131a: display driver chip 14a: display control unit 1: LED display device 11: LED display panel 131: display driver chip 1311: first input and output unit 1312: second input and output unit 1313: third input and output unit 1314: fourth input and output unit 1315: detection unit 1316: multiplexer 1317: first oscillator 1318: data decoder 1319: data buffer 131B: data regenerator 131C: first latch 131D: second latch 131E: second oscillator 131F: PWM generator 131G: channel driver 14: display control unit

FIG1 is a block diagram of a known LED scanning display device; FIG2A is a working timing diagram of coding "0"; FIG2B is a working timing diagram of coding "1"; FIG2C is a working timing diagram of coding "Reset"; FIG3 is a working timing diagram of N input display data; FIG4 is a block diagram of an LED scanning display device of the present invention; FIG5 is a block diagram of multiple display driver chips and a display control unit shown in FIG4; FIG6 is an internal block diagram of the display driver chip shown in FIG5; FIG7 is a working timing diagram of N first input display data; FIG8 is a working timing diagram of N-1 second input display data; and FIG9 is a partial working timing diagram of the first/second input display data.

131: Display driver chip

14: Display control unit

Claims (4)

A data transmission method for a cascade driver circuit, the cascade driver circuit includes a plurality of display driver chips in a cascade configuration, each of the display driver chips has a first data transmission end and a second data transmission end for transmitting display data with the two display driver chips cascaded in front, and a third data transmission end and a fourth data transmission end for transmitting the display data with the two display driver chips cascaded in the rear. The method is characterized in that each of the display driver chips can transmit the first data to the display driver chip when it is detected that the first data transmission end has input display data. The transmission end is set as the input end, and the third data transmission end is set as the output end; when it is detected that the second data transmission end has input the display data, the second data transmission end is set as the input end, and the fourth data transmission end is set as the output end; when it is detected that the third data transmission end has input the display data, the third data transmission end is set as the input end, and the first data transmission end is set as the output end; and when it is detected that the fourth data transmission end has input the display data, the fourth data transmission end is set as the input end, and the second data transmission end is set as the output end. A data transmission method for a cascade drive circuit as described in claim 1, wherein the display data includes: frame header data, register configuration data, display data, end code and control code. The data transmission method of the cascade drive circuit as described in claim 1, wherein each of the display driver chips has a detection unit to detect whether the first data transmission end, the second data transmission end, the third data transmission end and the fourth data transmission end have input the display data, thereby determining the transmission direction of the display data between the first data transmission end and the third data transmission end, or determining the transmission direction of the display data between the second data transmission end and the fourth data transmission end. The data transmission method of the cascade drive circuit as described in claim 3, wherein each of the display drive chips further has a multiplexer, and the multiplexer outputs the display data input from the first data transmission end to the third data transmission end, or outputs the display data input from the third data transmission end to the first data transmission end, or outputs the display data input from the second data transmission end to the fourth data transmission end, or outputs the display data input from the fourth data transmission end to the second data transmission end according to the control of the detection unit.

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