TWI739150B - Package structure of micro memory and package structure of memory - Google Patents

Abstract

A package structure of memory includes circuit substrate, a first chip, a second chip and an encapsulant. The circuit substrate has a first surface, a second surface facing away from the first surface, and a conductive pattern is located on the second surface. The first chip is disposed on the first surface. The first chip has a first active surface away from the first surface and a redistribution layer is located on the first active surface, and the redistributed layer is electrically connected to the circuit substrate. The second chip is disposed on the first active surface and electrically connected to the redistribution layer. The second chip has a second active surface facing the first active surface. The encapsulant is disposed on the first surface and covers the first chip and the second chip. A package structure of memory having an antenna is also provided.

Description

Micro memory packaging structure and memory packaging structure

The present invention relates to a memory packaging structure, and more particularly to a miniature memory packaging structure and a memory packaging structure.

With the vigorous development of the electronic industry, electronic products are also developing in the direction of lightness, thinness, shortness, smallness, high integration, and multi-function. Generally speaking, the packaging form is usually wire bonding (Wire Bonding) packaging. However, this type of packaging structure requires more bonding wires (such as gold wires), so it will need to reserve a larger wire bonding space and also increase a lot. Material costs. Therefore, how to reduce the overall size and reduce the manufacturing cost will become an important issue.

The present invention provides a miniature memory package structure, which can reduce the overall size and reduce the manufacturing cost.

The present invention provides a memory package structure which integrates an antenna.

The micro memory packaging structure of the present invention includes a circuit substrate, a first chip, a second chip, and a packaging glue. The circuit substrate has a first surface, a second surface facing away from the first surface, and a conductive pattern on the second surface. The first wafer is disposed on the first surface. The first chip has a first active surface away from the first surface and a redistributed circuit layer on the first active surface, and the redistributed circuit layer is electrically connected to the circuit substrate. The second chip is disposed on the first active surface and is electrically connected to the redistribution circuit layer. The second wafer has a second active surface facing the first active surface. The packaging glue is arranged on the first surface and covers the first chip and the second chip.

The memory packaging structure of the present invention includes a circuit substrate, a first chip, a second chip, an antenna, and a packaging glue. The circuit substrate has a first surface, a second surface facing away from the first surface, and a conductive pattern on the second surface. The first wafer is disposed on the first surface. The first chip has a first active surface away from the first surface and a redistributed circuit layer on the first active surface, and the redistributed circuit layer is electrically connected to the circuit substrate. The second chip is disposed on the first active surface and is electrically connected to the redistribution circuit layer. The second wafer has a second active surface facing the first active surface. The antenna is disposed on the circuit substrate, and the antenna is located on one side of the first chip. The packaging glue is arranged on the first surface and covers the first chip and the second chip.

Based on the above, the second chip of the micro memory package structure of the present invention is bonded to the first chip with the second active surface facing the first active surface. Therefore, the pre-reserved wire bonding space can be reduced and the overall size can be reduced, and Can reduce the production cost on the wire bonding material.

The memory package structure of the present invention integrates an antenna, and because the second chip is bonded to the first chip in such a way that the second active surface faces the first active surface, the antenna is disposed on the circuit substrate and located on one side of the first chip, Therefore, the pre-reserved wire bonding space can be reduced to increase the clearance area around the antenna, thereby improving the antenna sensitivity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIG. 1A is a schematic top view of a memory package structure according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. In this embodiment, the size of the micro memory package structure 100a may be in line with the size of a micro secure digital memory card (Micro Secure Digital, Micro SD).

Please refer to FIGS. 1A and 1B at the same time. In this embodiment, the micro memory package structure 100 a includes a circuit substrate 110, a first chip 120, a second chip 130, and a packaging compound 160. The circuit substrate 110 may include a plurality of dielectric layers and inner circuit layers (not shown).

The dielectric layer can be made of non-organic or organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, and benzocyclobutene. The inner circuit layer can be made of copper, aluminum, nickel or other suitable conductive materials. It should be noted that the substrate shown in FIG. 1B has at least one dielectric layer (not shown), and the number of layers in the circuit substrate 110 can be determined according to product requirements.

In this embodiment, the circuit substrate 110 has a first surface 110a, a second surface 110b facing away from the first surface 110a, a patterned circuit layer 1161 on the first surface 110a, and a conductive pattern 118 on the second surface 110b . The patterned circuit layer 1161 may partially cover the first surface 110 a of the circuit substrate 110 for subsequent electrical connection between the first chip 120 and the circuit substrate 110. The conductive pattern 118 may be protruded on the second surface 110b. The conductive pattern 118 is, for example, a conductive pad, a contact, or a golden finger.

In this embodiment, the first wafer 120 is disposed on the first surface 110a. The first chip 120 has a first active surface 120 a away from the first surface 110 a and a redistributed circuit layer 122 on the first active surface 120 a, and the redistributed circuit layer 122 is electrically connected to the circuit substrate 110. In an embodiment, the redistributed circuit layer 122 may be located only on the first active surface 120a. The first chip 120 is, for example, a memory chip. For example, the memory chip may be NAND Flash.

In this embodiment, the second chip 130 is disposed on the first active surface 120a and is electrically connected to the redistributed circuit layer 122. The second chip 130 has a second active surface 130a facing the first active surface 120a. The second chip 130 may be electrically connected to the redistribution circuit layer 122 in a flip-chip manner, so that the second chip 130 is electrically connected to the first chip 120, as shown in FIG. 1B.

For example, the second chip 130 may also have a plurality of conductive portions 132 on the second active surface 130 a, and the plurality of conductive portions 132 are bonded to the redistributed circuit layer 122. Furthermore, the conductive portion 132 of the second chip 130 can be disposed on the redistributed circuit layer 122, so that the electrical connection between the second chip 130 and the redistributed circuit layer 122 can be realized.

In this embodiment, since the second chip 130 is bonded to the first chip 120 in such a manner that the second active surface 130a faces the first active surface 120a, the overall size and manufacturing cost can be reduced. Furthermore, through the above method, the pre-reserved wire bonding space can be reduced to reduce the overall size, and the manufacturing cost of the wire bonding material can be reduced. In addition, the redistributed circuit layer 122 can be used for redistribution of circuit signals. Therefore, the second chip 130 faces the first active surface 120a with the second active surface 130a and is electrically connected to the first chip 120 by the redistribution circuit layer 122, which can shorten the signal conduction path and increase the access speed.

The conductive portion 132 may be a conductive ball, a conductive bump, or a conductive pillar. In an embodiment, the material of the conductive ball, the conductive bump or the conductive pillar may include copper, tin, gold, nickel, solder, or a combination of the foregoing, but the present invention is not limited thereto. The second wafer 130 is, for example, a control wafer.

In an embodiment, the orthographic projection of the first chip 120 on the circuit substrate 110 may overlap with the orthographic projection of the second chip 130 on the circuit substrate 110. For example, the orthographic projection range of the second chip 130 on the circuit substrate 110 may be within the orthographic projection range of the first chip 120 on the circuit substrate 110. Furthermore, the size of the second wafer 130 may be smaller than the size of the first wafer 120.

In an embodiment, the micro memory package structure 100 a may further include at least one wire 140. The redistributed circuit layer 122 may be electrically connected to the circuit substrate 110 by wire bonding. Furthermore, the redistributed circuit layer 122 can be electrically connected to the patterned circuit layer 1161 on the circuit substrate 110 through the wires 140, but the present invention is not limited to this, and the connection method of the wires 140 can be adjusted according to actual process requirements.

In an embodiment, the micro memory package structure 100 a may further include at least one passive element 150. The passive element 150 is disposed on the first surface 110 a of the circuit substrate 110 and is electrically connected to the circuit substrate 110. The passive component 150 may be located on a part of the patterned circuit layer 1161. In one embodiment, the orthographic projection of the passive element 150 on the circuit substrate 110 is located between the orthographic projection of the conductive pattern 118 on the circuit substrate 110 and the orthographic projection of the first chip 120 on the circuit substrate 110. The passive element 150 and the conductive pattern 118 may be located on the same side of the first chip 120. Compared with the passive element 150, the conductive pattern 118 can be farther away from the first chip 120.

In this embodiment, the packaging glue 160 is disposed on the first surface 110 a and covers the first chip 120 and the second chip 130. In detail, the encapsulant 160 covers the side surface of the first chip 120 and the side surface of the second chip 130. Furthermore, the encapsulant 160 can also cover the wires 140 and the passive components 150 on the first surface 110 a of the circuit substrate 110. The material of the encapsulant 160 is, for example, Epoxy Molding Compound (EMC).

It must be noted here that the following embodiments follow the component numbers and part of the content of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiments, and the descriptions of the following embodiments will not be repeated.

2 is a schematic cross-sectional view of a memory package structure according to another embodiment of the invention. Please refer to FIG. 2, the memory packaging structure 100b of this embodiment is similar to the micro memory packaging structure 100a of the above-mentioned embodiment, but the difference is that the memory packaging structure 100b is not limited to a micro memory packaging structure, and this embodiment The memory package structure 100b includes an antenna 1701. The antenna 1701 is disposed on the circuit substrate 110, and the antenna 1701 is located on one side of the first chip 120. Furthermore, the antenna 1701 may be embedded in the circuit substrate 110. In this embodiment, the antenna 1701 may belong to a part of the inner circuit layer. In this way, the antenna 1701 can be integrated into the inner circuit layer to further reduce the manufacturing cost.

In this embodiment, since the second chip 130 is bonded to the first chip 120 in such a manner that the second active surface 130a faces the first active surface 120a, and the antenna 1701 is disposed on the circuit substrate and located on one side of the first chip 120 Therefore, the pre-reserved wire bonding space can be reduced, and the clearance area around the antenna 1701 can be increased, thereby improving the sensitivity of the antenna 1701.

For example, the antenna 1701 is, for example, a radio frequency identification (RFID) antenna applicable to Near Field Communication (NFC). When the above-mentioned memory package structure 100b is applied to near field communication, the above-mentioned configuration can increase the area of the clear space around the antenna 1701, thereby increasing the sensing distance of the antenna 1701 and improving the sensing sensitivity of the antenna 1701.

Here, the clearance area refers to an area where there is no conductive material, which is used to prevent electronic components from causing electromagnetic interference to the antenna 1701 in an external environment. For example, the circuit substrate 110 may have an insulating region R located between the first surface 110a and the second surface 110b, and the insulating region R is located directly above the antenna 1701. In other words, the insulating region R is located between the first surface 110a and the antenna 1701. Therefore, the insulating region R may be a part of the clearance area around the antenna 1701.

In an embodiment, the passive element 150 may be located between the first chip 120 and the antenna 1701. The passive element 150, the antenna 1701 and the conductive pattern 118 may be located on the same side of the first chip 120. Compared with the passive element 150, the antenna 1701 and the conductive pattern 118 can be farther away from the first chip 120, and the orthographic projection of the antenna 1701 on the circuit substrate 110 overlaps the orthographic projection of the conductive pattern 118 on the circuit substrate 110. In an embodiment, the orthographic projection area of the antenna 1701 on the circuit substrate 110 is smaller than the orthographic projection area of the conductive pattern 118 on the circuit substrate 110, but the present invention is not limited to this.

3 is a schematic cross-sectional view of a memory package structure according to another embodiment of the invention. 3, the memory package structure 100c of this embodiment is similar to the memory package structure 100b of the above-mentioned embodiment, but the difference is that the antenna 1702 of the memory package structure 100c of this embodiment is disposed on the first circuit substrate 110 On a surface 110b. The antenna 1702 is electrically connected to the patterned circuit layer 1162. In an embodiment, the antenna 1702 may be a part of the patterned circuit layer 1162, and the encapsulant 160 may cover the antenna 1702.

FIG. 4 is a schematic top view of the antenna in FIG. 2 and FIG. 3. Please refer to FIG. 4, the antenna 1701 of FIG. 2 and the antenna 1702 of FIG. 3 may be helical antennas. The helical antenna can be a near-field antenna and a far-field antenna. The winding method and graphical presentation of the antenna design can adjust the antenna area and appearance design method according to the actual design impedance matching requirements.

5A is a schematic cross-sectional view of a memory package structure according to still another embodiment of the invention. FIG. 5B is a schematic top view of the antenna in FIG. 5A. Referring to FIGS. 5A and 5B at the same time, the memory package structure 100d of this embodiment is similar to the memory package structure 100c of the above embodiment, but the difference is that the antenna 1703 of the memory package structure 100d of this embodiment includes an antenna substrate 1704 and an antenna pattern 1705 arranged on the antenna substrate 1704, and the antenna 1703 may be an array antenna, as shown in FIG. 5B. Further speaking. The antenna substrate 1704 is disposed on the first surface 110 a of the circuit substrate 110, and the antenna substrate 1704 is electrically connected to the circuit substrate 110. The antenna substrate 1704 may be located on the patterned circuit layer 1163 to be electrically connected to the circuit substrate 110 through the patterned circuit layer 1163. In an embodiment, the antenna 1703 may be combined on the circuit substrate 110 in a surface-mount technology (SMT) manner, but the present invention is not limited to this.

In summary, in the micro memory package structure of the present invention, since the second chip is bonded to the first chip with the second active surface facing the first active surface, the pre-reserved bonding space can be reduced and the overall size can be reduced. , And can reduce the production cost of wire bonding materials. Furthermore, the second chip faces the first active surface with the second active surface and is electrically connected to the first chip by the redistributed circuit layer, which can shorten the signal conduction path and increase the access speed.

The memory package structure of the present invention integrates an antenna, and because the second chip is bonded to the first chip in such a way that the second active surface faces the first active surface, the antenna is disposed on the circuit substrate and located on one side of the first chip, Therefore, the pre-reserved wire bonding space can be reduced to increase the clearance area around the antenna, thereby improving the antenna sensitivity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100a: Micro memory package structure 100b, 100c, 100d: memory package structure 110: circuit board 110a: first surface 110b: second surface 1161, 1162, 1163: patterned circuit layer 118: Conductive pattern 120: The first chip 120a, 130a: active surface 122: Relay line layer 130: second chip 132: Conductive part 140: Wire 150: Passive components 160: Encapsulation colloid 1701, 1702, 1703: antenna 1704: Antenna substrate 1705: antenna pattern R: Insulated area

FIG. 1A is a schematic top view of a micro memory package structure according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. 2 is a schematic cross-sectional view of a memory package structure according to another embodiment of the invention. 3 is a schematic cross-sectional view of a memory package structure according to another embodiment of the invention. FIG. 4 is a schematic top view of the antenna in FIG. 2 and FIG. 3. 5A is a schematic cross-sectional view of a memory package structure according to still another embodiment of the invention. FIG. 5B is a schematic top view of the antenna in FIG. 5A.

100a: Micro memory package structure

110: circuit board

110a: first surface

110b: second surface

1161: Patterned circuit layer

118: Conductive pattern

120: The first chip

120a, 130a: active surface

122: Relay line layer

130: second chip

132: Conductive part

140: Wire

150: Passive components

160: Encapsulation colloid

Claims (15)

A memory packaging structure, comprising: a circuit substrate having a first surface, a second surface facing away from the first surface, and a conductive pattern on the second surface; a first chip disposed on the first surface Above, wherein the first chip has a first active surface away from the first surface and a redistributed circuit layer on the first active surface, and the redistributed circuit layer is electrically connected to the circuit substrate; The second chip is arranged on the first active surface and is electrically connected to the redistributed circuit layer, wherein the second chip has a second active surface facing the first active surface; the antenna is arranged on the The circuit substrate, and the antenna is located on one side of the first chip; and an encapsulating compound is disposed on the first surface and covers the first chip and the second chip. In the memory package structure described in the first item of the scope of patent application, the antenna is embedded in the circuit substrate. The memory package structure according to the second patent application, wherein the circuit substrate further has an insulating area between the first surface and the second surface, and the insulating area is located on the antenna Right above, the insulating area is located between the first surface and the antenna. The memory package structure according to the first item of the scope of patent application, wherein the antenna is disposed on the first surface of the circuit substrate. According to the memory package structure described in claim 4, the circuit substrate further has a patterned circuit layer on the first surface, and the antenna is a part of the patterned circuit layer. According to the memory package structure described in claim 4, the circuit substrate further has a patterned circuit layer on the first surface, and the antenna is electrically connected to the patterned circuit layer. In the memory packaging structure described in item 4 of the scope of patent application, the packaging glue covers the antenna. The memory package structure according to claim 4, wherein the antenna includes an antenna substrate and an antenna pattern arranged on the antenna substrate, wherein the antenna substrate is arranged on the first of the circuit substrate. On the surface, and the antenna substrate is electrically connected to the circuit substrate. The memory package structure described in the first item of the scope of patent application further includes: at least one passive element disposed on the first surface of the circuit substrate and located between the first chip and the antenna. The memory package structure according to the first item of the scope of patent application, wherein the orthographic projection of the first chip on the circuit substrate overlaps the orthographic projection of the second chip on the circuit substrate. The memory package structure according to the first item of the scope of patent application, wherein the orthographic projection range of the second chip on the circuit substrate is within the orthographic projection range of the first chip on the circuit substrate. The memory package structure according to claim 1, wherein the second chip further has a plurality of conductive parts on the second active surface, and the plurality of conductive parts are connected to the redistribution wiring Road layer. The memory packaging structure described in the first item of the scope of patent application further includes: at least one wire, and the redistributed circuit layer is electrically connected to the circuit substrate through the wire. The memory package structure according to the scope of patent application, wherein the circuit substrate further has a patterned circuit layer on the first surface, and the redistributed circuit layer is electrically connected to the ground through the wire The patterned circuit layer. The memory package structure according to the first item of the patent application, wherein the first chip is a memory chip and the second chip is a control chip.

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