TWI738003B - Line structure for fan-out circuit and manufacturing method thereof - Google Patents

Abstract

A line structure for fan-out circuit having a dense-line area and a fan-out area is provided. The line structure includes a plurality of dense lines arranged in the dense-line area parallel to a first direction, a plurality of pads disposed in the fan-out area, and a plurality of connecting lines arranged in the fan-out area parallel to a second direction. The connecting lines respectively connect one of the dense lines with one of the pads, wherein at least one of the connecting lines is a wavy line.

Description

Circuit structure of fan-out circuit and manufacturing method thereof

The invention relates to a circuit structure of a fan-out circuit and a manufacturing method thereof.

The circuit of the fan-out circuit connects the dense line array pattern of the word lines in the memory array to the pad pattern of the pad.

The circuit of a general fan-out circuit includes a dense line area with many dense lines and a fan-out area connected to the pads. With the increase in line density and the development of miniaturization of components, the line spacing and line width in the dense line area have also been greatly reduced. In order to ensure the resolution of the dense line area in the exposure process, a light source with high light intensity in a single direction (orthogonal to the direction in which the dense line extends) is used for exposure. However, such an exposure method will cause problems in the semi-iso line exposure at the junction of the dense line area and the fan-out area, which in turn impacts the process window. Since the semi-isolated line is only adjacent to other dense lines on one side, the light intensity in the direction orthogonal to the extension direction of the dense lines is higher than other dense lines, which causes the photoresist to collapse and cannot be formed.

Although there are researches on improving the mask pattern, there are problems of photoresist collapse (peeling) or unexpected patterns (dummy patterns) being printed out due to optical interference and diffraction.

The invention provides a circuit structure of a fan-out circuit, which is manufactured by a lithography process with a large process margin, and has no unexpected pattern formation.

The present invention also provides a method for manufacturing a circuit structure of a fan-out circuit, which can obtain a larger manufacturing process margin without unintended pattern formation.

The circuit structure of the fan-out circuit of the present invention includes a plurality of dense lines, a plurality of pads (PAD), and a plurality of connecting lines. The fan-out circuit has a dense line area and a fan-out area. The dense lines are arranged in the dense line area parallel to a first direction, the pads are located in the fan-out area, and the connecting lines are arranged in the fan-out area parallel to a second direction, and connect one line respectively The dense line and a pad, wherein at least one of the connecting lines is a wavy line.

In an embodiment of the present invention, the shape of the wavy line in the two adjacent connecting lines is mirror symmetry.

In another embodiment of the present invention, the shape of the wavy line in the two adjacent connecting lines is an asymmetric structure.

In an embodiment of the present invention, the minimum distance between the two adjacent connecting lines is between 150 nm and 200 nm.

In an embodiment of the present invention, the period of the waveform line is between 70 nm and 90 nm.

In an embodiment of the present invention, the amplitude of the above-mentioned waveform line is between 20 nm and 40 nm.

The manufacturing method of the circuit structure of the fan-out circuit of the present invention includes forming a sacrificial layer on a conductor layer, and then forming a patterned photoresist layer on the sacrificial layer. The patterned photoresist layer includes a A plurality of first linear patterns arranged in a dense line area in one direction and a plurality of second linear patterns arranged in a fan-out area parallel to a second direction, and at least one side of the second linear patterns presents waves shape. Then, the first line patterns and the second line patterns are transferred to the sacrificial layer to form a plurality of first lines and a plurality of second lines and expose the conductive layer, wherein at least the second line One side wall is wavy. A gap wall is formed on the side wall of each first line and the side wall of at least one second line, and then the first line and the second line are removed. Using the spacer as a mask, the exposed conductor layer is etched and removed, so that the conductor layer becomes multiple dense lines in the dense line area and multiple connection lines in the fan-out area. One connecting line is a wavy line.

In another embodiment of the present invention, the method for forming the above-mentioned patterned photoresist layer includes using an exposure light source whose intensity in the second direction is greater than that in the first direction.

In another embodiment of the present invention, the first direction is perpendicular to the second direction.

In another embodiment of the present invention, after removing the first line and the second line, a plurality of pads may be formed in the fan-out area, which are respectively connected to the connecting line.

Based on the above, the present invention can enlarge the process margin for the circuit process of fan-out circuit by specially designed mask pattern, thus forming circuit with specific morphology to connect the pads of the fan-out area and the dense line area. Dense lines, and because of the large process margin, the photoresist is not easy to collapse (peeling) or print out (print out), so it can prevent the formation of unintended patterns (dummy patterns) in the structure from being formed.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The following content provides many different implementations or examples for implementing different features of the present invention. Moreover, these embodiments are only exemplary, and are not used to limit the scope and application of the present invention. Furthermore, for the sake of clarity, the relative size (such as length, thickness, spacing, etc.) and relative position of each region or structural element may be reduced or enlarged. In addition, similar or identical element symbols are used in the various drawings to indicate similar or identical elements or features.

FIG. 1 is a schematic diagram of the layout of a photomask pattern according to the first embodiment of the present invention.

Please refer to FIG. 1, the photomask pattern of this embodiment is used in a fan-out circuit, and the fan-out circuit usually includes a dense line area 10a and a fan-out area 10b. In order to ensure the resolution of the dense line region 10a and the overall process margin at the same time, an auxiliary pattern 110 is added to the mask pattern.

In one embodiment, the main pattern 100 in the mask pattern includes a plurality of strip patterns 102a, 102b, 102c arranged in a dense line region 10a parallel to a first direction and a plurality of strip patterns 102a, 102b, 102c in the fan-out region 10b A plurality of connecting patterns (connecting patterns) 104a, 104b, 104c arranged parallel to a second direction, and each connecting pattern connects to a strip pattern, for example, the connecting pattern 104b connects to the strip pattern 102a, and the connecting pattern 104c connects to the strip pattern 102b, and so on. The first direction is different from the second direction, for example, the first direction is perpendicular to the second direction. In another embodiment, if the circuit is to be lengthened, the main pattern 100 may further include a plurality of block patterns 106a, 106b, 106c, which are arranged in the fan-out area 10b parallel to the second direction, and each The widths of the block patterns 106a, 106b, and 106c are generally greater than the widths of the connection patterns 104a, 104b, and 104c. The above connection pattern connects a strip pattern with a block pattern; for example, the connection pattern 104b connects the strip pattern 102a with the block pattern 106b, and the connection pattern 104c connects the strip pattern 102b with the block pattern 106c, according to And so on.

As for the auxiliary pattern 110, it is composed of a plurality of line patterns 112a, 112b arranged in parallel to the second direction, and the auxiliary pattern 110 is respectively arranged in the area between a strip pattern and two adjacent connection patterns; for example; In other words, the line pattern 112a is set in the area between the strip pattern 102a and two adjacent connection patterns 104a and 104b, and the line pattern 112b is set in the strip pattern 102b and two adjacent connection patterns 104b and 104c. The area between, and so on. Moreover, the line patterns 112a, 112b in the auxiliary pattern 110 directly contact a strip pattern; for example, each line pattern 112a directly contacts the strip pattern 102a, each line pattern 112b directly contacts the strip pattern 102b, and so on.

In another embodiment, if the main pattern 100 further includes block patterns 106a, 106b, 106c, the auxiliary pattern 110 is arranged in a strip pattern, two adjacent connection patterns and two adjacent block patterns For example, the line pattern 112a is the area between the strip pattern 102a, the two adjacent connection patterns 104a and 104b, and the two adjacent block patterns 106a and 106b, and the line pattern 112b is set in The area between the strip pattern 102b, the two adjacent connection patterns 104b and 104c, and the two adjacent block patterns 106b and 106c, and so on.

FIG. 2 is an enlarged schematic view of a part of FIG. 1 (the line pattern 112a in the auxiliary pattern 110). In FIG. 2, the length L of the line pattern 112a in the auxiliary pattern 110 is, for example, between 200 nm and 240 nm, and the width W1 of the line pattern 112a in the auxiliary pattern 110 is, for example, between 18 nm and 24 nm. The spacing S1 between the line patterns 112a is, for example, between 30 nm and 50 nm, and the spacing S2 between the line pattern 112a and the adjacent connection pattern 104a (or 104b) next to it is, for example, between 40 nm and 80 nm. It is not limited to this. In response to different component size designs, various size designs of the auxiliary pattern 110 can be changed.

Fig. 3 is a schematic diagram of the layout of another mask pattern of the first embodiment, in which the element symbols in Fig. 1 are used to denote the same or similar components, and the description of the same components can refer to the content of the above first embodiment, here No longer.

In FIG. 3, the auxiliary pattern 300 includes additional line patterns 304a and 304b in addition to the line patterns 302a and 302b. The position of the line patterns 302a, 302b is similar to the line patterns 112a, 112b of FIG. 1, and they will directly contact the strip patterns 102a, 102b. The additional line patterns 304a are arranged between the line patterns 302a parallel to the second direction, and the additional line patterns 304b are arranged between the line patterns 302b parallel to the second direction. Moreover, the additional line patterns 304a, 304b do not contact the bar patterns 102a, 102b. In other words, the auxiliary pattern 300 is composed of a staggered line pattern 302a (or 302b) and an additional line pattern 304a (or 304b). In addition, the additional line patterns 304a, 304b in the auxiliary pattern 300 can directly contact two adjacent block patterns; for example, an additional line pattern 304a will directly contact the block pattern 106a, and some additional line patterns 304a will directly contact the block pattern. Pattern 106b; an additional line pattern 304b will directly contact the block pattern 106b, some additional line pattern 304b will directly contact the block pattern 106c, and so on. However, the present invention is not limited to this, and the additional line patterns 304a and 304b may not touch the surrounding patterns.

The mask pattern and the photoresist pattern after simulated exposure and development according to the first embodiment are shown in Fig. 4, where the lines represent the outline of the mask pattern similar to Fig. 1, and the area drawn by dots represents the simulated non-resistor. The pattern area, the white area represents the simulated photoresist pattern. It can be seen from FIG. 4 that the use of the mask pattern of the first embodiment for exposure and development will result in multiple first line patterns 400a, 400b, 400c in the dense line area 10a and multiple second line patterns in the fan-out area 10b. In the photoresist pattern of the linear pattern 402, the side 402a of the second linear pattern 402 is wavy.

Since the mask pattern has a comb-shaped pattern composed of a stripe pattern and contacting auxiliary patterns (such as 102a and 112a in Figure 1), the light source with high light intensity in a single direction (such as the second direction) is used for exposure. At the same time, such a comb pattern can solve the problem of exposure in the direction with strong light intensity (such as the second direction), thereby increasing the process margin. In detail, if there is no auxiliary pattern, the light intensity of exposure in the second direction is too high, so the first line pattern 400a closest to the boundary between the dense line area 10a and the fan-out area 10b cannot be formed. If several line patterns arranged in the first direction are used as auxiliary patterns, an unnecessary line pattern will be formed in the fan-out area 10b close to the boundary line between the dense line area 10a and the fan-out area 10b, which is unexpected. The problem of dummy pattern being printed out occurs. If several line patterns that are arranged along the second direction but do not touch the stripe pattern (102a in Fig. 1) are used as the auxiliary pattern, the area between the stripe pattern and this auxiliary pattern will be illuminated by strong light. The first line pattern 400a closest to the boundary between the dense line area 10a and the fan-out area 10b is collapsed.

5A to 5E are schematic top views of a manufacturing process of a circuit structure of a fan-out circuit according to a second embodiment of the present invention.

5A, a sacrificial layer 500 is first formed on the conductor layer (not shown), and then a patterned photoresist layer 502 is formed on the sacrificial layer 500, and the method of forming the patterned photoresist layer 502 is used, for example, An exposure light source whose intensity in the second direction is greater than that in a first direction is matched with the mask pattern of the first embodiment to increase the process margin. Therefore, this patterned photoresist layer 502 includes a plurality of first linear patterns 504 arranged in a dense line area 50a parallel to the first direction, and a plurality of second line patterns 504 arranged in a fan-out area 50b parallel to the second direction. Linear patterns 506, at least one side 506a of the second linear patterns 506 is wavy. In this embodiment, the period P1 of the first linear pattern 504 is, for example, between 70 nm and 90 nm; the width W2 of the first linear pattern 504 is, for example, between 35 nm and 50 nm; The spacing S3 between 504 is, for example, between 20 nm and 55 nm, but the present invention is not limited to this. In response to different component layout designs, the above-mentioned various size designs of the first linear pattern 504 can be changed. Although two first line patterns 504 and two second line patterns 506 are shown in the figure, it should be understood that the dense line area 50a of the fan-out circuit has a very dense number of first line patterns 504, and the fan-out area 50b corresponding to these first line patterns 504 will also have many second line patterns 506. In addition, the patterned photoresist layer 502 may further include a block pattern 508 parallel to the second direction for subsequent formation of lines extending and connected to the pads. In this embodiment, the first direction is perpendicular to the second direction. For example, FIG. 6A is a scanning electron microscopy image (SEM image) of a patterned photoresist layer obtained by using the mask pattern of FIG. 4 to perform exposure and development with high light intensity in the second direction; FIG. 6B is the image Partial enlarged view of 6A. It can be clearly observed from Fig. 6B that the sides of the linear pattern are wavy.

Then, referring to FIG. 5B, the first line patterns 504 and the second line patterns 506 are transferred to the sacrificial layer 500 to form a plurality of first lines 510 and a plurality of second lines 512 and expose the underlying conductor In the layer 514, at least one sidewall 512a of the second line 512 is also wavy like the side 506a of the second line pattern 506. The above-mentioned pattern transfer method, for example, uses the patterned photoresist layer 502 as a mask, etches the exposed sacrificial layer 500, and then removes the patterned photoresist layer 502.

Next, referring to FIG. 5C, a spacer 516 is formed on the sidewall 510a of each first line 510 and at least one sidewall 512a of the second line 512. The method of forming the spacer 516, for example, first deposit a layer of material (not shown) to cover the entire first line 510 and the second line 512, and then etch the aforementioned material layer until the spacer 516 is formed. The material of the spacer 516 is, for example, polysilicon, silicon oxide, silicon nitride, etc.

Subsequently, referring to FIG. 5D, the first line 510 and the second line 512 are removed, and then the spacer 516 of FIG. 5C is used as a mask, and the exposed conductor layer 514 is etched away to form a plurality of dense lines in the dense line region 50a (Dense line) 514a and multiple connection lines 514b in the fan-out area 50b. At least one of these connecting lines 514b is a wavy line 518. In addition, the connecting line 514b also includes a straight line 520 or a curved line other than the wavy line 518. Then, the spacer 516 is removed. Since at least one of the connecting lines 514b is a wavy line 518, it means that a mask pattern with a specific auxiliary pattern is used, which can expand the manufacturing process margin and prevent the photoresist from collapsing or printing out. The formation of unintended patterns in the structure can be avoided.

After that, referring to FIG. 5E, a plurality of pads (PAD) 522 may be selectively formed in the fan-out area 50b, and each pad 522 is connected to a connecting line 514b. For example, the partially connected connection lines 514b are separated by etching or the like, and then the pads 522 are formed at the end of each connection line 514b by evaporation, electroplating, or printing technology. However, the present invention is not limited to this; the design and manufacture of the above-mentioned pad 522 can also adopt other existing technologies, which will not be repeated here.

7 is a schematic top view of the circuit structure of a fan-out circuit according to the third embodiment of the present invention, in which the component symbols of FIG. 5E are used to denote the same or similar components, and the description of the same components can refer to the second The content of the embodiment will not be repeated here.

Referring to FIG. 7, the circuit structure 700 of the fan-out circuit of the third embodiment includes a plurality of dense lines 514a, a plurality of pads 522, and a plurality of connecting lines 514b. The dense lines 514a are arranged in a dense line area 50a parallel to a first direction, the pads 522 are located in the fan-out area 50b, and the connecting lines 514b are arranged in a fan-out area 50b parallel to a second direction. In addition, one connecting line 514b connects a dense line 514a and one pad 522, and at least one connecting line 514b is a wavy line 518. In this embodiment, the period P2 of the waveform line 518 is, for example, between 70 nm and 90 nm; the amplitude Amp of the waveform line 518 is, for example, between 20 nm and 40 nm. Since the wavy line 518 is caused by the design of the auxiliary pattern in the mask pattern, which results in interference and diffraction of light, the period P2 and amplitude Amp of the wavy line 518 will also vary due to the different auxiliary pattern design in the mask pattern. Variety. In addition, depending on the circuit design of the circuit, the connecting line 514b may also include a straight line 520 or a curve other than the wavy line 518.

In FIG. 7, the shape of the wavy line 518 in the two adjacent connecting lines 514b is mirror symmetry. Moreover, the minimum distance d between two adjacent connecting lines 514b is, for example, between 150 nm and 200 nm. However, in response to different device size designs and exposure and development processes, the shape, position, and size of the wavy line 518 can be changed.

For example, if the patterned photoresist layer as shown in FIG. 6A is used to perform the manufacturing process of the second embodiment, the shape of the wavy lines in the two adjacent connecting lines will be an asymmetric structure.

FIG. 8 is a schematic top view of the circuit structure of another fan-out circuit of the third embodiment, in which the component symbols of FIG. 7 are used to denote the same or similar components, and the description of the same components can refer to the related content of FIG. 7 , I won’t repeat it here.

In FIG. 8, the connecting line 514 b has only the wave line 518, so the wave line 518 connects a dense line 514 a and a pad 522.

In summary, the present invention uses a mask pattern with a specific auxiliary pattern to expand the process margin of the circuit process for fan-out circuits, and thereby form a circuit with a specific shape to connect the fan-out area The dense lines of the pads and dense line areas, and due to the large process margin, are not prone to problems such as photoresist collapse (peeling) or print out (print out), and can prevent the formation of unexpected patterns in the structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10a, 50a: dense line area 10b, 50b: fan-out area 100: main pattern 102a, 102b, 102c: strip pattern 104a, 104b, 104c: connection pattern 106a, 106b, 106c: block pattern 110, 300: auxiliary pattern 112a, 112b, 302a, 302b: line pattern 304a, 304b: additional line pattern 400a, 400b, 400c, 504: the first line pattern 402, 506: second line pattern 402a, 506a: side 500: sacrifice layer 502: patterned photoresist layer 510: first line 510a, 512a: side wall 512: second line 514: Conductor layer 514a: dense line 514b: connection line 516: Clearance Wall 518: Wave line 520: straight line 522: Adapter 700: Line structure Amp: amplitude d: minimum distance L: length P1, P2: cycle S1, S2, S3: Spacing W1, W2: width

FIG. 1 is a schematic diagram of the layout of a photomask pattern according to the first embodiment of the present invention. Fig. 2 is a partial enlarged schematic diagram of Fig. 1. FIG. 3 is a schematic diagram of the layout of another mask pattern of the first embodiment. 4 is a photomask pattern and a photoresist pattern after simulated exposure and development according to the first embodiment. 5A to 5E are schematic top views of a manufacturing process of a circuit structure of a fan-out circuit according to a second embodiment of the present invention. FIG. 6A is a scanning electron microscopic image of a patterned photoresist layer obtained by exposure and development using the photomask pattern of FIG. 4. FIG. Fig. 6B is a partially enlarged view of Fig. 6A. FIG. 7 is a schematic top view of a circuit structure of a fan-out circuit according to a third embodiment of the present invention. FIG. 8 is a schematic top view of the circuit structure of another fan-out circuit of the third embodiment.

50a: dense line area

50b: Fan-out area

514a: dense line

514b: connection line

518: Wave line

520: straight line

522: Adapter

700: Line structure

Amp: amplitude

d: minimum distance

P2: Period

Claims (10)

A circuit structure of a fan-out circuit. The fan-out circuit has a dense line area and a fan-out area. The circuit structure includes a plurality of dense lines arranged in the dense line area parallel to a first direction A plurality of pads are located in the fan-out area; and a plurality of connecting lines are arranged in the fan-out area parallel to the second direction, and respectively connect one of the plurality of dense lines and the majority One of the pads, wherein at least one of the connecting lines includes a wavy line, and the line width of the plurality of dense lines is approximately equal to the line width of the plurality of connecting lines. As for the circuit structure of the fan-out circuit described in the first item of the scope of patent application, the shape of the wave line in the two adjacent connecting lines is mirror symmetry. In the circuit structure of the fan-out circuit described in the first item of the scope of patent application, the shape of the wavy line in the two adjacent connecting lines is an asymmetric structure. As for the circuit structure of the fan-out circuit described in item 1 of the scope of patent application, the minimum distance between two adjacent connecting lines is between 150 nm and 200 nm. As for the circuit structure of the fan-out circuit described in the first item of the scope of patent application, the period of the wavy line is between 70 nm and 90 nm. In the circuit structure of the fan-out circuit described in the first item of the scope of patent application, the amplitude of the wave line is between 20 nm and 40 nm. A method for manufacturing a circuit structure of a fan-out circuit, the fan-out circuit having a dense line area and a fan-out area, the method comprising: forming a sacrificial layer on a conductor layer; on the sacrificial layer A patterned photoresist layer is formed, which includes a plurality of first linear patterns arranged in the dense line area parallel to the first direction and a plurality of second linear patterns arranged in the fan-out area parallel to the second direction At least one side of the second linear pattern is wavy; the plurality of first linear patterns and the plurality of second linear patterns are transferred to the sacrificial layer to form a plurality of first lines and A plurality of second lines expose the conductor layer, wherein at least one side wall of the second line is wavy; a gap is formed between the side wall of the first line and the at least one side wall of the second line And removing the plurality of first lines and the plurality of second lines; using the spacer as a mask, etching and removing the exposed conductor layer, so that the conductor layer becomes the dense line The majority of dense lines in the area and the majority of connection lines in the fan-out area, wherein at least one of the connection lines is a wavy line. The manufacturing method according to claim 7, wherein the method of forming the patterned photoresist layer includes using an exposure light source whose intensity in the second direction is greater than that in the first direction. The manufacturing method as described in item 7 of the scope of patent application, wherein the first direction is perpendicular to the second direction. According to the manufacturing method described in item 7 of the scope of patent application, after removing the plurality of first wires and the plurality of second wires, it further includes forming a plurality of pads in the fan-out area, respectively Most of the connecting lines are connected.

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