TWI737417B - Transistor structure and manufacturing method thereof - Google Patents

Abstract

A transistor structure including a substrate, a gate electrode, contacts, spacers is provided. The gate electrode is divided into gate electrode portions by slits. Each of the contacts includes an upper portion and a lower portion connected to each other. The lower part is located in the slit. The upper part is located on the lower part and spans over the slit. The spacers are respectively located between the gate electrode potions and the contacts.

Description

Transistor structure and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and more particularly to a transistor structure and its manufacturing method.

Metal oxide semiconductor (MOS) devices can be divided into symmetrical (symmetry) devices and asymmetrical (asymmetry) devices. The so-called symmetrical device means that the drain and source can be reversed and have exactly the same characteristics. On the other hand, an asymmetric element means that the characteristics of the drain and source are completely different after they are used. If there are no special regulations, symmetrical components are generally used. In the layout design of symmetrical components, the distance from the drain, source, and contact window to the gate must be the same, otherwise the characteristics will be different.

At present, in the layout design of some transistor devices, the distance from the drain contact to the gate must be the same as the distance from the source contact to the gate. However, the lithography process used to form the above-mentioned contact window often has the problem of overlay shift, so it is difficult to make these distances completely equal. In this case, the drain saturation current (Idsat) between the transistor elements will be mismatched, and the electrical performance of the transistor elements will be reduced.

The present invention provides a transistor structure and a manufacturing method thereof, which can effectively improve the electrical performance of the transistor element.

The present invention provides a transistor structure including a substrate, a gate electrode, a plurality of contact windows and a plurality of gap walls. The gate is divided into a plurality of gate portions by a plurality of slits. Each contact window includes an upper part and a lower part connected to each other. The lower part is located in the slit. The upper part is on the lower part and spans the slit. The gap walls are respectively located between the gate portion and the contact window.

According to an embodiment of the present invention, in the above-mentioned transistor structure, each gate portion may have a first end and a second end. Two adjacent first ends of two adjacent gate portions may be connected to each other. Two adjacent gate parts can be integrally formed.

According to an embodiment of the present invention, in the above-mentioned transistor structure, two adjacent second ends of two adjacent gate portions can be connected to each other.

According to an embodiment of the present invention, in the above-mentioned transistor structure, each gate portion has a first end and a second end. Two adjacent first ends of two adjacent gate parts may be disconnected from each other, and two adjacent second ends of two adjacent gate parts may be disconnected from each other, so that two adjacent gate parts Can be separated from each other.

According to an embodiment of the present invention, the above-mentioned transistor structure may further include a plurality of doped regions. The doped regions are respectively located in the substrate exposed by the spacer in the slit.

According to an embodiment of the present invention, the above-mentioned transistor structure can be applied to a current mirror structure.

The present invention provides a method for manufacturing a transistor structure, which includes the following steps. Provide a base. A gate is formed on the substrate. The gate is divided into a plurality of gate portions by a plurality of slits. A gap wall is formed in the slit. The gap walls are respectively located on the side walls of the gate portion. A dielectric layer is formed on the gate electrode. The dielectric layer fills the slit and covers the gap wall. A patterning process is performed on the dielectric layer to remove the dielectric layer in the slit, and a plurality of first openings are formed in the dielectric layer. Each first opening spans the corresponding slit. A plurality of first contact windows are formed. Each first contact window is filled with the corresponding first opening and slit.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned transistor structure may further include the following steps. Doping regions are respectively formed in the substrate exposed by the spacers in the slits.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned transistor structure may further include the following steps. Before forming the gate, a gate dielectric material layer is formed on the substrate. After performing a patterning process on the dielectric layer, part of the gate dielectric material layer exposed by the spacer in the slit is removed to form a gate dielectric layer.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned transistor structure may further include the following steps. After forming the first contact window, a second opening exposing the gate is formed in the dielectric layer. A second contact window electrically connected to the gate is formed in the second opening.

Based on the above, in the transistor structure and its manufacturing method proposed in the present invention, the gate is divided into a plurality of gate parts by a plurality of slits, and the contact window is self-aligned by the spacer in the slit. The self-aligned contact (SAC) is formed, so the distance between the contact window on both sides of the gate part and the gate part can be fixed by the gap wall in the slit. In this way, it is possible to prevent the mismatch problem of the drain saturation current (Idsat) between the transistor elements, thereby improving the electrical performance of the transistor elements. For example, when the distance between the contact windows on both sides of the gate part and the gate part needs to be equal, the influence of the overlap and offset of the lithography process can be avoided, so that the contact windows on both sides of the gate part The distance between the gate and the gate is equal. In addition, the positions of doped regions (eg, source regions, drain regions, or lightly doped drain (LDD) regions) formed in the substrate can be fixed by slits and/or spacers, Therefore, it helps to fix the distance between the above-mentioned doped region and the gate electrode, thereby improving the electrical performance of the transistor element. In addition, since the size of the slit affects the implantation amount of the pocket doped region, the size of the slit can be adjusted to form transistor elements with different threshold voltages (Vt), which can save a lot of use. For adjusting the threshold voltage of the mask.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1A is a top view of a transistor structure according to an embodiment of the invention. 1B and 1C are top views of transistor structures according to other embodiments of the present invention. 2A to 2I are cross-sectional views of the manufacturing process of the transistor structure along the section line I-I' in FIG. 1A. In the top views of FIGS. 1A to 1C, in order to clearly illustrate the relationship between the components, some of the components in the cross-sectional view of FIG. 2I are omitted.

1A and 2A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. There may be an isolation structure 102 in the substrate 100. The active area AA can be defined in the substrate by the isolation structure 102. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 102 is silicon oxide, for example.

Next, a gate dielectric material layer 104 can be formed on the substrate 100. The material of the gate dielectric material layer 104 is silicon oxide, for example. The method for forming the gate dielectric material layer 104 is, for example, a thermal oxidation method.

Then, a gate electrode 106 is formed on the substrate 100. For example, the gate electrode 106 may be formed on the gate dielectric material layer 104. The gate 106 is divided into a plurality of gate portions GP by a plurality of slits S. In addition, the channel length CL can be defined by the distance between two adjacent slits S. In this embodiment, the gate 106 is divided into three gate parts GP by two slits S as an example, but the present invention is not limited to this. The gate electrode 106 may be a single-layer structure or a multi-layer structure. In this embodiment, the gate electrode 106 is an example of a two-layer structure including a conductive layer 108 and a conductive layer 110, but the invention is not limited to this. In other embodiments, the gate electrode 106 may have a single-layer structure or a multi-layer structure with more than three layers. The material of the conductive layer 108 is, for example, doped polysilicon. The material of the conductive layer 110 is, for example, metal silicide, such as tungsten silicide (WSi). In addition, a hard mask layer 112 may be formed on the gate electrode 106. The material of the hard mask layer 112 is, for example, silicon nitride.

In addition, the formation method of the gate electrode 106 (the conductor layer 108 and the conductor layer 110), the hard mask layer 112 and the slit S may include the following steps, but the present invention is not limited thereto. First, a first conductive material layer, a second conductive material layer, and a hard mask material layer (not shown) can be sequentially formed on the gate dielectric material layer 104. Then, the hard mask material layer, the second conductive material layer, and the first conductive material layer can be patterned to form the hard mask layer 112, the conductive layer 110, the conductive layer 108, and the slit S.

In addition, each gate portion GP may have a first end E1 and a second end E2. In this embodiment, as shown in FIG. 1A, two adjacent first ends E1 of two adjacent gate portions GP may be connected to each other, and two adjacent second ends E2 of two adjacent gate portions GP It may not be connected to each other, and two adjacent gate portions GP may be integrally formed, but the present invention is not limited to this. In other embodiments, as shown in FIG. 1B, two adjacent first ends E1 of two adjacent gate portions GP may be connected to each other, and two adjacent second ends of two adjacent gate portions GP E2 can be connected to each other, and two adjacent gate parts GP can be integrally formed. In other embodiments, as shown in FIG. 1C, two adjacent first ends E1 of two adjacent gate portions GP may not be connected to each other, and two adjacent first ends E1 of two adjacent gate portions GP The two ends E2 can be disconnected from each other, so that two adjacent gate portions GP can be separated from each other.

Referring to FIG. 2B, pocket doped regions 114 may be formed in the substrate 100 below both sides of the gate electrode 106. In addition, the size of the slit S affects the implantation amount of the pocket doped region 114. For example, when the size of the slit S is larger, the implantation amount of the pocket doped region 114 is larger. When the size of the slit S is small, the implantation amount of the pocket doped region 114 is small. Therefore, by adjusting the size of the slit S, transistor elements with different threshold voltages (Vt) can be formed, and many photomasks for adjusting the threshold voltage can be omitted. The method of forming the pocket doped region 114 is, for example, an oblique angle ion implantation method.

Then, a lightly doped drain region 116 may be formed in the substrate 100 exposed by the slit S. The method of forming the lightly doped drain region 116 is, for example, an ion implantation method.

2C, a gap wall 118 is formed in the slit S. The spacers 118 are respectively located on the sidewalls of the gate portion GP, and may be located on the sidewalls of the hard mask layer 112. In some embodiments, the gap wall 118 and the hard mask layer 112 may be the same material. The material of the spacer 118 is silicon nitride, for example. The method for forming the spacer 118 is, for example, to conformally form a spacer material layer (not shown) in the slit S, and then perform an etch-back process (for example, a dry etching process) on the spacer material layer.

Then, doped regions 120 may be formed in the substrate 100 exposed by the spacer 118 in the slit S, respectively. The doped region 120 can be used as a source region or a drain region, respectively. The formation method of the doped region 120 is, for example, an ion implantation method.

Referring to FIG. 2D, a dielectric layer 122 is formed on the gate electrode 106. For example, the dielectric layer 122 may be formed on the hard mask layer 112. The dielectric layer 122 fills the slit S and covers the gap wall 118. The material of the dielectric layer 122 is, for example, a silicon oxide material such as borophosphosilicate glass (BPSG). The formation method of the dielectric layer 122 is, for example, a chemical vapor deposition method.

2E, a patterning process is performed on the dielectric layer 122 to remove the dielectric layer 122 in the slit, and a plurality of openings OP1 are formed in the dielectric layer 122. Each opening OP1 spans the corresponding slit S. For example, the patterning process on the dielectric layer 122 may include the following steps. First, a patterned photoresist layer 124 is formed on the dielectric layer 122. The patterned photoresist layer 124 can be formed by a photolithography process. Then, the patterned photoresist layer 124 can be used as a mask to remove part of the dielectric layer 122. The method for removing part of the dielectric layer 122 is, for example, a dry etching method.

In addition, the patterned photoresist layer 124 can be used as a mask to remove part of the gate dielectric material layer 104 exposed by the spacer 118 in the slit S to form the gate dielectric layer 104a. The method for removing the partial gate dielectric material layer 104 is, for example, a dry etching method.

Referring to FIG. 2F, the patterned photoresist layer 124 can be removed. The removal method of the patterned photoresist layer 124 is, for example, a dry stripping method or a wet stripping method.

Next, a plurality of contact windows 126 are formed. Each contact window 126 is filled with the corresponding opening OP1 and the slit S. The contact window 126 may be electrically connected to the corresponding doped region 120. The material of the contact window 126 is, for example, metal such as tungsten (W). The method of forming the contact window 126 is, for example, a damascene method.

Then, a wire 128 may be formed on the dielectric layer 122 and the contact window 126. The wire 128 may be electrically connected to the corresponding contact window 126. The material of the wire 128 is, for example, metal such as aluminum (Al), copper (Cu), or aluminum copper alloy (AlCu). The wire 128 may be formed by a deposition process, a lithography process, and an etching process.

Referring to FIG. 2G, a dielectric layer 130 covering the dielectric layer 122 and the wires 128 can be formed. The material of the dielectric layer 130 is silicon oxide, for example. The formation method of the dielectric layer 130 is, for example, a chemical vapor deposition method. Then, the dielectric layer 130 may be subjected to a planarization process. The planarization process is, for example, a chemical mechanical polishing process.

Referring to FIG. 2H, a patterned photoresist layer 132 may be formed on the dielectric layer 130. The patterned photoresist layer 132 can be formed by a photolithography process. Then, the patterned photoresist layer 132 can be used as a mask to remove part of the dielectric layer 130, part of the dielectric layer 122, and part of the hard mask layer 112. Thereby, an opening OP2 exposing the gate electrode 106 can be formed in the dielectric layer 130, the dielectric layer 122, and the hard mask layer 112, and an opening OP3 exposing the wire 128 can be formed in the dielectric layer 130. The method for removing part of the dielectric layer 130, part of the dielectric layer 122 and part of the hard mask layer 112 is, for example, a dry etching method.

In this embodiment, the same mask is used to form the opening OP2 and the opening OP3, thereby reducing the number of masks, but the invention is not limited to this. In other embodiments, the opening OP2 and the opening OP3 can also be formed by different masks.

Please refer to FIG. 2I, the patterned photoresist layer 132 can be removed. The removal method of the patterned photoresist layer 124 is, for example, a dry peeling method or a wet peeling method.

Then, a contact window 134 electrically connected to the gate electrode 106 may be formed in the opening OP2, and a via 136 electrically connected to the wire 128 may be formed in the opening OP3. The material of the contact window 134 and the via 136 is, for example, metal such as tungsten. The method of forming the contact window 134 and the via 136 is, for example, a damascene method.

Hereinafter, the transistor structure 10 of this embodiment will be described with reference to FIGS. 1 and 2I. In addition, although the method for forming the transistor structure 10 is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

1 and FIG. 2I, the transistor structure 10 includes a substrate 100, a gate electrode 106, a plurality of contact windows 126 and a plurality of spacers 118. The transistor structure 10 can be applied to various transistor elements. For example, the transistor structure 10 can be applied to an integrated circuit design of an analog circuit, such as a current mirror. The gate 106 is divided into a plurality of gate portions GP by a plurality of slits S. Each contact window 126 includes an upper part UP and a lower part LP connected to each other. The upper part UP and the lower part LP can be integrally formed. The lower part is located in the slit S. The upper part UP is located on the lower part LP and straddles the slit S. That is, the length L1 of the upper portion UP of the contact window 126 may be greater than the width W1 of the slit S. The extending direction of the length L1 and the extending direction of the width W1 may be parallel to the extending direction of the channel length CL. The gap walls 118 are respectively located between the gate portion GP and the contact window 126.

In addition, the transistor structure 10 may further include a gate dielectric layer 104a, a hard mask layer 112, a pocket doped region 114, a lightly doped drain region 116, a doped region 120, a dielectric layer 122, a wire 128, a dielectric At least one of the layer 130, the contact window 134, and the via 136. The gate dielectric layer 104 a is located between the gate electrode 106 and the substrate 100. The hard mask layer 112 is located on the gate 106. The pocket doped regions 114 are located in the substrate 100 below both sides of the gate 106. The lightly doped drain region 116 is located in the substrate 100 under the spacer 118. The doped regions 120 are respectively located in the substrate 100 exposed by the spacer 118 in the slit S. The dielectric layer 122 is located on the hard mask layer 112. The upper part UP of the contact window 126 may be located in the dielectric layer 122. The wire 128 is electrically connected to the contact window 126. The dielectric layer 130 covers the dielectric layer 122 and the wires 128. The contact window 134 is located in the dielectric layer 130, the dielectric layer 122 and the hard mask layer 112. The contact window 134 is electrically connected to the gate electrode 106. The via 136 is located in the dielectric layer 130. The via 136 is electrically connected to the wire 128.

In addition, the materials, arrangement methods, formation methods and effects of the components in the transistor structure 10 have been described in detail in the above-mentioned embodiments, and will not be described here.

Based on the above embodiment, in the transistor structure 10 and the manufacturing method thereof, the gate 106 is divided into a plurality of gate portions GP by a plurality of slits S, and the contact window 126 is formed by the gap wall 118 in the slit S. A self-aligned contact window (SAC) formed by self-alignment, so the distance D1 between the contact window 126 on both sides of the gate portion GP and the gate portion GP can be fixed by the spacer 118 in the slit S . In this way, the problem of mismatch between the drain saturation current (Idsat) between the transistor elements can be prevented, and the electrical performance of the transistor elements can be improved. For example, when the distance D1 between the contact window 126 on both sides of the gate part GP and the gate part GP needs to be equal, the influence of the overlap offset of the lithography process can be avoided, so that the gate part GP The distance between the contact window 126 on both sides and the gate portion GP is equal.

In addition, the position of the doped region (for example, the doped region 120 or the lightly doped drain region 116) formed in the substrate 100 can be fixed by the slit S and/or the spacer 118, thereby helping to fix the aforementioned The distance between the doped region and the gate 106 further improves the electrical performance of the transistor element.

In addition, since the size of the slit S affects the implantation amount of the pocket doped region 114, the size of the slit S can be adjusted to form transistor elements with different threshold voltages (Vt), which can save a lot of use. For adjusting the threshold voltage of the mask.

FIG. 3 is a top view of a current mirror structure according to an embodiment of the invention. The cross-sectional view of the current mirror structure 20 in FIG. 3 along the section line II-II' may be the cross-sectional view as shown in FIG. 2I. In the top view of FIG. 3, in order to clearly illustrate the relationship between the components, some of the components in the cross-sectional view of FIG. 2I are omitted.

Please refer to FIG. 1A, FIG. 2I and FIG. 3, the transistor structure 10 of FIG. 1A and FIG. 2I can be applied to the current mirror structure 20 of FIG. The difference between the current mirror structure 20 of FIG. 3 and the transistor structure 10 of FIG. 1A is as follows. The number of slits S of the current mirror structure 20 and the transistor structure 10 are different. In addition, in the current mirror structure 20 of FIG. 3, two adjacent first ends E1 of two adjacent gate portions GP are connected to each other, and two adjacent second ends E2 of two adjacent gate portions GP are connected to each other. Are connected to each other, but the present invention is not limited to this. In other embodiments, two adjacent gate portions GP of the current mirror structure 20 may be connected to each other only through two adjacent first ends E1 or only through two adjacent second ends E2. In other embodiments, two adjacent first ends E1 of two adjacent gate portions GP of the current mirror structure 20 may not be connected to each other, and the phases of two adjacent gate portions GP of the current mirror structure 20 The two adjacent second ends E2 can be disconnected from each other, so that the two adjacent gate portions GP can be separated from each other. In addition, the current mirror structure 20 may further include a drain line DL1, a drain line DL2, and a source line SL. The drain line DL1, the drain line DL2, and the source line SL can be respectively electrically connected to the corresponding doped region 120 through the corresponding contact window 126 (FIG. 2I).

In summary, in the transistor structure and manufacturing method of the foregoing embodiment, since the contact window is a self-aligned contact window (SAC), the gap between the contact window on both sides of the gate part and the gate part can be fixed. distance. In this way, the problem of mismatch between the transistor elements can be prevented, and the electrical performance of the transistor elements can be improved. In addition, the position of the doped region formed in the substrate can be fixed by slits and/or spacers, thereby helping to fix the distance between the above-mentioned doped region and the gate electrode, thereby improving the electrical properties of the transistor element Performance. In addition, the size of the slits can be adjusted to form transistor elements with different threshold voltages, so that many photomasks for adjusting threshold voltages can be omitted.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Transistor structure

20: Current mirror structure

100: base

102: Isolation structure

104: gate dielectric material layer

104a: Gate dielectric layer

106: Gate

108, 110: Conductor layer

112: hard mask layer

114: pocket doped area

116: Lightly doped drain region

118: Clearance Wall

120: doped area

122, 130: Dielectric layer

124, 132: Patterned photoresist layer

126,134: Contact window

128: Wire

136: Interlayer window

AA: active area

CL: Channel length

D1: distance

E1: first end

E2: second end

GP: Gate

L1: length

LP: Lower

OP1, OP2, OP3: opening

S: slit

UP: Upper

W1: width

FIG. 1A is a top view of a transistor structure according to an embodiment of the invention. 1B and 1C are top views of transistor structures according to other embodiments of the present invention. 2A to 2I are cross-sectional views of the manufacturing process of the transistor structure along the section line I-I' in FIG. 1A. FIG. 3 is a top view of a current mirror structure according to an embodiment of the invention.

10: Transistor structure

100: base

104a: Gate dielectric layer

106: Gate

108, 110: Conductor layer

112: hard mask layer

114: pocket doped area

116: Lightly doped drain region

118: Clearance Wall

120: doped area

122, 130: Dielectric layer

126,134: Contact window

128: Wire

136: Interlayer window

CL: Channel length

D1: distance

GP: Gate

L1: length

LP: Lower

OP1, OP2, OP3: opening

S: slit

UP: Upper

W1: width

Claims (9)

A transistor structure, comprising: a substrate; a gate, divided into a plurality of gate parts by a plurality of slits, wherein each of the gate parts has a first end and a second end, and two adjacent gate parts are adjacent to each other The two adjacent first ends of the two adjacent ones are connected to each other, and the two adjacent gate portions are integrally formed; a plurality of contact windows, wherein each of the contact windows includes an upper part and a lower part connected to each other, the lower part Located in the slit, the upper part is located on the lower part and spans the slit; and a plurality of gap walls are respectively located between the plurality of gate portions and the plurality of contact windows. A transistor structure, comprising: a substrate; a gate, divided into a plurality of gate parts by a plurality of slits, wherein each of the gate parts has a first end and a second end, and two adjacent gate parts are adjacent to each other Two adjacent first ends of two adjacent gate portions are connected to each other, two adjacent second ends of two adjacent gate portions are connected to each other, and two adjacent gate portions are integrally formed; more Contact windows, wherein each of the contact windows includes an upper part and a lower part connected to each other, the lower part is located in the slit, the upper part is located on the lower part and spans the slit; and a plurality of gap walls, They are respectively located between the plurality of gate portions and the plurality of contact windows. The transistor structure according to claim 1 or 2, further comprising: a plurality of doped regions, respectively located in the substrate exposed by the plurality of spacers in the plurality of slits. The transistor structure according to claim 1 or 2, which is applied to a current mirror structure. A method for manufacturing a transistor structure includes: providing a substrate; forming a gate on the substrate, wherein the gate is divided into a plurality of gate portions by a plurality of slits, wherein each of the gate portions has a first end and At the second end, two adjacent first ends of two adjacent gate parts are connected to each other, and two adjacent gate parts are integrally formed; A spacer, wherein a plurality of the spacers are respectively located on the sidewalls of a plurality of the gate portions; a dielectric layer is formed on the gate, wherein the dielectric layer fills the plurality of slits and covers A plurality of the spacers; performing a patterning process on the dielectric layer to remove the dielectric layer in the plurality of slits, and a plurality of first openings are formed in the dielectric layer, Wherein each of the first openings spans the corresponding slit; and a plurality of first contact windows are formed, wherein each of the first contact windows is filled with the corresponding first opening and the slit . A method for manufacturing a transistor structure includes: providing a substrate; A gate is formed on the substrate, wherein the gate is divided into a plurality of gate parts by a plurality of slits, wherein each of the gate parts has a first end and a second end, and two adjacent gate parts are adjacent to each other. Two adjacent first ends of two adjacent gate parts are connected to each other, two adjacent second ends of two adjacent gate parts are connected to each other, and two adjacent gate parts are integrally formed; A plurality of spacers are formed in the plurality of slits, wherein the plurality of spacers are respectively located on the sidewalls of the plurality of gate portions; a dielectric layer is formed on the gate, wherein the dielectric layer is filled Insert a plurality of the slits and cover a plurality of the spacers; perform a patterning process on the dielectric layer to remove the dielectric layer in the plurality of slits, and in the dielectric A plurality of first openings are formed in the layer, wherein each of the first openings spans the corresponding slit; and a plurality of first contact windows are formed, wherein each of the first contact windows is filled with a corresponding The first opening and the slit. The manufacturing method of the transistor structure according to claim 5 or 6, further comprising: forming a doped region in the substrate exposed by the plurality of spacers in the plurality of slits, respectively. The manufacturing method of the transistor structure according to claim 5 or 6, further comprising: forming a gate dielectric material layer on the substrate before forming the gate; and patterning the dielectric layer After the manufacturing process, a portion of the gate dielectric material layer exposed by the plurality of spacers in the plurality of slits is removed to form a gate dielectric layer. The manufacturing method of the transistor structure according to claim 5 or 6, further comprising: forming a second opening in the dielectric layer that exposes the gate electrode after forming a plurality of the first contact windows; And a second contact window electrically connected to the gate is formed in the second opening.

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