TWI736645B - Display driver integrated circuit and electronic device - Google Patents

Abstract

Disclosed is a display driver integrated circuit which includes a first booster that generates a first boosting voltage by boosting at least one of first and second power supply voltages, a second booster that generates the first boosting voltage or a second boosting voltage by boosting at least one of the first and second power supply voltages, a first regulator that generates a first output voltage based on at least one of the first boosting voltages generated by the first and second boosters, and a second regulator that generates a second output voltage based on the second boosting voltage.

Description

Display driver integrated circuit and electronic device

This application is based on 35 USC § 119 and claims that the Korean Patent Application No. 10-2016-0105372 filed with the Korean Intellectual Property Office on August 19, 2016 and filed with the Korean Intellectual Property Office on November 14, 2016 The priority of application No. 10-2016-0151425, and the entire content of each of the Korean patent applications are incorporated into this case for reference.

Some exemplary embodiments of the inventive concept disclosed herein are related to an electronic device, and more specifically, to a configuration of a display driver integrated circuit supporting various operation modes and an operation method thereof.

Generally speaking, electronic devices such as laptop computers, tablet personal computers (PC), smart phones, and wearable devices may include display devices. Display devices used in electronic devices can be implemented in various forms, and can include organic light-emitting diodes (OLED) and active matrix organic light-emitting diodes (AMOLED) , Liquid crystal display (LCD), electrophoretic display Device, electrowetting display, and plasma display (PDP).

The voltage generated by a power management circuit (such as a power management integrated circuit (PMIC)) may not be enough to directly drive the display device. Therefore, in order to drive the display device, a display driver integrated circuit for processing (or generating) voltage is desired.

However, power may be consumed unnecessarily when processing the voltage. Therefore, it is desirable to reduce power consumption in the process of generating the voltage used by the display driver integrated circuit to drive the display device.

An exemplary embodiment of the inventive concept provides a display driver integrated circuit supporting various operation modes of a display device.

According to an exemplary embodiment of the inventive concept, a display driver integrated circuit includes: a first booster, which generates a first booster by boosting at least one of a first power supply voltage and a second power supply voltage A boosted voltage; a second booster that generates the first boosted voltage or the second boosted voltage by boosting at least one of the first power supply voltage and the second power supply voltage A boosted voltage; a first regulator that generates a first output voltage based on at least one of the first boosted voltages generated by the first booster and the second booster; and The second regulator generates a second output voltage based on the second boosted voltage.

According to another exemplary embodiment of the inventive concept, an electronic device includes a display driver integrated circuit and a first A display panel driven by the output voltage and the second output voltage. The display driver integrated circuit includes: a first booster that generates a first boosted voltage by boosting at least one of a first power supply voltage and a second power supply voltage; and a second boost A device for generating the first boosted voltage or the second boosted voltage by boosting at least one of the first power supply voltage and the second power supply voltage; a first regulator, A first output voltage is generated based on at least one of the first boosted voltage generated by the first booster and the second booster; and a second regulator is based on the second booster The voltage is boosted to generate a second output voltage.

According to another exemplary embodiment of the inventive concept, a display driver integrated circuit includes: a boost circuit, which generates a first power supply voltage by boosting at least one of a first power supply voltage and a second power supply voltage A boosted voltage and generating the first boosted voltage or the second boosted voltage by boosting at least one of the first power supply voltage and the second power supply voltage; and regulation The circuit generates a first output voltage based on the first boosted voltage, and generates a second output voltage based on the second boosted voltage.

According to another exemplary embodiment of the inventive concept, an electronic device includes: a display panel configured to display images; a power management integrated circuit configured to generate an external voltage; and a display driver integrated circuit configured to select At least one of the two modes. In the first mode, the display driver integrated circuit is configured to provide a first output voltage to the display panel, and the power management integrated circuit is configured to provide the external voltage to the display panel , The absolute value of the external voltage is less than the absolute value of the first output voltage. In the second mode The display driver is configured to provide the first output voltage and the second output voltage to the display panel, and the absolute value of the second output voltage is less than the absolute value of the first output voltage and less than the absolute value of the first output voltage. Describe the absolute value of the external voltage.

1000, 6000: electronic device

1100, 2100, 3100, 4100, 5100, 6100: display driver integrated circuit

1110: switch circuit

1120: Boost circuit

1121, 3121, 4121, 5121: first booster (booster)

1122, 3122, 4122, 5122: second booster (booster)

1130: regulating circuit

1131, 5131: the first regulator (regulator)

1132, 5132: second regulator (regulator)

1200, 5200c, 5200d, 6200: power management integrated circuit

1300, 6300: display panel

2110, 3110, 4110, 5110: the first switch circuit

2121: The first booster

2122: second booster

2131, 3131, 4131, 5131a, 5131b, 5131c, 5131d: first tune Constrictor

2132, 3132, 4132, 5132a, 5132b, 5132c, 5132d: second regulator

2140: The second switch circuit (switch circuit)

2140a, 2140b, 3140, 4140, 5140, 5140a, 5140b, 5140c, 5140d: second switch circuit

3150, 4150, 5150: Controller

4133, 5133a, 5133b, 5133c, 5133d: third regulator

5133: Third regulator (regulator)

5200a: External power management integrated circuit (power management integrated circuit)

5200b: External power management integrated circuit

6400: Gate driver

6500: timing controller

CLK1: the first clock (clock)

CLK2: second clock (clock)

CST: Capacitor

CTRL1, CTRL2, CTRL3: control signal

D-RGB: image data

DCS: data control signal (control signal)

DL1~DLm: data line

Dk: Data signal

DLk: kth data line

EA: Error amplifier

Ei: the i-th transmit control signal

Ei-1: (i-1) transmit control signal

EL1, EL2, EL3~ELn: emission line

ELi: i-th launch control line

ELi-1: (i-1) launch control line

ELVDD: the first voltage (voltage)

ELVSS: second voltage (voltage)

ENB1, ENB2: Enabling signal

GCS: Gate control signal

IL: Initialization line

N1: the first node

N2: second node

OLED: organic light emitting diode

OPR: Turn on pixel ratio

PL: Power cord

PT: Transmission Transistor

PX: pixel

R1: first resistor

R2: second resistor

SEL: select signal

SEL1: First selection signal (selection signal)

SEL2: Second selection signal (selection signal)

Si: i-th scan signal

SL1: the first scan line

SL2: second scan line

SL3: Third scan line

SL4~SLn: scan line

SLi: i-th scan line

SW1: The first switch (switch)

SW2: The second switch (switch)

SW3: The third switch (switch)

SW4: The fourth switch (switch)

SW5, SW6, SW7: switch

TR1: The first transistor (thin film transistor)

TR2: second transistor (thin film transistor)

TR3: Third Transistor (Thin Film Transistor)

TR4: Fourth Transistor (Thin Film Transistor)

TR5: Fifth Transistor (Thin Film Transistor)

TR6: Sixth Transistor (Thin Film Transistor)

U_ELVDD: third voltage (voltage)

U_ELVSS: Fourth voltage (voltage, negative voltage)

VB1: The first boost voltage (boost voltage, voltage)

VB2: second boost voltage (boost voltage, voltage)

Vext: external voltage (voltage)

VGH: Voltage

VGL: Voltage (negative voltage)

VINT: Voltage (negative voltage, initialization voltage)

VO1: The first output voltage (output voltage)

VO2: second output voltage (output voltage)

VO3: The third output voltage (output voltage)

Vref: Reference voltage

VS1: The first power supply voltage (power supply voltage)

VS2: Second power supply voltage (power supply voltage)

VS3: Third power supply voltage (power supply voltage)

VS4~VSn, VSs: power supply voltage

The above and other objectives and features will become apparent by referring to the following figures in conjunction with the following description. Unless otherwise specified, the same reference numbers refer to the same components throughout the figures, in which: Figure 1 is a concept according to the present invention The exemplary embodiment illustrates a block diagram of an electronic device to which a display driver integrated circuit is applied.

FIG. 2 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

FIG. 3 is a block diagram illustrating the configuration of the switch circuit shown in FIG. 2. FIG.

4 is a diagram illustrating the operation waveforms of the switches constituting the switching circuit and the waveforms of the control signals used to operate in any of various low-power modes.

Fig. 5 is a diagram illustrating the configuration of the regulator shown in Fig. 2.

FIG. 6 is a block diagram illustrating the operation of the electronic device in a normal mode.

FIG. 7 is a block diagram illustrating the operation of the electronic device in a low power mode.

FIG. 8 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

9A and 9B are diagrams illustrating the configuration of the second switch circuit shown in FIG. 8.

FIG. 10 illustrates the display driver shown in FIG. 1 according to an exemplary embodiment of the concept of the present invention; Block diagram of the integrated circuit of the device.

FIG. 11 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

FIG. 12 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

13A to 13D are block diagrams illustrating the operation of the display driver integrated circuit in various operation modes.

Fig. 14 is a block diagram for explaining the operation of the controller shown in Fig. 12.

15 is a block diagram illustrating the configuration of an electronic device to which a display driver integrated circuit is applied according to an exemplary embodiment of the inventive concept.

Fig. 16 is an equivalent circuit diagram of the pixel shown in Fig. 15.

Hereinafter, to the extent that a person with ordinary knowledge in the art can easily implement the concept of the present invention, exemplary embodiments of the concept of the present invention will be described in detail and clearly.

FIG. 1 is a block diagram illustrating an electronic device 1000 to which a display driver integrated circuit 1100 is applied according to an exemplary embodiment of the inventive concept. 1, the electronic device 1000 may include a display driver integrated circuit 1100, a power management integrated circuit 1200, and a display panel 1300.

The display driver integrated circuit 1100 can drive the display panel 1300. For example, the display driver integrated circuit 1100 can generate a gray scale voltage corresponding to the image data received from the outside, and can output the gray scale voltage to the display surface 板1300.

The display driver integrated circuit 1100 can support various operation modes in which the display panel 1300 operates in various low power modes and normal modes. For example, when no input from the user is received during the reference time, when the battery level of the electronic device 1000 is lower than the reference level, or when the image is displayed in only one area of the display panel 1300 or when the image When a small amount of information (for example, text information) is included, the display panel 1300 can operate in a low power mode.

The display driver integrated circuit 1100 can provide various voltages to the display panel 1300 to display images on the display panel 1300. For example, the second output voltage VO2 shown in FIG. 1 may be a voltage used in the low power mode of the display panel 1300. To simplify the explanation and description, in FIG. 1, the two output voltages VO1 and VO2 are shown as being supplied from the display driver integrated circuit 1100 to the display panel 1300, but the concept of the present invention is not limited to this.

The display driver integrated circuit 1100 may include a switch circuit 1110, a boost circuit 1120, and a regulating circuit 1130 to generate various output voltages VO1 and VO2 to be supplied to the display panel 1300.

The switch circuit 1110 can select at least one of the power supply voltages VS1 and VS2 received from the outside, and the selected power supply voltage can be supplied to the boost circuit 1120. According to various operation modes, only one power supply voltage VS1 or VS2 can be selected, or all power supply voltages VS1 and VS2 can be selected. To make the explanation and description concise, only two power supply voltages VS1 and VS2 are shown in FIG. 1, but three or more power supply voltages can be supplied to the switch circuit 1110, and the concept of the present invention It's not limited to this.

The boost circuit 1120 can boost at least one received power supply voltage to generate boosted voltages VB1 and VB2. The boost circuit 1120 can generate different boost voltages according to the operation mode of the electronic device 1000. For example, in the normal mode, the boost circuit 1120 can generate the first boost voltage VB1. In the low power mode, the boost circuit 1120 can generate the first boost voltage VB1 and the second boost voltage VB2. For example, each of the boosted voltages VB1 and VB2 may be a negative voltage, and the absolute value of the first boosted voltage VB1 may be greater than the absolute value of the second boosted voltage VB2.

The regulating circuit 1130 can generate output voltages VO1 and VO2 based on the first power supply voltage VS1 from the outside and the boosted voltages VB1 and VB2, and the levels of the output voltages VO1 and VO2 are suitable for driving the display panel 1300. For example, the regulating circuit 1130 may include a linear regulator, such as a low dropout (LDO) regulator. For example, each of the output voltages VO1 and VO2 may be a negative voltage, and the absolute value of the first output voltage VO1 may be greater than the absolute value of the second output voltage VO2. For example, the component generating the first output voltage VO1 can be driven by the first power supply voltage VS1 and the first boosted voltage VB1, and the component generating the second output voltage VO2 can be driven by the first power supply voltage VS1 and the second boosted voltage VB2 driver. To simplify the explanation and description, the exemplary embodiment in FIG. 1 is shown as the regulating circuit 1130 generating only two output voltages. However, the exemplary embodiments of the inventive concept may not be limited to this.

The regulating circuit 1130 can generate different output voltages according to different operating modes of the electronic device 1000. For example, in the normal mode, the adjustment circuit 1130 The first output voltage VO1 may be generated but the second output voltage VO2 may not be generated. In the normal mode, the display panel 1300 can be driven by the first output voltage VO1 and the external voltage Vext. The external voltage Vext is independently generated by the power management integrated circuit 1200.

In contrast, in the low power mode, the regulating circuit 1130 can generate the first output voltage VO1 and the second output voltage VO2. In the low power mode, the display panel 1300 can be driven by the first output voltage VO1 and the second output voltage VO2, and the power management integrated circuit 1200 may not generate the external voltage Vext.

A separate controller provided in the display driver integrated circuit 1100 or on the outside thereof can perform the following operations: the operation of selecting any one of the power supply voltages VS1 and VS2 at the switch circuit according to various operating modes, The operation of generating various levels of boosted voltage at the voltage circuit 1120, the operation of generating various levels of output voltage at the regulating circuit 1130, and the operation of generating an external voltage Vext at the power management integrated circuit 1200. For example, if the controller is disposed on the outside of the display driver integrated circuit 1100, the controller may be a timing controller that controls the overall operation of the display driver integrated circuit 1100.

The power management integrated circuit 1200 can generate power supply voltages (for example, VS1 and VS2) to drive the display driver integrated circuit 1100. The power management integrated circuit 1200 can generate the external voltage Vext to drive the display panel 1300 in the normal mode. For example, the power management integrated circuit 1200 may include a voltage converter (not shown in the figure) that generates a voltage with a level suitable for driving the display driver integrated circuit 1100. As another option, the voltage converter can be provided as an independent separate circuit instead of being provided in the power management integrated circuit 1200.

The display panel 1300 may include a plurality of pixels. The output voltages VO1 and VO2 from the regulating circuit 1130 can drive the display panel 1300. The display panel 1300 can output a gray-scale voltage corresponding to the image data.

Meanwhile, in an exemplary embodiment of the inventive concept, the boost circuit 1120 generating a separate boost voltage VB2 in the low power mode may be associated with the power consumption and efficiency of the display driver integrated circuit 1100. Generally speaking, a certain (certain, specific, etc.) voltage drop may occur during the adjustment process of the adjustment circuit 1130. For example, the levels of the first boost voltage VB1 from the boost circuit 1120 and the output voltages VO1 and VO2 from the regulation circuit 1130 may be negative. Therefore, the absolute value of the first boosted voltage VB1 is the largest, and the absolute value of the second output voltage VO2 is the smallest. If the regulating circuit 1130 uses the first boosted voltage VB1 to generate the second output voltage VO2 in the low power mode, an undesired boost or excessive boost of the boost circuit 1120 may occur. In addition, since the regulating circuit 1130 uses an excessively boosted voltage to generate an output voltage, the power consumption of the regulating circuit 1130 may increase.

Therefore, in order to solve the problem, the boost circuit 1120 of the display driver integrated circuit 1100 generates a separate boost voltage VB2 in the low power mode. For example, in the low power mode, the boost circuit 1120 can not only generate the first boost voltage VB1 for generating the first output voltage VO1, but the boost circuit can also generate the second output voltage VO2. The second boosted voltage VB2. For example, the second boosted voltage VB2 may be a negative voltage, and the absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1.

According to the above configuration, in the low-power mode, there is no need to over-boost to produce The output voltage VO2 for driving the display panel 1300 is generated. Therefore, the inventive concept can make or be suitable for preventing or reducing the increase in power consumption of the adjustment circuit 1130.

FIG. 2 is a block diagram illustrating the display driver integrated circuit 1100 shown in FIG. 1. The display driver integrated circuit 1100 may include a switch circuit 1110, a first booster 1121, a second booster 1122, a first regulator 1131, and a second regulator 1132.

In an exemplary embodiment, the configuration in which the boost circuit 1120 shown in FIG. 1 generates the first boost voltage VB1 may be implemented by the first booster 1121. In addition, the configuration in which the boost circuit 1120 shown in FIG. 1 generates the first boost voltage VB1 or the second boost voltage VB2 can be implemented by the second booster 1122.

In an exemplary embodiment, the configuration in which the regulating circuit 1130 shown in FIG. 1 generates the first output voltage VO1 can be implemented by the first regulator 1131. In addition, the configuration in which the regulating circuit 1130 shown in FIG. 1 generates the second output voltage VO2 can be implemented by the second regulator 1132.

The overall operation of the switching circuit 1110, the boosting circuit 1120, and the adjusting circuit 1130 shown in FIG. 1 is described with reference to FIG. 1, and therefore the same description is omitted.

The first booster 1121 can use at least one of the power supply voltages VS1 and VS2 to generate the first boosted voltage VB1. The power supply voltages VS1 and VS2 can be selected by the switch circuit 1110. For example, the first booster 1121 can generate the first boosted voltage VB1 in the low power mode and the normal mode. This operation can be performed by the control signal CTRL1.

The second booster 1122 can use at least one of the power supply voltages VS1 and VS2 to generate the first boosted voltage VB1 or the second boosted voltage VB2. Electricity The source supply voltages VS1 and VS2 can be selected by the switch circuit 1110. For example, in the normal mode, the first booster 1121 can generate the first boosted voltage VB1 used by the first regulator 1131 to generate the first output voltage VO1. However, according to an exemplary embodiment, the first booster 1121 may not operate in the normal mode. For example, in the low power mode, the second booster 1122 can generate the second boosted voltage VB2 used by the second regulator 1132 to generate the second output voltage VO2. The operation can be performed by the control signal CTRL2. The absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1.

Each of the boosters 1121 and 1122 can be implemented using a charge pump, a switched mode power supply (SMPS), and/or a combination thereof. However, the configuration of the boosters 1121 and 1122 may not be limited to this. The boosters 1121 and 1122 may include various configurations suitable for boosting the input voltage to a specific level and generating a negative voltage by inverting the voltage at the specific level.

Although not shown in FIG. 2, a stabilizing capacitor may be further provided between the ground node and the node through which the first boosted voltage VB1 is output from the first booster 1121. In addition, a stabilizing capacitor may be further provided between the ground node and the node through which the boosted voltages VB1 and VB2 are output from the second booster 1122. The stabilizing capacitor can help the voltages VB1 and VB2 to be more stably supplied to the regulators 1131 and 1132.

FIG. 3 is a block diagram illustrating the configuration of the switch circuit 1110 shown in FIG. 2. The switch circuit 1110 can be controlled so that at least one of the plurality of power supply voltages VS1 and VS2 is supplied to the boosters 1121 and 1122. For example, the switch circuit 1110 can be composed of multiple switches controlled by the selection signal SEL. For example, the selection signal SEL can be generated by a separate controller provided in or on the outside of the display driver integrated circuit 1100.

For example, the switch circuit 1110 may be composed of multiple transistors that are turned on or off by the selection signal SEL. Alternatively or additionally, the switch circuit 1110 can be implemented by using a multiplexer that selects at least one power supply voltage in response to the selection signal SEL. However, the configuration of the switch circuit 1110 may not be limited to this. The switch circuit 1110 may include various components for selecting at least one of a plurality of power supply voltages.

The operation of the switching circuit 1110 and the boosters 1121 and 1122 in the normal mode and the low power mode will be described more fully with reference to FIGS. 2 and 3.

In the normal mode, the first switch SW1 to the fourth switch SW4 can be turned on. In this case, each of the boosters 1121 and 1122 can use the power supply voltages VS1 and VS2 to generate the first boosted voltage VB1. Alternatively, in the normal mode, only the first switch SW1 and the third switch SW3 may be turned on. In this case, each of the boosters 1121 and 1122 can use the power supply voltage VS1 to generate the first boosted voltage VB1. Here, the absolute value of the boosted voltage generated in this situation may be smaller than the absolute value of the boosted voltage generated by using all the power supply voltages VS1 and VS2.

At the same time, in the low power mode, it may be desirable to generate boosted voltages of different levels to prevent or alleviate unnecessary boosting or excessive boosting of the boosting circuit 1120 (refer to FIG. 1) including the boosters 1121 and 1122. For example, by the second booster The second boosted voltage VB2 generated by 1122 may be less than the first boosted voltage VB1 generated by the first booster 1121.

For example, in the low power mode, only the switches SW1, SW2, and SW3 can be turned on. In this case, the first booster 1121 can use the power supply voltages VS1 and VS2 to generate the first boosted voltage VB1, and the second booster 1122 can use the power supply voltage VS1 to generate the second boosted voltage VB2 . In this case, the absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1.

For example, in another low power mode, only the switches SW1, SW2, and SW4 may be turned on. In this case, the first booster 1121 may use the power supply voltages VS1 and VS2 to generate the first boosted voltage VB1, and the second booster 1122 may use the power supply voltage VS2 to generate the second boosted voltage VB2 . In this case, the absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1.

For example, in yet another low power mode, only switches SW1 and SW4 can be turned on. In this case, the first booster 1121 may use the power supply voltage VS1 to generate the first boosted voltage VB1, and the second booster 1122 may use the power supply voltage VS2 to generate the second boosted voltage VB2. In this case, the absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1.

In addition to the switching operation of the switching circuit 1110 for selecting the power supply voltage to be supplied to the boosters 1121 and 1122, the frequency of the clock for operating the boosters 1121 and 1122 can also be adjusted. For example, in the low power mode, the control signal CTRL2 can be used to reduce the clock for operating the second booster 1122 Frequency of. In addition, the levels of the power supply voltages VS1 and VS2 can be changed based on various factors including user requirements and system environment to generate the optimized boost voltage.

4 illustrates the operation waveforms of the switches constituting the switching circuit 1110 and the waveforms of the control signals CTRL1 and CTRL2 for operating the boosters 1121 and 1122 in any of various low power modes.

The control signal CTRL1 for controlling the first booster 1121 may include the enabling signal ENB1 and the clock CLK1, and the control signal CTRL2 for controlling the second booster 1122 may include the enabling signal ENB2 and the clock CLK2. The boosters 1121 and 1122 can be activated by the enable signals ENB1 and ENB2, respectively, and can perform boost operations in response to the clocks CLK1 and CLK2, respectively. In an exemplary embodiment, FIG. 4 shows that in the low power mode, the switches SW1, SW2, and SW4 are turned on. In addition, the frequency of the first clock CLK1 used to drive the first booster 1121 in the low power mode is lower than the frequency of the first clock CLK1 in the normal mode, and is used to drive the first clock CLK1 of the second booster 1122 The frequency of the second clock CLK2 is lower than the frequency of the second clock CLK2 in the normal mode. The first clock CLK1 can be in the same phase or different phases from the second clock CLK2 in the low power mode.

Fig. 5 is a circuit diagram illustrating the configuration of the regulators 1131 and 1132 shown in Fig. 2. For example, each of the regulators 1131 and 1132 may be a linear regulator, such as a low pressure drop regulator. However, the exemplary embodiments of the inventive concept may not be limited to this. For example, the regulators 1131 and 1132 can be changed or modified in various ways to be driven by the boosted voltages VB1 and VB2.

The regulator 1131/the regulator 1132 may include an error amplifier EA, a first resistor R1 and a second resistor R2, and a transmission transistor PT. The reference voltage Vref may be applied to the first input terminal of the error amplifier EA. The output terminal of the error amplifier EA can be connected to the control electrode or the gate electrode of the transmission transistor PT. The first power supply voltage VS1 can be applied to the first or source terminal of the transmission transistor PT, and the output voltage VO1/output voltage VO2 can be output through the second or drain terminal of the transmission transistor PT. The first resistor R1 can be connected between the second input terminal of the error amplifier EA and the source terminal of the transmission transistor PT, and the second resistor R2 can be connected between the second input terminal of the error amplifier EA and the ground node . The transmission transistor PT is shown as a P-type metal oxide semiconductor transistor, but the concept of the present invention is not limited to this.

In the first regulator 1131, the first power supply voltage VS1 can be applied to the first power terminal of the error amplifier EA regardless of the operation mode. In the first regulator 1131, the first boosted voltage VB1 can be applied to the second power terminal of the error amplifier EA regardless of the operation mode. Therefore, the first regulator 1131 can generate the first output voltage VO1 regardless of the operation mode.

The second regulator 1132 can selectively operate based on the operation mode. For example, the second regulator 1132 may not operate in the normal mode. The reason is that the external voltage Vext separately generated by the power management integrated circuit 1200 (refer to FIG. 1) is used instead of the second output voltage VO2 to drive the display panel 1300.

In the second regulator 1132, the first power supply voltage VS1 may be applied to the first power terminal of the error amplifier EA in the low power mode. In the second regulator In 1132, the second boosted voltage VB2 can be applied to the second power terminal of the error amplifier EA. Therefore, the second regulator 1132 can generate the second output voltage VO2 in the low power mode.

In this way, according to the configuration in which the second regulator 1132 is driven by the boosted voltage VB2 separately generated in the low power mode, there is no need to generate an excessively boosted voltage to obtain the second output voltage VO2 of the target level. Therefore, since the power consumption of the second regulator 1132 is reduced, the concept of the present invention can reduce the power consumption of the display driver integrated circuit 1100.

However, the configuration of the regulator 1131 / regulator 1132 shown in FIG. 5 is only an example, and is not limited to this. Unlike the configuration shown in FIG. 5, for example, the first boosted voltage VB1 or the second boosted voltage VB2 can be applied to the first power terminal of the error amplifier EA of the first regulator 1131 and the drain of the transmission transistor PT. Terminal, and the first power supply voltage VS1 can be applied to the second power terminal of the error amplifier EA of the first regulator 1131. In this case, the transmission transistor PT may be an N-type metal oxide semiconductor transistor.

FIG. 5 illustrates that the second boosted voltage VB2 generated separately in the low power mode drives the error amplifier EA of the second regulator 1132. For example, a configuration for generating a boost voltage VB2 with a level different from that of the boost voltage VB1 generated in the normal mode and a configuration in which the regulators 1131 and 1132 are respectively driven by this configuration can be used. It belongs to the scope and spirit of the concept of the present invention.

FIG. 6 is a block diagram illustrating the operation of the electronic device 1000 in a normal mode. Generally speaking, a large amount of power is required to drive the display panel 1300 in the normal mode. to this end, The switch circuit 1110 can be controlled so that the same power supply voltage is supplied to the first booster 1121 and the second booster 1122.

For example, each of the boosters 1121 and 1122 may be supplied with the power supply voltages VS1 and VS2, and each of the boosters 1121 and 1122 may generate the first boosted voltage VB1. The operation can be controlled by the control signals CTRL1 and CTRL2, for example.

However, according to an exemplary embodiment, even if the current operation mode is the normal mode, the second booster 1122 may not operate. For example, the display driver integrated circuit 1100 can be set in consideration of various factors such as the brightness control made by the user and the battery power of the electronic device 1000 so that only the first booster 1121 operates.

As another option, according to an exemplary embodiment, even if the current operation mode is the normal mode, each of the boosters 1121 and 1122 may be supplied with only the first power supply voltage VS1. Similarly, various factors such as brightness control made by the user and battery power of the electronic device 1000 can be considered to control the switch circuit 1110 so that only the first power supply voltage VS1 is supplied to the boosters 1121 and 1122.

The first regulator 1131 (more specifically, the error amplifier EA shown in FIG. 4) can be driven by the first power supply voltage VS1 and the first boosted voltage VB1 generated by the first booster 1121. Alternatively or additionally, in order to stably generate the first output voltage VO1, the first regulator 1131 may be additionally supplied with the first boosted voltage VB1 generated by the second booster 1122. For example, due to the current caused by the first boosted voltage VB1 generated by the first booster 1121 and the first boosted voltage VB1 generated by the second booster 1122 The current caused by a boosted voltage VB1 is all supplied to the first regulator 1131, so the first output voltage VO1 can be generated more stably.

The voltage Vext can be generated by the power management integrated circuit 1200. The voltage Vext may be a level different from the level of the first output voltage VO1 among the voltages expected to drive the display panel 1300 in the normal mode. For example, the external voltage Vext may be a negative voltage, and the absolute value of the external voltage Vext may be less than the absolute value of the first output voltage VO1.

For example, the power management integrated circuit 1200 can generate the external voltage Vext in response to the control signal CTRL3 in the normal mode. For example, the control signal CTRL3 can be received from a controller disposed in or on the outside of the display driver integrated circuit 1100. The power management integrated circuit 1200 can generate the first power supply voltage VS1 to generate the boosted voltages VB1 and/or VB2. In addition, the power management integrated circuit 1200 can generate the first power supply voltage VS1 to drive the error amplifier EA of the first regulator 1131 (refer to FIG. 4).

FIG. 7 is a block diagram illustrating the operation of the electronic device 1000 in a low power mode. Generally speaking, a relatively small amount of power is sufficient to drive the display panel 1300 in the low power mode. In other words, the absolute value of the second output voltage VO2 sufficient to drive the display panel 1300 in the low power mode may be smaller than the absolute value of the external voltage Vext used in the normal mode. Therefore, the switch circuit 1110 can be controlled so that different power supply voltages are supplied to the first booster 1121 and the second booster 1122 respectively.

For example, the first power supply voltage VS1 can be supplied to the first booster 1121 through the switch circuit 1110, and the second power supply voltage VS1 can be supplied through the switch circuit 1110. The supply voltage VS2 is supplied to the second booster 1122. For example, the power management integrated circuit 1200 can generate the first power supply voltage VS1 and the second power supply voltage VS2. However, the exemplary embodiments of the inventive concept may not be limited to this. For example, the first power supply voltage VS1 and/or the second power supply voltage VS2 can be converted into voltages with appropriate levels by a separate voltage converter provided in or on the outside of the power management integrated circuit 1200, and It is sufficient when the level of the first power supply voltage VS1 is higher than the second power supply voltage VS2.

The first power supply voltage VS1 and the first boosted voltage VB1 can drive the first regulator 1131 to generate the first output voltage VO1. The first power supply voltage VS1 and the second boosted voltage VB2 can drive the second regulator 1132 to generate the second output voltage VO2. For example, the absolute value of the first output voltage VO1 may be greater than the absolute value of the second output voltage VO2.

FIG. 8 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept. The display driver integrated circuit 2100 may include a first switch circuit 2110, a first booster 2121, a second booster 2122, a first regulator 2131, a second regulator 2132, and a second switch circuit 2140. According to an exemplary embodiment of the inventive concept, except that the display driver integrated circuit 2100 further includes a second switch circuit 2140, the display driver integrated circuit 2100 is substantially the same as or similar to the embodiment shown in FIG. 2. Therefore, the same description will not be repeated here. However, for clarity of description, the first switch circuit 2110 is shown as being controlled by the first selection signal SEL1.

The second switch circuit 2140 can be configured to respond to the second selection signal SEL2 selectively provides the first boosted voltage VB1 to the first regulator 2131 or selectively provides the second boosted voltage VB2 to the second regulator 2132. For example, the second selection signal SEL2 can be generated by a separate controller provided in or on the outside of the display driver integrated circuit 2100.

For example, in the normal mode, the second switch circuit 2140 can be controlled to provide the first boosted voltage VB1 generated by the second booster 2122 to the first regulator 2131. However, even if the current mode can be the normal mode, the second booster 2122 may not generate the first boosted voltage VB1 due to various factors such as user requirements and/or system environment. In contrast, in the low power mode, the second switch circuit 2140 can be controlled to provide the second boosted voltage VB2 generated by the second booster 2122 to the second regulator 2132.

9A and 9B are diagrams illustrating the configuration of the second switch circuit 2140 shown in FIG. 8. Referring to FIG. 9A, the second switch circuit 2140a may include two switches SW5 and SW6 implemented by transistors, which are turned on or off by the second selection signal SEL2. For example, in the normal mode, the switch SW5 can be turned on by the second selection signal SEL2, and the switch SW6 can be turned off by the selection signal SEL2. However, even if the current mode is the normal mode, if the second booster 2122 does not need to generate the first boosted voltage VB1, the switch SW5 can also be turned off.

Alternatively or additionally, as shown in FIG. 9B, the second switch circuit 2140b may include a switch SW7. The switch SW7 can be configured to provide the first boosted voltage VB1 to the first regulator 2131 or the second boosted voltage VB2 to the second regulator 2132 in response to the second selection signal SEL2.

The above-mentioned configurations of the second switch circuits 2140a and 2140b are only examples, and the exemplary embodiments of the inventive concept may not be limited thereto. The switch circuit 2140 (refer to FIG. 8) can be configured in various ways to provide the first boosted voltage VB1 to the first regulator 2131 in the normal mode or to provide the second boosted voltage VB2 to the second regulator in the low power mode. Adjuster 2132.

10 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept. The display driver integrated circuit 3100 may include a first switch circuit 3110, a first booster 3121, a second booster 3122, a first regulator 3131, a second regulator 3132, a second switch circuit 3140, and a controller 3150 . According to an exemplary embodiment of the inventive concept, except that the display driver integrated circuit 3100 further includes a controller 3150, the display driver integrated circuit 3100 is substantially the same as or similar to the embodiment shown in FIG. 8. Therefore, the same description will not be repeated here.

The controller 3150 can control the switching operation of the first switching circuit 3110, the operation of the first boosters 3121 and 3122 in the normal mode or the low power mode, and the switching operation of the second switching circuit 3140. For example, the controller 3150 can generate selection signals SEL1 and SEL2, enabling signals ENB1 and ENB2, and clocks CLK1 and CLK2 based on control signals from a timing controller (not shown in the figure).

In the normal mode, the controller 3150 can use the first selection signal SEL1 to control the first switch circuit 3110 so that the same power supply voltage is supplied to the boosters 3121 and 3122. The controller 3150 can use the enabling signal ENB2 and the clock CLK2 to control the second booster 3122 so that the second booster 3122 generates the first boosted voltage VB1. The controller 3150 can use the second selection signal SEL2 to control the Two switching circuits 3140, so that the first boosted voltage VB1 generated by the second booster 3122 is provided to the first regulator 3131.

In the normal mode, the display panel 1300 (refer to FIG. 1) can be driven by the first output voltage VO1 from the first regulator 3131 and the external voltage Vext generated by the power management integrated circuit 1200 (refer to FIG. 1).

In the low power mode, the controller 3150 can use the first selection signal SEL1 to control the first switch circuit 3110 so that different power supply voltages are supplied to the boosters 3121 and 3122. The controller 3150 can use the enabling signal ENB2 and the clock CLK2 to control the second booster 3122 so that the second booster 3122 generates the second boosted voltage VB2. For example, the absolute value of the second boosted voltage VB2 may be smaller than the absolute value of the first boosted voltage VB1. The controller 3150 can use the second selection signal SEL2 to control the second switch circuit 3140 so that the second boosted voltage VB2 generated by the second booster 3122 is provided to the second regulator 3132.

In the low power mode, since the second output voltage VO2 from the second regulator 3132 is used instead of the external voltage Vext generated by the power management integrated circuit 1200 (refer to FIG. 1), the power management integrated circuit 1200 does not need to generate External voltage Vext. Therefore, the power management integrated circuit 1200 may not generate the external voltage Vext under the control of the controller 3150. Alternatively or additionally, the operation may be performed under the control of a timing controller (not shown in the figure).

In the low power mode, the display panel 1300 can be driven by the first output voltage VO1 from the first regulator 3131 and the second output voltage VO2 from the second regulator 3132.

FIG. 11 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept. The display driver integrated circuit 4100 may include a first switch circuit 4110, a first booster 4121, a second booster 4122, a first regulator 4131, a second regulator 4132, a third regulator 4133, and a second switch circuit 4140, and controller 4150. According to an exemplary embodiment of the inventive concept, except that the display driver integrated circuit 4100 receives three power supply voltages VS1 to VS3 and further includes a third regulator 4133, the display driver integrated circuit 4100 is substantially the same as or similar to FIG. 10 Example shown. Therefore, the same description will not be repeated here.

In the normal mode, the first switch circuit 4110 can be controlled so that at least one of the power supply voltages VS1 to VS3 is supplied to the boosters 4121 and 4122. For example, the switches SW1 and SW4 can be turned on so that only the first power supply voltage VS1 is supplied to the boosters 4121 and 4122. As another alternative or in addition, the switches SW1, SW2, SW4, and SW5 may be turned on so that the power supply voltages VS1 and VS2 are supplied to each of the boosters 4121 and 4122. However, the combination of the power supply voltages supplied to the boosters 4121 and 4122 in the normal mode may be changed or modified in various ways, and exemplary embodiments of the inventive concept may not be limited to this.

Meanwhile, in the normal mode, the display panel 1300 (refer to FIG. 1) can be driven by the output voltages VO1 and VO2 and the external voltage Vext generated by the power management integrated circuit 1200 (refer to FIG. 1). For example, each of the output voltages VO1 and VO2 and the external voltage Vext may be a negative voltage. In this case, the absolute value of the first output voltage VO1 can be the maximum, and the absolute value of the external voltage Vext can be The smallest.

In the normal mode, each of the first regulator 4131 and the second regulator 4132 can be driven by the first power supply voltage VS1 and the first boosted voltage VB1. Therefore, the first boosted voltage VB1 and the second boosted voltage VB2 can be generated by the boosters 4121 and 4122, respectively. However, the pressure drop generated by the second regulator 4132 may be greater than the pressure drop generated by the first regulator 4131. For example, the absolute value of the first output voltage VO1 may be greater than the absolute value of the second output voltage VO2. The third regulator 4133 may not operate in the normal mode. Instead, the external voltage Vext generated by the power management integrated circuit 1200 (refer to FIG. 1) can be used to drive the display panel 1300.

In the low power mode, the first switch circuit 4110 can be controlled so that at least one of the power supply voltages VS1 to VS3 is supplied to the boosters 4121 and 4122. For example, the voltages respectively supplied to the first booster 4121 and the second booster 4122 may be different from each other. For example, the switch SW1 can be turned on to enable the first power supply voltage VS1 to be supplied to the first booster 4121, and the switches SW5 and SW6 can be turned on to enable the second power supply voltage VS2 and the third power supply voltage VS3 It is supplied to the second booster 4122.

However, this switching operation is only an example. For example, the power supply voltages to be supplied to the boosters 4121 and 4122 can be combined in various ways so that the absolute value of the first boosted voltage VB1 boosted by the first booster 4121 is greater than the borrowed value. The absolute value of the second boosted voltage VB2 boosted by the second booster 4122.

In the low power mode, the display panel 1300 can be controlled by the third regulator 4133 The generated third output voltage VO3 is not driven by the external voltage Vext generated by the power management integrated circuit 1200 (refer to FIG. 1). Since the third output voltage VO3 is generated based on the second boosted voltage VB2 having an absolute value smaller than the absolute value of the first boosted voltage VB1, it is possible to prevent or reduce undesired boosting or excessive boosting. Therefore, since the power consumption of the third regulator 4133 is reduced, the concept of the present invention can reduce the power consumption of the display driver integrated circuit 4100.

FIG. 12 is a block diagram illustrating the integrated circuit of the display driver shown in FIG. 1 according to an exemplary embodiment of the inventive concept. The display driver integrated circuit 5100 may include a first switch circuit 5110, a first booster 5121, a second booster 5122, a first regulator 5131, a second regulator 5132, a third regulator 5133, and a second switch circuit 5140, and controller 5150. According to an exemplary embodiment of the inventive concept, except that the display driver integrated circuit 5100 receives a plurality of power supply voltages VS1 to VSn and except for the configuration and arrangement of the second switch circuit 5140, the display driver integrated circuit 5100 is similar to that shown in FIG. 11示实施例。 Example. Therefore, the same description will not be repeated here.

Different from the above-mentioned exemplary embodiment, the embodiment shown in FIG. 12 may be implemented such that a plurality of power supply voltages VS1 to VSn are supplied to the display driver integrated circuit 5100. The plurality of power supply voltages VS1 to VSn can be generated by a power management integrated circuit 1200 (refer to FIG. 1). The exemplary embodiment assumes |VS1|>|VS2|>...>|VSn|, but the concept of the present invention is not limited to this.

The second switch circuit 5140 may be configured to use the boosted voltages VB1 and VB2 to provide various boosted voltages to the regulators 5131 to 5133 based on various operating modes. The second switch circuit 5140 may include a plurality of switches for switching the boosted voltages VB1 and VB2 Provided to each regulator, and for example, the switch may be formed by a transistor. The operation of the second switch circuit 5140 in various operation modes will be described more fully with reference to FIGS. 13A to 13D.

13A to 13D are block diagrams illustrating the operation of the display driver integrated circuit 5100 in various operation modes. To simplify the description, only the second switch circuit 5140, regulators 5131, 5132, and 5133, and power management integrated circuit 5200 are shown in the figure, but the first power supply is supplied to regulators 5131, 5132, and 5133 The voltage VS1 is not shown. As described above, the levels of the boosted voltage VB1, the output voltages VO1 and VO2, and the external voltage Vext may all be negative, and the exemplary embodiment assumes that their absolute values have the following relationship: |VB1|>|VB2| and|VO1 ｜>｜VO2｜>｜VO3｜, and｜VO1｜>｜VO2｜>｜Vext｜. To help understanding, it will be explained with reference to FIG. 9A and FIG. 9B.

Referring to FIG. 13A, in the normal mode, by the switching operation of the second switch circuit 5140a, the first boosted voltage VB1 generated by the first booster 5121 and the first boosted voltage VB1 generated by the second booster 5122 can be combined. The voltage VB1 is supplied to the first regulator 5131a and the second regulator 5132a. Since the absolute value of the second output voltage VO2 is smaller than the absolute value of the first output voltage VO1, the voltage drop in the second regulator 5132a may be greater than the voltage drop in the first regulator 5131a.

The third regulator 5133a may not operate in the normal mode. Instead, the external power management integrated circuit 5200a of the display driver integrated circuit 5100 can generate a voltage Vext sufficient to drive the display panel 1300. The power management integrated circuit can be executed by the controller 5150 or by an external timing controller (not shown in the figure) The operation of the 5200a to generate the external voltage Vext.

Referring to FIG. 13B, in another normal mode, by the switching operation of the second switch circuit 5140b, the first boosted voltage VB1 generated by the first booster 5121 and the second boosted voltage VB1 generated by the second booster 5122 can be combined. The boosted voltage VB2 is supplied to the first regulator 5131b and the second regulator 5132b, respectively. Since the absolute value of the second boost voltage VB2 is smaller than the absolute value of the first boost voltage VB1, the difference between the voltage drop in the first regulator 5131b and the voltage drop in the second regulator 5132b may be smaller than that of FIG. 13A The difference of the embodiment shown.

Similarly, the third regulator 5133b may not operate in the normal mode. Instead, the external power management integrated circuit 5200b of the display driver integrated circuit 5100 can generate a voltage Vext sufficient to drive the display panel 1300.

Referring to FIG. 13C, in the low power mode, by the switching operation of the second switching circuit 5140c, the first boosted voltage VB1 generated by the first booster 5121 can be supplied to the first regulator 5131c and the second regulator 5132c , And can supply the second boosted voltage VB2 generated by the second booster 5122 to the third regulator 5133c. Since the third regulator 5133c is driven by the second boosted voltage VB2 with a relatively small absolute value, it can prevent or reduce excessive boosting or undesired boosting. In addition, since the excessive voltage drop in the third regulator 5133c can be prevented or reduced, the performance of the display driver integrated circuit 5100 can be improved.

In the low power mode, the controller 5150 or an external timing controller (not shown in the figure) can control the power management integrated circuit 5200c so that the power management integrated circuit 5200c does not generate the external voltage Vext.

Referring to FIG. 13D, in another low power mode, the first boosted voltage VB1 generated by the first booster 5121 can be supplied to the first regulator 5131d by the switching operation of the second switch circuit 5140d. In addition, the second boosted voltage VB2 generated by the second booster 5122 may be supplied to the second regulator 5132d and the third regulator 5133d. Similarly, the power management integrated circuit 5200d can be controlled to not generate the external voltage Vext.

In the exemplary embodiment described with reference to FIGS. 13A to 13D, the first boosted voltage VB1 supplied to the second switch circuits 5140a, 5140b, 5140c, and 5140d may be different from each other and be supplied to the second switch circuit 5140a , 5140b, 5140c, and 5140d can also have different second boost voltages VB2. For example, the boosted voltages VB1 and VB2 may be voltages that are boosted based on the power supply voltages appropriately selected from the plurality of power supply voltages VS1 to VSn to generate the output voltages VO1, VO2, and VO3 of the target level. .

The switching operation of the second switching circuit 5140 has been explained above. Although the detailed configuration of the second switching circuit is not explicitly shown, an appropriate element (for example, a transistor) that supplies the boosted voltage to the regulator may be used. Although it is explained that the boosted voltages VB1 and VB2 are distributed to three regulators, the technical features of the concept of the present invention can be equally applied to the situation where four or more regulators are used.

Fig. 14 is a block diagram for explaining the operation of the controller shown in Fig. 12. For a better understanding, the description will be made with reference to FIG. 12 and FIG. 14.

Basically, the controller 5150 can control the display driver integrated circuit 5100 based on a preset or desired setting value. Therefore, it can be based on normal mode or various low power Rate mode to preset the power supply voltage to be supplied to the boosters 5121 and 5122 (refer to FIG. 12). For example, each value can be preset to supply the power supply voltages VS1 and VS2 to the first booster 5121 in the normal mode, and supply the power supply voltage VSn to the second booster 5122 in the low power mode. .

However, the default setting can be changed if necessary. For example, when the level of the voltage used to drive the display panel needs to be completely changed due to the very high temperature of the display panel, the preset setting value can be changed. Therefore, the value for changing the preset or desired setting value can be sent to the controller 5150 as feedback. For example, the temperature of the display panel, panel brightness, on pixel ratio (OPR), image pattern to be output on the display panel, and/or other values can be regarded as feedback.

The controller 5150 can change the setting value of the boost voltage of each of the regulators 5131, 5132, and 5133 in response to the feedback signal from the display panel. The controller 5150 may calculate the power supply voltage optimized to generate the newly set boost voltage. Based on the above description, the first switch circuit 5110 can perform a switching operation in response to the first selection signal SEL1 based on the calculation result of the controller 5150, so as to supply an appropriate power supply voltage (for example, selected from the power supply voltages VS1 to VSn). Voltage) is supplied to boosters 5121 and 5122.

For example, the exemplary embodiment assumes that the respective values are set to supply the power supply voltages VS1 and VS2 to each of the boosters 5121 and 5122. If the temperature of the display panel is very high as determined based on the feedback signal from the display panel, the controller 5150 can generate the first selection signal SEL1 for controlling the first switch circuit 5110 to compare the power supply voltage VS1 and VS2 different power supply The voltage is supplied to the boosters 5121 and 5122. To this end, the display panel may include a sensor that measures the temperature of the display panel.

As another alternative or in addition, if the display panel is determined to be very bright based on the feedback signal from the display panel, the controller 5150 may generate a first selection signal SEL1 for controlling the first switch circuit 5110 to combine the power supply voltage with Different power supply voltages of VS1 and VS2 are supplied to boosters 5121 and 5122.

As another example, if it is determined based on the feedback signal from the display panel that the ratio of white pixels to the pixels constituting the display panel (that is, the ratio of turned-on pixels) exceeds the reference value, the controller 5150 may generate control signals for controlling The first selection signal SEL1 of the first switch circuit 5110 is used to supply a power supply voltage different from the power supply voltages VS1 and VS2 to the boosters 5121 and 5122.

As another example, if it is determined that an image is displayed in a region of the display panel based on the feedback signal from the display panel, the controller 5150 may generate the first selection signal SEL1 for controlling the first switch circuit 5110 to compare the Different power supply voltages VS1 and VS2 are supplied to the boosters 5121 and 5122.

15 is a block diagram illustrating the configuration of an electronic device 6000 to which a display driver integrated circuit 6100 is applied according to an exemplary embodiment of the inventive concept. The electronic device 6000 may include a display driver integrated circuit 6100, a power management integrated circuit 6200, a display panel 6300, a gate driver 6400, and a timing controller 6500.

The display driver integrated circuit 6100 can receive the data control signal DCS and the image data D-RGB from the timing controller 6500. The display driver integrated circuit 6100 can convert the image data D-RGB into a data signal and can output the data signal to Data lines DL1 to DLm. The data signal may be an analog voltage corresponding to the gray scale value of the image data D-RGB, respectively.

The display driver integrated circuit 6100 can generate voltages VGH, VGL, VINT, U_ELVDD, and U_ELVSS for driving the display panel 6300. To this end, the display driver integrated circuit 6100 may include multiple boosters and multiple regulators described in this specification. The display driver integrated circuit 6100 may further include a first selection circuit for selecting the power supply voltage to be supplied to the display driver integrated circuit 6100 and a second selection circuit for transmitting the boosted voltage to each regulator.

For example, the voltages VGH, VGL, and VINT can be used to drive the display panel 6300 regardless of the operation mode. In the low power mode, the voltages U_ELVDD and U_ELVSS can be used to drive the display panel 6300. Meanwhile, in the normal mode, the display panel 6300 can be driven by the voltages ELVDD and ELVSS generated by the power management integrated circuit 6200 instead of the voltages U_ELVDD and U_ELVSS.

Meanwhile, in the low power mode, the absolute values of the negative voltages VGL, VINT, and U_ELVSS for driving the display panel 6300 may be different from each other. In an exemplary embodiment, the power supply voltage can be appropriately selected to increase the boosting efficiency of the booster and reduce the power consumption of the regulator when the negative voltages VGL, VINT, and U_ELVSS are generated, and the proper boosting voltage can be Respectively produced by the booster. For example, the voltage VGL may be generated by the first regulator 5131 shown in FIG. 12, the voltage VINT may be generated by the second regulator 5132 shown in FIG. 12, and the voltage U_ELVSS may be generated by the third regulator 5133 shown in FIG.

The power management integrated circuit 6200 can generate various power supply voltages VSs(s Is 2 or an integer greater than 2), the various power supply voltages VSs are used to generate voltages for driving the display panel 6300. For example, the power management integrated circuit 6200 may include a voltage converter (not shown in the figure) that generates a voltage with a level suitable for driving the display driver integrated circuit 6100. As another option, the voltage converter can be arranged as an independent circuit instead of being arranged in the power management integrated circuit 6200. The power management integrated circuit 6200 can generate the voltages ELVDD and ELVSS for driving the display panel 6300 in the normal mode.

The display panel 6300 may be, for example, an organic light emitting diode display panel. However, the exemplary embodiments of the inventive concept may not be limited to this. For example, the display driver integrated circuit 6100 can be applied to various display panels. The pixel structure when the display panel 6300 is an organic light emitting diode display panel will be explained more fully with reference to FIG. 16.

The display panel 6300 may include scan lines SL1 to SLn, emission lines EL1 to ELn, data lines DL1 to DLm, and pixels PX.

Each of the emission lines EL1 to ELn may be arranged in parallel to the corresponding scan line of the scan lines SL1 to SLn. The data lines DL1 to DLm may cross the scan lines SL1 to SLn, and may be separated from the scan lines SL1 to SLn.

Each of the pixels PX may be connected to a corresponding one of the scan lines SL1 to SLn, a corresponding one of the emission lines EL1 to ELn, and a corresponding data line of the data lines DL1 to DLm.

Each pixel PX can receive the first voltage ELVDD and the second voltage ELVSS with a level lower than the first voltage ELVDD in the normal mode. PX per pixel The third voltage U_ELVDD and the fourth voltage U_ELVSS can be received in the low power mode. Each pixel PX can be connected to the power line PL to which the first voltage ELVDD is applied. Each pixel PX can be connected to the initialization line IL for receiving the initialization voltage VINT.

Each pixel PX can be electrically connected to three scan lines. For example, the pixels of the second pixel column can be connected to the first scan line SL1 to the third scan line SL3.

Although not shown in FIG. 15, the display panel 6300 may further include a plurality of dummy scan lines. The display panel 6300 may further include, for example, a dummy scan line connected to the pixel PX of the first pixel row and a dummy scan line connected to the pixel PX of the nth pixel row. In addition, pixels connected to any one of the data lines DL1 to DLm (hereinafter referred to as "pixels of a pixel row") may be connected to each other. Two adjacent pixels among the pixels in the pixel row can be electrically connected to each other.

Each pixel PX may include an organic light-emitting diode (not shown in the figure) and a pixel driver circuit (not shown in the figure) that controls the emission of the organic light-emitting diode. The pixel driver circuit may include multiple thin film transistors and capacitors. At least one of the gate driver 6400 and the display driver integrated circuit 6100 may include a thin film transistor formed by the same process as the pixel driver circuit.

The scanning lines SL1 to SLn, the emission lines EL1 to ELn, the data lines DL1 to DLm, the power line PL, the initialization line IL, the pixel PX, the display driver integrated circuit 6100, and the gate can be implemented by repeatedly performing the photolithography process. The pole driver 6400 is formed on a substrate (not shown in the figure). The insulating layer can be formed on the substrate (not shown in the figure) by repeatedly performing the deposition process and the coating process. Each insulating layer may include covering The film covering the entire display panel 6300 or at least one insulating pattern that only overlaps the specific configuration of the display panel 6300. The insulating layer may include an organic layer and/or an inorganic layer. In addition, a sealing layer (not shown in the figure) for protecting the pixels PX can be formed on the substrate.

The gate driver 6400 can receive the gate control signal GCS from the timing controller 6500. The gate control signal GCS may include a starting vertical signal for starting the operation of the gate driver 6400, a clock signal for determining the output timing of the signal, and the like. The gate driver 6400 can generate a plurality of scan signals, and can sequentially output the scan signals to the scan lines SL1 to SLn. In addition, the gate driver 6400 can generate a plurality of emission control signals in response to the gate control signal GCS, and can output the emission control signals to the emission lines EL1 to ELn.

The timing controller 6500 can receive an input image signal (not shown in the figure), and can generate an image by converting the data format of the input image signal to be suitable for the interface specification with the gate driver 6400 Data D-RGB. The timing controller 6500 can output the image data D-RGB and various control signals DCS and SCS to the display driver integrated circuit 6100 and the gate driver 6400.

In an exemplary embodiment, the scan signal and the control signal are shown as output from a gate driver 6400 in FIG. 15. However, the exemplary embodiments of the inventive concept may not be limited to this. According to an exemplary embodiment, a plurality of scan driver circuits may divide and output the scan signal, and may divide and output the emission control signal. As another option, according to an exemplary embodiment, a scan signal is generated and output The driver circuit and the driver circuit that generates and outputs the emission control signal can be separated from each other. Alternatively, according to an exemplary embodiment, the gate driver 6400 may be integrated in the display driver integrated circuit 6100 to form one chip.

Fig. 16 is an equivalent circuit diagram of the pixel shown in Fig. 15. 16 illustrates an equivalent circuit diagram corresponding to the i-th pixel PXi connected to the k-th data line DLk among the data lines DL1 to DLm.

The i-th pixel PXi may include an organic light emitting diode OLED and a pixel driver circuit for controlling the organic light emitting diode OLED. The first electrode of the organic light emitting diode OLED may be connected to the second node N2. The second electrode of the organic light emitting diode OLED may be connected to the second voltage ELVSS in the normal mode and to the fourth voltage U_ELVSS in the low power mode. The pixel driver circuit may include six thin film transistors TR1 to TR6 and one capacitor CST. The pixel driver circuit shown in FIG. 16 is only an example, and the exemplary embodiment of the inventive concept may not be limited to this.

The pixel driver circuit may include a driving transistor and a control transistor.

The driving transistor can adjust the driving current flowing to the organic light emitting diode OLED. For example, the driving transistor may be the first transistor TR1. The output electrode of the first transistor TR1 can be electrically connected with the organic light emitting diode OLED. The output electrode of the first transistor TR1 may be directly connected to the anode of the organic light emitting diode OLED, or may be connected to the anode of the organic light emitting diode OLED via another transistor.

The control gate of the control transistor can receive the control signal. The control signal to be applied to the i-th pixel PXi may include the i-th scan signal Si, the data signal Dk, the (i-1)th emission control signal Ei-1, and the i-th emission control signal Ei.

For example, the control transistors may include second to sixth transistors TR2 to TR6. The explanation will be made under the condition that the control transistor includes five thin film transistors. However, the exemplary embodiments of the inventive concept may not be limited to this. For example, the control transistors can be implemented with thin film transistors with a number less than 5 or greater than 5.

The node between the output electrode of the second transistor TR2 and the input electrode of the first transistor TR1 is defined as the first node N1, and the node between the output electrode of the fifth transistor TR5 and the output electrode of the first transistor TR1 The node is defined as the second node N2.

The first transistor TR1 may receive the first voltage ELVDD or the third voltage U_ELVDD via the third transistor TR3. The first transistor TR1 may have an input electrode connected to the first node N1, a control electrode connected to one electrode of the capacitor CST, and an output electrode connected to the organic light emitting diode OLED via the second node N2.

The second transistor TR2 may have a control electrode connected to the i-th scan line SLi, an input electrode, and an output electrode connected to the first node N1. The input electrode of the second transistor TR2 may be connected to the control electrode of the first transistor TR1 and the one electrode of the capacitor CST.

The third transistor TR3 may have a control electrode connected to the i-th emission control line ELi, an input electrode connected to the power line PL, and an output electrode connected to the first node N1. The third transistor TR3 can be turned on in response to the i-th transmission control signal Ei.

The fourth transistor TR4 may have a control electrode connected to the i-th scan line SLi, an input electrode connected to the k-th data line DLk, and an output electrode. Fourth Electric The output electrode of the crystal TR4 can be connected to the other electrode of the capacitor CST and the fifth transistor TR5. When the fourth transistor TR4 is turned on by the i-th scan signal Si, the fourth transistor TR4 can provide the data signal received through its input electrode to the capacitor CST.

The fifth transistor TR5 may have a control electrode connected to the (i-1)th emission control line ELi-1, an input electrode, and an output electrode connected to the second node N2. The input electrode of the fifth transistor TR5 can be connected to the other electrode of the capacitor CST and the fourth transistor TR4. The fifth transistor TR5 can be turned on in response to the (i-1)th transmitting control signal Ei-1.

The sixth transistor TR6 may have a control electrode connected to the i-th scan line SLi, an input electrode connected to the initialization line IL, and an output electrode connected to the organic light emitting diode OLED. When the sixth transistor TR6 is turned on by the i-th scan signal Si, the sixth transistor TR6 can provide the initialization voltage VINT to the second node N2.

Each of the first to sixth transistors TR1 to TR6 may be a P-type transistor or an N-type transistor. The organic light emitting diode display device may not be limited to any one embodiment, but may include various types of transistors.

According to an exemplary embodiment of the inventive concept, the display driver integrated circuit can generate boosted voltages of different levels based on the operation mode, thereby preventing unnecessary boosting or excessive boosting.

In addition, the display driver integrated circuit can adjust the voltage based on the appropriately boosted voltage, thereby reducing the power loss caused by the regulator.

Although the inventive concept has been explained with reference to exemplary exemplary embodiments, However, it will be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the concept of the present invention. Therefore, it should be understood that the above exemplary embodiments are not restrictive, but illustrative.

1100: Display driver integrated circuit

1110: switch circuit

1121: The first booster (booster)

1122: Second booster (booster)

1131: The first regulator (regulator)

1132: second regulator (regulator)

CTRL1, CTRL2: control signal

SEL: select signal

VB1: First boost voltage (first boost voltage, voltage)

VB2: second boost voltage (second boost voltage, voltage)

VO1: First output voltage (first output voltage)

VO2: second output voltage (second output voltage)

VS1: first power supply voltage (first power supply voltage)

VS2: second power supply voltage (second power supply voltage)

Claims (20)

A display driver integrated circuit is configured to operate according to different operation modes among a plurality of operation modes. The display driver integrated circuit includes: a first booster, which is configured to operate according to different operation modes regardless of the operation mode. At least one of the first power supply voltage and the second power supply voltage is boosted to generate a first boosted voltage; At least one of the power supply voltage and the second power supply voltage is boosted to generate the first boosted voltage or the second boosted voltage; a first regulator is configured to be based on The first boosted voltage generated by at least one of the booster and the second booster to generate a first output voltage; and a second regulator configured to be based on the second boosted voltage And the second output voltage is generated. The display driver integrated circuit according to the first item of the scope of patent application further includes: a first switch circuit configured to provide at least one of the first power supply voltage and the second power supply voltage To the first booster and provide at least one of the first power supply voltage and the second power supply voltage to the second booster. The display driver integrated circuit described in claim 1, wherein in the normal mode, the first power supply supplied to the first booster At least one of the voltage and the second power supply voltage is the same as at least one of the first power supply voltage and the second power supply voltage provided to the second booster. The display driver integrated circuit described in the scope of patent application 1, wherein in the low power mode, the first power supply voltage and the second power supply voltage of the first booster are provided At least one of is different from at least one of the first power supply voltage and the second power supply voltage provided to the second booster. The display driver integrated circuit described in the scope of patent application 1, wherein in the normal mode, the first regulator is configured to be generated by the first booster and the second booster At least one of the first boosted voltage is driven by the first power supply voltage, and the second regulator is configured not to operate. The display driver integrated circuit described in the scope of patent application 1, wherein in the low power mode, the first regulator is configured to be the first boosted voltage generated by the first booster And the first power supply voltage, and the second regulator is configured to be driven by the second boost voltage and the first power supply voltage. The display driver integrated circuit according to the first item of the scope of patent application, wherein at least one of the first booster and the second booster includes a charge pump or a switch mode power supply (SMPS) ). The display driver integrated circuit according to the first item of the patent application, wherein at least one of the first boosted voltage and the second boosted voltage is negative Voltage, and the absolute value of the first boosted voltage is greater than the absolute value of the second boosted voltage. The display driver integrated circuit according to item 8 of the scope of patent application, wherein at least one of the first output voltage and the second output voltage is a negative voltage, and the absolute value of the first output voltage Greater than the absolute value of the second output voltage. The display driver integrated circuit described in the first item of the scope of patent application further includes: a second switch circuit configured to operate in a normal mode to transfer the first boosted voltage generated by the first booster And at least one of the first boosted voltage generated by the second booster is provided to the first regulator and the second boosted voltage is provided to the second regulator. A display driver integrated circuit includes: a booster circuit configured to generate a first boosted voltage by boosting at least one of a first power supply voltage and a second power supply voltage, and At least one of the first power supply voltage and the second power supply voltage is boosted to generate the first boosted voltage or the second boosted voltage; and a regulating circuit is configured to be based on the A first boosted voltage generates a first output voltage, and a second output voltage is generated based on the second boosted voltage, wherein at least one of the first boosted voltage and the second boosted voltage Is a negative voltage, and the absolute value of the first boosted voltage is greater than the absolute value of the second boosted voltage. The display driver integrated circuit described in the eleventh item of the scope of patent application further includes: a switch circuit configured to provide at least one of the first power supply voltage and the second power supply voltage to the述Boost circuit. The display driver integrated circuit described in claim 11, wherein at least one of the first output voltage and the second output voltage is a negative voltage, and the absolute value of the first output voltage Greater than the absolute value of the second output voltage. The display driver integrated circuit described in claim 11, wherein the booster circuit is configured to not generate the second boosted voltage in the normal mode. The display driver integrated circuit according to the 14th patent application, wherein the adjustment circuit is configured to not generate the second output voltage in the normal mode. An electronic device includes: a display panel configured to display images; a power management integrated circuit configured to generate an external voltage; and a display driver integrated circuit configured to generate boosted voltages of different levels and configured to At least one of the two modes is selected. In the first mode, the display driver integrated circuit is configured to provide a first output voltage based on at least one of the boosted voltages to the display Panel, and the power management integrated circuit is configured to transfer the external voltage Provided to the display panel, the absolute value of the external voltage is less than the absolute value of the first output voltage, and in the second mode, the display driver is configured to be based on at least one of the boosted voltages One of the first output voltage and the second output voltage is provided to the display panel, and the absolute value of the second output voltage is smaller than the absolute value of the external voltage. The electronic device according to claim 16, wherein the display driver integrated circuit is configured to perform in the first mode if the area of the image displayed on the display panel is a first area And the display driver integrated circuit is configured to operate in the second mode if the area of the image displayed on the display panel is a second area, the second area being smaller than the first area One area. The electronic device according to claim 16, wherein the display driver integrated circuit is configured to use the first mode if the brightness of the image displayed on the display panel is the first brightness And the display driver integrated circuit is configured to operate in the second mode if the brightness of the image displayed on the display panel is a second brightness, the second brightness being higher than the first brightness One brightness is dark. The electronic device described in claim 16, wherein the display driver integrated circuit is configured such that if the on-pixel ratio of the image displayed on the display panel is the first ratio, the The first mode operates, and the display driver integrated circuit is configured to display on the display panel If the ON-pixel ratio of the image is a second ratio, it operates in the second mode, and the second ratio is lower than the first ratio. The electronic device according to claim 16, wherein the display driver integrated circuit is configured to operate in the first mode if the temperature of the display panel is the first temperature, and the display driver The integrated circuit is configured to operate in the second mode if the temperature of the display panel is a second temperature, and the second temperature is higher than the first temperature.

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