TWI735338B - Pixel driving circuit - Google Patents

Abstract

A pixel driving circuit includes a light emitting diode, a first transistor, a second transistor, a first capacitor, a second capacitor, a third capacitor, a fourth transistor, a fifth transistor and a photo-sensitive switch. In a compensation period, the second transistor provides a first driving current to the light emitting diode, thus the light emitting diode illuminates the photo-sensitive switch, and the photo-sensitive switch is configured to generate a photo current corresponding to the illumination of the light emitting diode. And then, a voltage level of a gate terminal of the second transistor is adjusted by the photo current so as to adjust a second driving current provided to the light emitting diode by the second transistor in later emission period.

Description

Pixel drive circuit

This case is about a pixel drive circuit, especially a voltage compensated pixel drive circuit.

In display panels, it is often due to variations in the electrical or optical properties of light-emitting diode components, electrical variations in thin-film transistors, circuit voltage degradation (IR-drop), defects generated by the transistor during transfer, and pixel parasitics. The influence of capacitance or other parasitic elements causes uneven brightness of the display screen. In view of this, how to provide a display pixel surface with uniform brightness is a problem to be solved in the industry.

This disclosure provides a pixel driving circuit. The pixel driving circuit includes a light-emitting diode, a first transistor, a second transistor, a first capacitor, a second capacitor, a third transistor, a fourth transistor, and a fifth transistor And a photosensitive switch. The second transistor is used for supplying power to make the light emitting diode emit light, wherein the first transistor, the second transistor and the light emitting diode are electrically connected in series and electrically coupled to a first system voltage terminal and Between a second system voltage terminal; a first capacitor, the first terminal of which is electrically coupled to the gate terminal of the second transistor; a second capacitor, the first terminal of which is electrically coupled to the second capacitor of the first capacitor Terminal, the second terminal of which is electrically coupled to the second system voltage terminal; the third transistor, the first terminal of which is used for receiving a data signal, and the second terminal of which is electrically coupled to the second terminal of the first capacitor; The fourth transistor, the first terminal of which is electrically coupled to a reference voltage terminal, and the second terminal of which is electrically coupled to the gate terminal of the second transistor; the fifth transistor, the first terminal of which is electrically coupled to the second transistor The second terminal of the four-transistor is electrically coupled to the reference voltage terminal; the first terminal of the photosensitive switch is electrically coupled to the second terminal of the fifth transistor, and the second terminal is electrically coupled to the The second end of the first capacitor.

This disclosure provides another pixel driving circuit. The pixel driving circuit includes a light emitting diode, a first transistor, a second transistor, a third transistor, a capacitor, a fourth transistor, a fifth transistor, and a photosensitive switch. The first terminal of the light emitting diode is electrically coupled to a first system voltage terminal; the first transistor, the first terminal of which is electrically coupled to the second terminal of the light emitting diode; the second terminal of the second transistor, One end is electrically coupled to the second end of the first transistor, and the second end is electrically coupled to a second system voltage end. The second transistor is used to supply power to the light emitting diode; the third transistor , The first terminal of the capacitor is used to receive a data signal; the first terminal of the capacitor is electrically coupled to the second terminal of the third transistor, and the second terminal of the capacitor is electrically coupled to the gate terminal of the second transistor; Four transistors, the first terminal of which is electrically coupled to the second terminal of the capacitor. The fifth transistor and the photosensitive switch are connected in series, and one of the fifth transistor and the photosensitive switch is electrically coupled to the first end of the capacitor.

In summary, the pixel driving circuit of the present disclosure senses the light-emitting brightness of the light-emitting diode through a photosensitive switch to adjust the size of the driving current provided to the light-emitting diode during the light-emitting period, so as to improve the display screen. The brightness is uneven.

The following examples are given in conjunction with the accompanying drawings for detailed description, but the examples provided are not intended to limit the scope of the disclosure, and the description of the structure and operation is not intended to limit the execution order, any recombination of components The structures and the devices with equal effects are all within the scope of this disclosure. In addition, the illustrations are for illustrative purposes only, and are not drawn according to the original dimensions. To facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The terms (terms) used in the entire specification and the scope of the patent application, unless otherwise specified, usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content.

In addition, the terms "include", "include", "have", "contain", etc. used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one or more of the related listed items and all combinations thereof.

In this text, when an element is referred to as "coupling" or "coupling", it can be referred to as "electrical coupling" or "electrical coupling". "Coupling" or "coupling" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

Please refer to FIG. 1. FIG. 1 is a circuit structure diagram of the pixel driving circuit 100 according to an embodiment of the disclosure. As shown in Figure 1, the pixel driving circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a photosensitive switch S1, and a first capacitor. C1, the second capacitor C2 and the light emitting diode L1.

In the embodiment of the present disclosure, the photosensitive switch S1 is a transistor as an example. However, the photosensitive switch S1 can also be selected from photodiodes, thin film transistors or other light sensing elements. Therefore, this disclosure is not limited to this.

In some embodiments, the transistors T1 to T5 are selected from thin film transistors with high sensitivity to light, and a black matrix can be used to cover the first transistor T1, the second transistor T2, and the third transistor T3. , The fourth transistor T4 and the fifth transistor T5, to shield the light emitting diode L1 may irradiate the light of the transistors T1~T5, and prevent the transistors T1~T5 from generating current in response to the light exposure to cause the pixel driving circuit 100 The potential is floating. In other embodiments, the transistors T1 to T5 are not highly sensitive to light, so there is no need to cover the transistors with a light-shielding layer. Therefore, this disclosure is not limited to this.

Structurally, the first transistor T1, the second transistor T2, and the light emitting diode L1 are electrically connected in series and electrically coupled between the first system voltage terminal VDD and the second system voltage terminal VSS. The first capacitor C1 and the second capacitor C2 are connected in series and electrically coupled between the node N1 and the second system voltage terminal VSS, wherein the node N1 is the connection point between the gate terminal of the second transistor T2 and the first capacitor C1. The fourth transistor T4 is electrically coupled between the reference voltage terminal and the node N1. The fifth transistor T5 and the photosensitive switch S1 are connected in series and electrically coupled between the node N1 and the node N2, where the node N2 is the junction of the first capacitor C1 and the second capacitor C2. The third transistor T3 is electrically coupled to the node N2. Wherein, the second transistor T2 is used to provide a driving current to the light emitting diode L1.

It is worth noting that, in this embodiment, the second transistor T2 provides different driving currents to the light emitting diode L1 during different operation periods. In the embodiment of this case, the second transistor T2 provides the first driving current Id1 and the second driving current Id2 to the light emitting diode L1 during the compensation period and the light emitting period, respectively. During the compensation period, the first driving current Id1 is used to make the light-emitting diode L1 emit light to illuminate the photosensitive switch S1, and the photocurrent generated by the photosensitive switch S1 in response to the illumination of the light-emitting diode L1 is used to adjust the gate terminal of the second transistor T2 The second transistor T2 can provide the adjusted second driving current Id2 to the light-emitting diode L1 during the subsequent light-emitting period. In order to better understand how the photocurrent generated by the photosensitive switch S1 according to the first driving current Id1 during the compensation phase adjusts the second driving current Id2 provided to the light-emitting diode L1 during the light-emitting phase, a subsequent embodiment will be described.

The aforementioned transistors respectively have a first terminal, a second terminal, and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the aforementioned capacitors also have a first end and a second end, respectively.

In detail, the first terminal of the first transistor T1 is electrically coupled to the first system voltage terminal VDD, the second terminal of the first transistor T1 is electrically coupled to the first terminal of the second transistor T2, and the first terminal The gate terminal of the crystal T1 is used for receiving the first control signal EM. The second terminal of the second transistor T2 is electrically coupled to the first terminal of the light emitting diode L1, and the gate terminal of the second transistor T2 is electrically coupled to the first terminal of the first capacitor C1 and the first terminal of the fourth transistor T4. The second end and the first end of the fifth transistor T5. The second terminal of the light emitting diode L1 is electrically coupled to the second system voltage terminal Vss.

The second terminal of the first capacitor C1 is electrically coupled to the first terminal of the second capacitor C2, the second terminal of the third transistor T3, the second terminal of the photosensitive switch S1, and the gate terminal of the photosensitive switch S1. The second terminal of the second capacitor C2 is electrically coupled to the second terminal of the light emitting diode L1 and the second system voltage terminal VSS.

The first terminal of the fourth transistor T4 is electrically coupled to the reference voltage terminal VREF, and the gate terminal of the fourth transistor T4 is used for receiving the third control signal RT. The gate terminal of the fifth transistor T5 is electrically coupled to the reference voltage terminal VREF, and the second terminal of the fifth transistor T5 is electrically coupled to the first terminal of the photosensitive switch S1. The gate terminal of the third transistor T3 is used for receiving the second control signal SN, and the first terminal of the third transistor T3 is used for receiving the data signal VDATA.

FIG. 2 is a timing diagram of control signals and data signals of the pixel driving circuit 100 in FIG. 1 according to an embodiment. As shown in FIG. 2, one display period in the control timing of the pixel driving circuit 100 can be divided into four periods, which are a reset period P1, a compensation period P2, a writing period P3, and a light emitting period P4. It should be particularly noted that the time lengths of these periods in Figure 2 are only for example, and are not used to limit the disclosure.

In detail, the first control signal EM has a first logic level V1 (for example, a low logic level) during the reset period P1 and the writing period P3; the first control signal EM has a first logic level V1 (for example, a low logic level) during the compensation period P2 and the light emitting period P4 Two logic levels V2 (for example: high logic level). The second control signal SN has a second logic level V2 during the reset period P1 and the compensation period P2; the second control signal SN switches from the first logic level V1 to the second logic level V2 during the writing period P3, and then The second logic level V2 is switched to the first logic level V1; the second control signal SN has the first logic level V1 during the light-emitting period P4.

The third control signal RT switches from the first logic level V1 to the second logic level V2 during the reset period P1, and then switches from the second logic level V2 to the first logic level V1; the third control signal RT is at The compensation period P2, the writing period P3, and the light-emitting period P4 have the first logic level V1.

Moreover, in the embodiment shown in Figure 1, the voltage level of the reference voltage terminal VREF during the reset period P1 and the compensation period P2 is equal to the voltage VH; the reference voltage terminal VREF has the voltage level during the writing period P3 and the light-emitting period P4 The voltage level is equal to the voltage VL, and the voltage VH has a higher voltage level than the voltage VL. For example, when the voltage VH is 3 volts, the voltage VL is 1 volt; or when the voltage VH is 5 volts, the voltage VL is 2 volts. The voltage level of the data signal VDATA during the reset period P1 and the compensation period P2 is equal to the voltage V0; the voltage level of the data signal VDATA during the writing period P3 and the light-emitting period P4 is equal to the voltage Vdi.

In order to make the overall operation of the pixel driving circuit 100 clearer and easier to understand, please refer to the first to 3D diagrams below. FIG. 3A is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the reset period P1. FIG. 3B is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the compensation period P2. FIG. 3C is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 in the writing period P3. FIG. 3D is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the light-emitting period P4.

During the reset period P1, since the second control signal SN and the third control signal RT have high logic levels, the third transistor T3 and the fourth transistor T4 are turned on. On the other hand, since the first control signal EM has a low logic level, the first transistor T1 is turned off. In addition, the voltage level of the reference voltage terminal VREF is the voltage VH, so the fifth transistor T5 will be turned on. At this time, the voltage level of the data signal VDATA is the voltage V0.

In detail, during the reset period P1, the voltage VH will be transmitted to the first terminal (node N1) of the first capacitor C1 through the fourth transistor T4, so that the voltage level at the node N1 is substantially equal to the voltage VH. At the same time, the voltage V0 of the data signal VDATA will be transmitted to the second end (node N2) of the first capacitor C1 through the third transistor T3, so that the voltage level of the node N2 is substantially equal to the voltage V0. In this way, the pixel driving circuit 100 completes the reset operation.

Then, during the compensation period P2, since the first control signal EM and the second control signal SN have high logic levels, and the voltage level of the gate terminal of the second transistor T2 is still the voltage VH. Therefore, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on. On the other hand, since the third control signal RT has a low logic level, the fourth transistor T4 is turned off. In addition, the voltage level of the reference voltage terminal VREF is the voltage VH, so the fifth transistor T5 will be turned on. At this time, the voltage level of the data signal VDATA is the voltage V0.

At the beginning of the compensation period P2, the voltage across the gate terminal and the source terminal of the second transistor T2 (Vgs) is (VH-Vss). Moreover, since the first transistor T1 is turned on, the second transistor T2 can provide the first driving current Id1 to the light emitting diode L1 according to the voltage across the gate terminal and the source terminal (Vgs).

Generally speaking, the drive current provided by the N-type transistor complies with the following formula: Id=k(Vgs-Vth) ² . Among them, k is a constant related to the element characteristics of the second transistor T2, and Vth is the threshold voltage of the second transistor T2.

Substituting the cross voltage (Vgs) between the gate terminal and the source terminal of the second transistor T2 into the formula of the aforementioned driving current, at the beginning of the compensation period P2, the first driving current Id1=k((VH – Vss)- Vth) ² . At the beginning of the compensation period P2, the pixel driving circuit 100 will give a fixed input voltage (for example, the data voltage Vdata is fixed to V0) and set the gate terminal and source terminal of the second transistor T2. Theoretically, the brightness of the light-emitting diode L1 It should be consistent. In actual applications, the variation in the LED L1 manufacturing process will cause the actual display brightness to be inconsistent with the expected brightness, or the threshold voltage Vth drift caused by the aging of the second transistor T2, or even worse. It is the voltage degradation in the circuit that prevents the pixel driving circuit 100 from operating at the expected voltage level. Therefore, the brightness of the light emitting diode L1 may be different even under the same voltage setting.

It is worth noting that, in the embodiment of the present disclosure, during the compensation period P2, the second transistor T2 provides the first driving current Id1 to the light emitting diode L1, so that the light emitting diode L1 depends on the first driving current Id. Amplitude luminescence is used to illuminate the photosensitive switch S1. The photosensitive switch S1 is used to generate a photocurrent corresponding to the illumination of the light-emitting diode L1, and the voltage level of the gate terminal of the second transistor T2 is adjusted by the photocurrent to adjust the first The second transistor T2 provides the second driving current Id2 of the light-emitting diode L1 during the subsequent light-emitting period P4 to compensate for the electrical and optical property variation caused by the aforementioned problems.

In detail, during the compensation period P2, the photosensitive switch S1 generates a photocurrent corresponding to the brightness of the light emitting diode L1, and the photocurrent turns on the photosensitive switch S1, so that the voltage V0 of the data signal VDATA passes through the fifth transistor T5 and the photosensitive switch S1 and the third transistor T3 pull down the voltage VH of the gate terminal (node N1) of the second transistor T2 until the photosensitive switch S1 is turned off. At this time, the voltage level of the node N1 will decrease by the voltage ΔV. That is, the voltage level of the gate terminal (node N1) of the second transistor T2 is substantially equal to (VH-ΔV).

When the compensation period P2 is completed, the voltage ΔV reduced by the voltage level of the node N1 will be positively correlated with the magnitude of the photocurrent, and the photocurrent will be positively correlated with the brightness of the light-emitting diode L1. That is, when the light-emitting diode L1 is brighter, the photocurrent generated by the photosensitive switch S1 is larger, and the value of the voltage ΔV reduced by the voltage level of the node N1 is greater; when the light-emitting diode L1 is darker, the photosensitive switch S1 The photocurrent generated by S1 is small, and the value of the voltage ΔV reduced by the voltage level of the node N1 is small.

Then, in the writing period P3, since the second control signal SN has a high logic level, the third transistor T3 is turned on. On the other hand, since the first control signal EM and the third control signal RT have low logic levels, the first transistor T1 and the fourth transistor T4 are turned off. In addition, the voltage level of the reference voltage terminal VREF is the voltage VL, so the fifth transistor T5 is turned off. In addition, the voltage level of the reference voltage terminal VREF is the voltage VL, so the fifth transistor T5 is turned off. At this time, the voltage level of the data signal VDATA increases from the voltage V0 in the previous period (compensation period P2) to the voltage Vdi. In addition, the voltage level of the second system voltage terminal VSS is the voltage Vss.

In detail, since the third transistor T3 is turned on during the compensation period P2 and the writing period P3, the voltage (Vdi-V0) of the data signal VDATA increased from the compensation period P2 to the writing period P3 can be transmitted through the third transistor T3 To the node N2, and coupled to the gate terminal (node N1) of the second transistor T2 through the first capacitor C1 through capacitive coupling, the voltage level of the node N1 is increased by the voltage (Vdi-V0). That is, the voltage level of the gate terminal (node N1) of the second transistor T2 is substantially equal to (VH-V+(Vdi-V0)). In addition, the voltage level of the source terminal of the second transistor T2 (the second terminal of the second transistor T2) is substantially equal to (Vss+Vled), where the voltage Vled is the turn-on voltage of the light-emitting diode L1. At this time, the cross voltage (Vgs) between the gate terminal and the source terminal of the second transistor T2 is (VH-V+(Vdi-V0)-Vled-Vss).

Then, during the light-emitting period P4, since the first control signal EM has a high logic level, the first transistor T1 is turned on. On the other hand, since the second control signal SN and the third control signal RT have low logic levels, the third transistor T3 and the fourth transistor T4 are turned off. In addition, the voltage level of the reference voltage terminal VREF is the voltage VL, so the fifth transistor T5 is turned off.

In detail, since the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off, the voltage across the gate terminal and the source terminal (Vgs) of the second transistor T2 is still (VH-ΔV+(Vdi -V0)- Vled-Vss). Moreover, since the first transistor T1 is turned on, the second transistor T2 can provide the second driving current Id2 to the light emitting diode L1 according to the voltage across the gate terminal and the source terminal (Vgs).

Substituting the cross voltage (Vgs) between the gate terminal and the source terminal of the second transistor T2 into the formula of the aforementioned driving current, the second driving current Id2=k(VH-ΔV+(Vdi-V0)-Vss-Vled-Vth) ² .

In the display panel, whether it is the optical and electrical variation of the components (for example, in a display panel, the luminous efficiency or forward voltage of different light-emitting diodes may have some differences, the mobility of different transistors, The threshold voltage and leakage current may also have some differences) or the voltage drop of the circuit will cause the brightness of the light-emitting diodes in the display panel to be inconsistent (for example, in the display panel, some light-emitting diodes are brighter, and some The light-emitting diode is darker), resulting in uneven brightness of the display screen.

Therefore, in the embodiment of the present disclosure, the voltage ΔV caused by the photocurrent corresponding to the brightness of the light emitting diode L1 generated by the photosensitive switch S1 during the compensation period P1 can compensate the effects caused by the aforementioned problems. For example, in a display panel, if some light-emitting diodes L1 have brighter light-emitting brightness during the compensation period P2, the photocurrent generated by the photosensitive switch S1 is larger, resulting in a larger voltage ΔV. The driving current Id2 is small, so that the display brightness of the light-emitting diode L1 during the light-emitting period P4 is relatively dark. If the light-emitting brightness of some light-emitting diodes L1 during the compensation period P2 is dark, the photocurrent generated by the photosensitive switch S1 is small, resulting in a small voltage ΔV, and the second driving current Id2 of P4 during the light-emitting period is large, making the light-emitting diodes The display brightness of the body L1 during the light-emitting period P4 is brighter. In this way, the problem of affecting the brightness of the light-emitting diode L1 in the display panel is covered, so as to adjust the brightness of the light-emitting diode L1 during display. Therefore, the brightness unevenness of the display screen is improved.

FIG. 4 is a circuit structure diagram of the pixel driving circuit 200 according to an embodiment of the disclosure. In the embodiment shown in Figure 4, the pixel driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a photosensitive switch S1. , The first capacitor C1, the second capacitor C2 and the light emitting diode L1.

Compared with the pixel driving circuit 100 in the embodiment of FIG. 1, the pixel driving circuit 200 in the embodiment of FIG. 4 is different in that the first transistor T1, the second transistor T2, and the light emitting diode L1 The coupling relationship. More specifically, in the pixel driving circuit 200 shown in FIG. 4, the first terminal of the light emitting diode L1 is electrically coupled to the first system voltage terminal VDD, and the second terminal of the light emitting diode L1 is electrically connected to the first system voltage terminal VDD. Is coupled to the first terminal of the second transistor T2; the second terminal of the second transistor T2 is electrically coupled to the first terminal of the first transistor T1; the second terminal of the first transistor T1 is electrically coupled to the second terminal System voltage terminal VSS. The other detailed connection relationships and operation modes of the pixel driving circuit 200 are substantially the same as those of the pixel driving circuit 100 in the previous embodiment in FIG. 1, and will not be described here.

In another embodiment of the present disclosure, the effects of the embodiment shown in FIG. 1 can also be achieved, please refer to FIG. 5. FIG. 5 is a circuit structure diagram of the pixel driving circuit 300 according to an embodiment of the disclosure. As shown in Figure 5, the pixel driving circuit 300 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a photosensitive switch S1, and a first capacitor. C1 and light-emitting diode L1.

Structurally, the first transistor T1, the second transistor T2, and the light emitting diode L1 are electrically connected in series and electrically coupled between the first system voltage terminal VDD and the second system voltage terminal VSS. The first capacitor C1, the photosensitive switch S1, and the fifth transistor T5 are electrically connected in series and electrically coupled between the node N1 and the reference voltage terminal VREF. The node N1 is at the junction of the first capacitor C1 and the gate terminal of the second transistor T2. The fourth transistor T4 is electrically coupled between the node N1 and the reference voltage terminal VREF. The third transistor T3 is electrically coupled to the node N2. The node N2 is at the junction of the first capacitor C1 and the photosensitive switch S1. The second transistor T2 is used to provide the driving current for the light emitting diode L1.

It is worth noting that, in this embodiment, the second transistor T2 provides different driving currents to the light emitting diode L1 during different operation periods. In the embodiment of this case, the second transistor T2 provides the first driving current Id1 and the second driving current Id2 to the light emitting diode L1 during the compensation period and the light emitting period, respectively. During the compensation period, the first driving current Id1 is used to make the light-emitting diode L1 emit light to illuminate the photosensitive switch S1, and the photocurrent generated by the photosensitive switch S1 in response to the illumination of the light-emitting diode L1 is used to adjust the gate terminal of the second transistor T2 The second transistor T2 can provide the adjusted second driving current Id2 to the light-emitting diode L1 during the subsequent light-emitting period. In order to better understand how the photocurrent generated by the photosensitive switch S1 according to the first driving current Id1 during the compensation phase adjusts the second driving current Id2 provided to the light-emitting diode L1 during the light-emitting phase, a subsequent embodiment will be described.

The aforementioned transistors respectively have a first terminal, a second terminal, and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the aforementioned capacitors also have a first end and a second end, respectively.

In detail, the first terminal of the light emitting diode L1 is electrically coupled to the first system voltage terminal VDD, and the second terminal of the light emitting diode L1 is electrically coupled to the first terminal of the first transistor T1. The second terminal of the first transistor T1 is electrically coupled to the first terminal of the second transistor T2, and the gate terminal of the first transistor T1 is used for receiving the first control signal EM. The second terminal of the second transistor T2 is electrically coupled to the second system voltage terminal VSS, and the gate terminal of the second transistor T2 is electrically coupled to the first terminal of the fourth transistor T4 and the second terminal of the first capacitor C1 .

The first terminal of the fifth transistor T5 is electrically coupled to the reference voltage terminal VREF, the second terminal of the fifth transistor T5 is electrically coupled to the first terminal of the photosensitive switch S1, and the gate terminal of the fifth transistor T5 is used for receiving The third control signal RT. The second terminal of the photosensitive switch S1 is electrically coupled to its gate terminal, the first terminal of the first capacitor C1 and the second terminal of the third transistor T3. The second terminal of the fourth transistor T4 is electrically coupled to the reference voltage terminal VREF, and the gate terminal of the fourth transistor T4 is used for receiving the third control signal RT. The first terminal of the third transistor T3 is used for receiving the data signal VDATA, and the gate terminal of the third transistor T3 is used for receiving the second control signal SN.

FIG. 6A is a timing diagram of control signals and data signals of the pixel driving circuit 300 in FIG. 5 during the reset period and the compensation period according to an embodiment. FIG. 6B is a timing diagram of control signals and data signals of the pixel driving circuit 300 in FIG. 5 during the writing period and the light emitting period according to an embodiment. As shown in FIG. 6A and FIG. 6B, a display period in the control sequence of the pixel driving circuit 300 can be divided into four periods. The periods are reset period P1, compensation period P2, writing period P3, and light emission. Period P4. It should be particularly noted that the time lengths of these periods in FIG. 6A and FIG. 6B are only for example, and are not used to limit the disclosure.

In detail, the first control signal EM has a first logic level V1 (for example, a low logic level) during the reset period P1 and the writing period P3; the first control signal EM has a first logic level V1 (for example, a low logic level) during the compensation period P2 and the light emitting period P4 Two logic levels V2 (for example: high logic level). The second control signal SN switches from the first logic level V1 to the second logic level V2 during the reset period P1 and the write period P3, and then switches from the second logic level V2 to the first logic level V1; The second control signal SN has the first logic level V1 during the compensation period P2 and the light emitting period P4. The third control signal RT has the second logic level V2 during the reset period P1 and the compensation period P2; the third control signal RT has the first logic level V1 during the writing period P3 and the light emitting period P4.

Moreover, in the embodiment shown in FIG. 5, the voltage level of the reference voltage terminal VREF is equal to the voltage VH. The voltage level of the data signal VDATA during the reset period P1 and the compensation period P2 is equal to the voltage V0, and the voltage level of the data signal VDATA during the writing period P3 and the light emitting period P4 is equal to the voltage Vdi.

In order to make the overall operation of the pixel driving circuit 300 clearer and easier to understand, please refer to Figures 5-7D below. FIG. 7A is a circuit state diagram of the pixel driving circuit 300 in FIG. 5 during the reset period P1. FIG. 7B is a circuit state diagram of the pixel driving circuit 300 in FIG. 5 during the compensation period P2. FIG. 7C is a circuit state diagram of the pixel driving circuit 300 in FIG. 5 during the writing period P3. FIG. 7D is a circuit state diagram of the pixel driving circuit 300 in FIG. 5 during the light-emitting period P4.

During the reset period P1, since the second control signal SN and the third control signal RT have high logic levels, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. On the other hand, since the first control signal EM has a low logic level, the first transistor T1 is turned off. At this time, the voltage level of the data signal VDATA is V0.

In detail, during the reset period P1, the voltage VH of the reference voltage terminal VREF will be transmitted to the second terminal (node N1) of the first capacitor C1 through the fourth transistor T4, so that the voltage level at the node N1 is substantially equal to the voltage VH. At the same time, the voltage V0 of the data signal VDATA will be transmitted to the first end (node N2) of the first capacitor C1 through the third transistor T3, so that the voltage level of the node N2 is substantially equal to the voltage V0. In this way, the pixel driving circuit 300 completes the reset operation.

Then, during the compensation period P2, since the first control signal EM and the third control signal RT have high logic levels, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on. On the other hand, since the second control signal SN has a low logic level, the third transistor T3 will be turned off. At this time, the voltage level of the reference voltage terminal VREF is the voltage VH, and the voltage level of the data signal VDATA is the voltage V0.

The voltage VH of the reference voltage terminal VREF is transmitted to the gate terminal (node N1) of the second transistor T2 via the fourth transistor T4, so that the voltage level of the node N1 is substantially equal to the voltage VH. Since the first voltage level of the node N1 is the voltage VH, the second transistor T2 will be turned on.

At the beginning of the compensation period P2, the voltage across the gate terminal and the source terminal of the second transistor T2 (Vgs) is (VH-Vss). Moreover, since the first transistor T1 is turned on, the second transistor T2 can provide the first driving current Id1 to the light emitting diode L1 according to the voltage across the gate terminal and the source terminal (Vgs).

Generally speaking, the driving current Id provided by the N-type transistor complies with the following formula: Id=k(Vgs-Vth) ² . Among them, k is a constant related to the element characteristics of the second transistor T2, and Vth is the threshold voltage of the second transistor T2.

Substituting the cross voltage (Vgs) of the gate terminal and source terminal of the second transistor T2 into the formula of the driving current, at the beginning of the compensation period P2, the first driving current Id1=k((VH-Vss)- Vth) ² .

During the compensation period P2, the second transistor T2 provides the first driving current Id1 to the light emitting diode L1, so that the light emitting diode L1 illuminates the photosensitive switch S1 according to the amplitude of the first driving current Id, and the photosensitive switch S1 is used to generate the corresponding The photocurrent irradiated by the light-emitting diode T2, and the voltage level of the gate terminal of the second transistor T2 is adjusted by the photocurrent to adjust the second transistor T2 to provide the light-emitting diode during the subsequent light-emitting period P4 The second driving current Id2 of L1 is used to compensate for the variation of the electrical and optical properties of the pixel driving circuit 300 and its components.

In detail, during the compensation period P2, the photosensitive switch S1 generates a photocurrent corresponding to the brightness of the light-emitting diode L1. The photocurrent causes accumulated charges on the first end (node N2) of the first capacitor C1, so that the voltage at the node N2 is The level increases by ΔV. That is, the voltage level of the first terminal (node N2) of the first capacitor C1 is substantially equal to the voltage (V0+ΔV).

When the compensation period P2 is completed, the voltage ΔV increased by the voltage level of the node N1 will be positively correlated with the magnitude of the photocurrent, and the photocurrent will be positively correlated with the brightness of the light-emitting diode L1. That is, when the light-emitting diode L1 is brighter, the photocurrent generated by the photosensitive switch S1 is larger, and the value of the voltage ΔV increased by the voltage level of the node N1 is larger; when the light-emitting diode L1 is darker, the photosensitive switch S1 The photocurrent generated by S1 is small, and the value of the voltage ΔV increased by the voltage level of the node N1 is small.

Then, during the writing period P3, since the second control signal SN has a high logic level, the third transistor T3 is turned on. On the other hand, since the first control signal EM and the third control signal RT have low logic levels, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned off. At this time, the voltage level of the data signal VDATA increases from the voltage V0 in the previous period (compensation period P2) to the voltage Vdi. In addition, the voltage level of the second system voltage terminal VSS is the voltage Vss.

In detail, since the third transistor T3 is turned on during the writing period P3, the increased voltage (Vdi-(V0+ΔV)) at the first end of the first capacitor C1 is coupled to the first capacitor C1 through capacitive coupling. The gate terminal (node N1) of the second transistor T2 increases the voltage level of the node N1 by a voltage (Vdi-(V0+ΔV)). That is, the voltage level of the node N1 is substantially equal to (VH+Vdi-(V0+ΔV)). At this time, the voltage across the gate terminal and the source terminal of the second transistor T2 (Vgs) is (VH+Vdi-(V0+ΔV)-Vss).

Then, during the light-emitting period P4, since the first control signal EM has a high logic level, the first transistor T1 is turned on. On the other hand, since the second control signal SN and the third control signal RT have a low logic level, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

In detail, since the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off, the voltage across the gate terminal and the source terminal (Vgs) of the second transistor T2 is still (VH+Vdi-( V0+ΔV)-Vss). Moreover, since the first transistor T1 is turned on, the second transistor T2 can provide the second driving current Id2 to the light emitting diode L1 according to the voltage across the gate terminal and the source terminal (Vgs).

Substituting the cross voltage (Vgs) between the gate terminal and the source terminal of the second transistor T2 into the formula of the driving current, the second driving current Id2=k(VH+Vdi-(V0+ΔV)-Vss) ² .

In a display panel, if some light-emitting diodes L1 have brighter light-emitting brightness during the compensation period P2, the photocurrent generated by the photosensitive switch S1 is larger, resulting in a larger voltage ΔV, and the second driving current Id2 of P4 during the light-emitting period is higher. Is small, so that the display brightness of the light-emitting diode L1 during the light-emitting period P4 is relatively dark. If the light-emitting brightness of some light-emitting diodes L1 during the compensation period P2 is dark, the photocurrent generated by the photosensitive switch S1 is small, resulting in a small voltage ΔV, and the second driving current Id2 of P4 during the light-emitting period is large, making the light-emitting diodes The display brightness of the body L1 during the light-emitting period P4 is brighter. In this way, the problem of affecting the brightness of the light-emitting diode L1 in the display panel is covered, so as to adjust the brightness of the light-emitting diode L1 during display. Therefore, the brightness unevenness of the display screen is improved.

FIG. 8 is a circuit structure diagram of the pixel driving circuit 400 according to an embodiment of the disclosure. In the embodiment shown in FIG. 8, the pixel driving circuit 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a photosensitive switch S1. , The first capacitor C1 and the light emitting diode L1.

Compared with the pixel driving circuit 300 in the embodiment in FIG. 5, the pixel driving circuit 400 in the embodiment in FIG. 8 is different in that there is no reference voltage terminal VREF. More specifically, in the pixel driving circuit 400 shown in FIG. 8, the first terminal of the fifth transistor T5 is electrically coupled to the first system voltage terminal VDD, and the second terminal of the fourth transistor T4 is electrically connected It is electrically coupled to the second system voltage terminal VSS. In the embodiment of the pixel driving circuit 300, the second driving current Id2=k(VH+Vdi-(V0+ΔV)-Vss) ² , where the voltage VH is determined by the voltage VH of the reference voltage terminal VREF through the fourth The transistor T4 is transferred to the gate terminal of the second transistor T2. Therefore, in the embodiment of the pixel driving circuit 600, the voltage VH is substituted into the aforementioned formula of the second driving current Id2 with the voltage Vss of the second system voltage terminal VSS, so that the second driving current Id2=k(Vss+Vdi-( V0+ΔV)-Vss) ² . That is, in the embodiment of the pixel driving circuit 600, the second driving current Id2=k(Vdi-(V0+ΔV)) ² . The other detailed connection relationships and operation modes of the pixel driving circuit 400 are substantially the same as those of the pixel driving circuit 300 in the previous embodiment in FIG. 5, and will not be repeated here.

FIG. 9 is a circuit structure diagram of a pixel driving circuit 500 according to an embodiment of the disclosure. In the embodiment shown in FIG. 9, the pixel driving circuit 500 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a photosensitive switch S1. , The first capacitor C1 and the light emitting diode L1.

Compared with the pixel driving circuit 300 in the embodiment of FIG. 5, the pixel driving circuit 500 in the embodiment of FIG. 9 is different in the coupling relationship between the photosensitive switch S1 and the fifth transistor T5. More specifically, in the pixel driving circuit 500 shown in FIG. 9, the first terminal of the photosensitive switch S1 is electrically coupled to the reference voltage terminal VREF, and the two terminals of the photosensitive switch S1 are electrically coupled to the fifth transistor T5. , The two terminals of the fifth transistor T5 are electrically coupled to the first terminal (node N2) of the first capacitor C1. The other detailed connection relationships and operation modes of the pixel driving circuit 400 are substantially the same as those of the pixel driving circuit 300 in the previous embodiment of FIG. 5, and will not be repeated here.

FIG. 10 is a circuit structure diagram of the pixel driving circuit 600 according to an embodiment of the disclosure. In the embodiment shown in FIG. 10, the pixel driving circuit 600 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a photosensitive switch S1. , The first capacitor C1 and the light emitting diode L1.

Compared with the pixel driving circuit 500 in the embodiment in FIG. 9, the pixel driving circuit 600 in the embodiment in FIG. 10 is different in that there is no reference voltage terminal VREF. More specifically, in the pixel driving circuit 600 shown in FIG. 10, the first terminal of the fifth transistor T5 is electrically coupled to the first system voltage terminal VDD, and the second terminal of the fourth transistor T4 is electrically coupled It is electrically coupled to the second system voltage terminal VSS. In the embodiment of the pixel driving circuit 500, the second driving current Id2=k(VH+Vdi-(V0+ΔV)-Vss) ² , where the voltage VH is determined by the voltage VH of the reference voltage terminal VREF through the fourth The transistor T4 is transferred to the gate terminal of the second transistor T2. Therefore, in the embodiment of the pixel driving circuit 600, the voltage VH is substituted into the aforementioned formula of the second driving current Id2 with the voltage Vss of the second system voltage terminal VSS, so that the second driving current Id2=k(Vss+Vdi-( V0+ΔV)-Vss) ² . That is, in the embodiment of the pixel driving circuit 600, the second driving current Id2=k(Vdi-(V0+ΔV)) ² . The other detailed connection relationships and operation modes of the pixel driving circuit 600 are substantially the same as those of the pixel driving circuit 500 in the previous embodiment of FIG. 9 and will not be described here.

The aforementioned transistors T1 to T5 are N-type MOSFET (NMOS) switches as an example, but the disclosure is not limited to this. In another embodiment, those skilled in the art can replace the above-mentioned transistors T1 to T5 with P-type MOSFET (PMOS) switches, C-type metal oxide Semiconductor field-effect transistor (C-type MOSFET, CMOS) switches or other similar switching elements, and control the system voltage (for example, the first system voltage terminal VDD and the second system voltage terminal VSS) and control signals (for example, the first The logic levels of the control signal EM, the second control signal SN, and the third control signal RT), the data signal VDATA, and the reference voltage terminal VREF are adjusted correspondingly, and the same functions as in this embodiment can also be achieved.

In summary, the pixel driving circuit of the present disclosure provides the first driving current Id1 to the light-emitting diode L1 during the compensation period P2 through the second transistor T2, so that the light-emitting diode L1 illuminates the photosensitive switch S1, and the photosensitive switch S1 responds The light-emitting diode L1 is irradiated to generate a photocurrent to adjust the size of the second driving current Id2 that the second transistor T2 provides to the light-emitting diode L1 during the subsequent light-emitting period P4 by the photocurrent to improve the display screen. The brightness is uneven.

Although this disclosure has been disclosed in the above implementation manner, it is not intended to limit this disclosure. Anyone with general knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection disclosed shall be subject to the scope of the attached patent application.

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the attached symbols is as follows: 100, 200, 300, 400, 500, 600: pixel drive circuit L1: Light-emitting diode S1: Photosensitive switch C1: The first capacitor C2: second capacitor T1: The first transistor T2: second transistor T3: third transistor T4: The fourth transistor T5: fifth transistor VDD: the first system voltage terminal VSS: The second system voltage terminal VREF: reference voltage terminal VDATA: data signal EM: The first control signal SN: Second control signal RT: third control signal N1, N2: Node

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows: FIG. 1 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 2 is a timing diagram of control signals and data signals of the pixel driving circuit in FIG. 1 according to an embodiment. FIG. 3A is a circuit state diagram of the pixel driving circuit in FIG. 1 during the reset period. FIG. 3B is a circuit state diagram of the pixel driving circuit in FIG. 1 during the compensation period. FIG. 3C is a circuit state diagram of the pixel driving circuit in FIG. 1 during the writing period. Fig. 3D is a circuit state diagram of the pixel driving circuit in Fig. 1 during the light-emitting period. FIG. 4 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 5 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 6A is a timing diagram of control signals and data signals of the pixel driving circuit in FIG. 5 during the reset period and the compensation period according to an embodiment. FIG. 6B is a timing diagram of control signals and data signals of the pixel driving circuit in FIG. 5 during the writing period and the light emitting period according to an embodiment. FIG. 7A is a circuit state diagram of the pixel driving circuit in FIG. 5 during the reset period. Fig. 7B is a circuit state diagram of the pixel driving circuit in Fig. 5 during the compensation period. FIG. 7C is a circuit state diagram of the pixel driving circuit in FIG. 5 during the writing period. FIG. 7D is a circuit state diagram of the pixel driving circuit in FIG. 5 during the light-emitting period. FIG. 8 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 9 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 10 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) none Foreign hosting information (please note in the order of hosting country, institution, date, and number) none

100: Pixel drive circuit

L1: Light-emitting diode

S1: Photosensitive switch

C1: The first capacitor

C2: second capacitor

T1: The first transistor

T2: second transistor

T3: third transistor

T4: The fourth transistor

T5: fifth transistor

VDD: the first system voltage terminal

VSS: The second system voltage terminal

VREF: reference voltage terminal

VDATA: data signal

EM: The first control signal

SN: Second control signal

RT: third control signal

N1, N2: Node

Claims (17)

A pixel drive circuit, including: A light-emitting diode; A first transistor; A second transistor, wherein the first transistor, the second transistor, and the light emitting diode are electrically connected in series and electrically coupled between a first system voltage terminal and a second system voltage terminal ； A first capacitor, the first terminal of which is electrically coupled to the gate terminal of the second transistor; A second capacitor, the first terminal of which is electrically coupled to the second terminal of the first capacitor, and the second terminal of which is electrically coupled to the second system voltage terminal; A third transistor, the first terminal of which is used for receiving a data signal, and the second terminal of which is electrically coupled to the second terminal of the first capacitor; A fourth transistor, the first terminal of which is electrically coupled to a reference voltage terminal, and the second terminal of which is electrically coupled to the gate terminal of the second transistor; A fifth transistor, the first terminal of which is electrically coupled to the second terminal of the fourth transistor, and the gate terminal of which is electrically coupled to the reference voltage terminal; and A photosensitive switch, the first terminal of which is electrically coupled to the second terminal of the fifth transistor, and the second terminal of which is electrically coupled to the second terminal of the first capacitor. The pixel driving circuit according to claim 1, wherein during a compensation period, the second transistor provides a first driving current to cause the light-emitting diode to illuminate the photosensitive switch, and the photosensitive switch is used to generate the light-emitting diode corresponding to the light-emitting diode. A photocurrent irradiated by the polar body, wherein the voltage level of the gate terminal of the second transistor is adjusted by the photocurrent, thereby adjusting the second transistor provided to the first light-emitting diode during a light-emitting period. Two drive current. The pixel driving circuit according to claim 1, wherein the first terminal of the first transistor is electrically coupled to the first system voltage terminal, and the second terminal of the first transistor is electrically coupled to the second circuit The first terminal of the crystal, the second terminal of the second transistor are electrically coupled to the first terminal of the light-emitting diode, and the second terminal of the light-emitting diode is electrically coupled to the second system voltage terminal. The pixel driving circuit according to claim 1, wherein the first terminal of the light-emitting diode is electrically coupled to the first system voltage terminal, and the second terminal of the light-emitting diode is electrically coupled to the second voltage terminal. The first end of the crystal, the second end of the second transistor are electrically coupled to the first end of the first transistor, and the second end of the first transistor is electrically coupled to the second system voltage end. The pixel driving circuit according to claim 1, wherein: The gate terminal of the first transistor is used for receiving a first control signal; The gate terminal of the third transistor is used for receiving a second control signal; The gate terminal of the fourth transistor is used to receive a third control signal; The pixel driving circuit operates in a reset period, a compensation period, a writing period and a light emitting period in sequence; During the reset period, the first control signal has a first logic level, and the second control signal and the third control signal have a second logic level; During the compensation period, the third control signal has the first logic level, and the first control signal and the second control signal have the second logic level; During the writing period, the first control signal and the third control signal have the first logic level, and the second control signal has the second logic level; and During the light-emitting period, the second control signal and the third control signal have the first logic level, and the first control signal has the second logic level. The pixel driving circuit according to claim 1, wherein the pixel driving circuit sequentially operates during a reset period, a compensation period, a writing period, and a light emitting period, wherein: During the reset period, the third transistor, the fourth transistor, and the fifth transistor are turned on, and the first transistor is turned off; During the compensation period, the first transistor, the third transistor, and the fifth transistor are turned on, and the fourth transistor is turned off; During the writing period, the third transistor is turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned off; and During the light-emitting period, the first transistor is turned on, and the third transistor, the fourth transistor, and the fifth transistor are turned off. The pixel driving circuit according to claim 1, further comprising a light-shielding layer for covering the first, the second, the third, the fourth, and the fifth transistor. The pixel driving circuit according to claim 1, wherein the photosensitive switch is a transistor, so that the photosensitive switch has a first terminal, a second terminal, and a gate terminal, wherein the gate terminal of the photosensitive switch is electrically coupled to the photosensitive switch The second end. A pixel drive circuit, including: A light emitting diode, the first terminal of which is electrically coupled to a first system voltage terminal; A first transistor, the first end of which is electrically coupled to the second end of the light emitting diode; A second transistor, the first terminal of which is electrically coupled to the second terminal of the first transistor, and the second terminal of which is electrically coupled to a second system voltage terminal; A third transistor, the first end of which is used to receive a data signal; A capacitor, the first terminal of which is electrically coupled to the second terminal of the third transistor, and the second terminal of which is electrically coupled to the gate terminal of the second transistor; A fourth transistor, the first terminal of which is electrically coupled to the second terminal of the capacitor; A fifth transistor; and A photosensitive switch, wherein the fifth transistor and the photosensitive switch are connected in series and one of the fifth transistor and the photosensitive switch is electrically coupled to the first end of the capacitor. The pixel driving circuit according to claim 9, wherein during a compensation period, the second transistor provides a first driving current to cause the light-emitting diode to illuminate the photosensitive switch, and the photosensitive switch is used to generate a light-emitting diode corresponding to the light-emitting diode. A photocurrent irradiated by the polar body, wherein the voltage level of the gate terminal of the second transistor is adjusted by the photocurrent, thereby adjusting the second transistor provided to the first light-emitting diode during a light-emitting period. Two drive current. The pixel driving circuit according to claim 9, wherein the first terminal of the fifth transistor is electrically coupled to a reference voltage terminal, and the second terminal of the fifth transistor is electrically coupled to the first terminal of the photosensitive switch. The second terminal of the photosensitive switch is electrically coupled to the first terminal of the capacitor, and the second terminal of the fourth transistor is electrically coupled to the reference voltage terminal. The pixel driving circuit according to claim 9, wherein the first terminal of the fifth transistor is electrically coupled to the first system voltage terminal, and the second terminal of the fifth transistor is electrically coupled to the photosensitive switch At the first terminal, the second terminal of the photosensitive switch is electrically coupled to the first terminal of the capacitor, and the second terminal of the fourth transistor is electrically coupled to the second system voltage terminal. The pixel driving circuit according to claim 9, wherein the first terminal of the photosensitive switch is electrically coupled to a reference voltage terminal, and the second terminal of the photosensitive switch is electrically coupled to the first terminal of the fifth transistor, The second terminal of the fifth transistor is electrically coupled to the first terminal of the capacitor, and the second terminal of the fourth transistor is electrically coupled to the reference voltage terminal. The pixel driving circuit according to claim 9, wherein the first terminal of the photosensitive switch is electrically coupled to the first system voltage terminal, and the second terminal of the photosensitive switch is electrically coupled to the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically coupled to the first terminal of the capacitor, and the second terminal of the fourth transistor is electrically coupled to the second system voltage terminal. The pixel driving circuit according to claim 9, wherein the photosensitive switch is a transistor, so that the photosensitive switch has a first terminal, a second terminal, and a gate terminal, wherein the gate terminal of the photosensitive switch is electrically coupled to the photosensitive switch The second end. The pixel driving circuit according to claim 9, wherein the pixel driving circuit operates in a reset period, a compensation period, a writing period, and a light emitting period in sequence, wherein: During the reset period, the third transistor is turned on, the fourth transistor and the fifth transistor are turned on, and the first transistor is turned off; During the compensation period, the first transistor, the fourth transistor, and the fifth transistor are turned on, and the third transistor is turned off; During the writing period, the third transistor is turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned off; and During the light-emitting period, the first transistor is turned on, and the third transistor, the fourth transistor, and the fifth transistor are turned off. The pixel driving circuit according to claim 9, further comprising a light-shielding layer for covering the first, the second, the third, the fourth, and the fifth transistor.

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