TWI732538B - Electronic package - Google Patents

Abstract

An electronic package is formed by arranging two different material encapsulant between a plurality of electronic components stacked on each other to adjust a stress distribution of the electronic package, so a warpage degree of the electronic package can be optimal.

Description

Electronic package

The present invention relates to a semiconductor packaging process, in particular to a multi-chip stacked type electronic package and its manufacturing method.

With the development of the electronics industry, today's electronic products have tended to be designed in the direction of lightness, thinness, shortness and diversification of functions, and semiconductor packaging technologies have also developed different packaging types. In order to meet the requirements of high integration, miniaturization and high circuit performance of semiconductor devices, flip chip bonding packaging technology was developed, and in order to improve the performance of a single semiconductor package ( ability) and capacity (capacity) to meet the trend of miniaturization, large-capacity, and high-speed electronic products. Flip-chip stacking multiple chips on a carrier (such as a package substrate or a lead frame), such as Patent No. TWI331371 (hereinafter referred to as the first case) or Patent No. TWI527170 (hereinafter referred to as the second case).

However, in the conventional multi-chip modularization, as in the previous case, there is a gap between the upper and lower chips, which causes the chip to easily warp and even break during the subsequent high-temperature manufacturing process.

Furthermore, in the previous case 1, the conductive bumps (such as 39) used to electrically connect the upper and lower chips are not covered by the encapsulant (such as 38), so the conductive bumps (such as 38) cannot be effectively dispersed. The stress of the bumps causes the wafers to easily warp, which results in the offset between the upper and lower wafers, and even greatly affects the electrical connection between the upper and lower wafers, resulting in low yield and Poor product reliability and other issues. What's more, when stacking more layers of wafers, the stress will continue to accumulate, making the degree of warpage bend in the same direction more obviously, and wafer breakage is more likely to occur.

On the other hand, in the second case, primer (such as 18a, 18b, 18c) is also filled between the upper and lower chips to cover the conductive bumps (such as 172, 173, 262, 263, 25a) used to electrically connect the upper and lower chips However, the conductive bumps and the coefficient of thermal expansion (CTE) of the primer do not match (mismatch), so uneven thermal stress is prone to occur, resulting in thermal cycle (thermal cycle), resulting in bottom The glue and the chip are pushed against each other to cause warpage of the chip, so that the alignment between the upper and lower chips is shifted, and even the electrical connection between the upper and lower chips is greatly affected. This leads to problems such as low yield and poor product reliability. What's more, when stacking more layers of wafers, the stress will continue to accumulate, making the degree of warpage bend in the same direction more obviously, and wafer breakage is more likely to occur.

In addition, although the second case of the previous case uses an encapsulant (such as 19a, 19b, 19c) to cover the primer to assist the primer to disperse the stress of the conductive bumps, the encapsulant does not cover the conductive bumps , And cannot effectively disperse the stress of these conductive bumps.

Therefore, how to overcome the various problems of the above-mentioned conventional technology has actually become an urgent problem to be solved at present.

In view of the deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a carrier; a first package module is disposed on the carrier and includes at least one first Electronic component, and the lower surface of the first electronic component defines a first arrangement area, the first arrangement area is arranged with one of the first covering portion and the second covering portion, the second covering portion The material of is different from the material of the first cladding part; and the second package module is stacked on the first package module and includes a plurality of second electronic components stacked on top of each other, and each of the second electronic components The lower surface defines a second layout area respectively, so that at least one of the plurality of second layout areas is provided with the first covering portion and the second covering portion relative to the other of the first deployment area. One, wherein a stress balance line is defined between the first package module and the second package module, so that the first encapsulation part and the second encapsulation part are arranged so that the first The strain of the package module and the strain of the second package module are complementary, and the stress of the first package module and the stress of the second package module substantially cancel each other out.

In the aforementioned electronic package, the first covering portion and the second covering portion are partially arranged on the first arrangement area.

In the aforementioned electronic package, the first covering portion and the second covering portion are partially arranged on the second arrangement area.

In the aforementioned electronic package, the first covering part is all arranged on the first arrangement area.

In the aforementioned electronic package, the first covering part is all arranged on the second arrangement area.

In the aforementioned electronic package, the second covering portion is all arranged on the first arrangement area.

In the aforementioned electronic package, the second covering part is all arranged on the second arrangement area.

In the aforementioned electronic package, the coefficient of thermal expansion of the first covering portion is different from the coefficient of thermal expansion of the second covering portion.

In the aforementioned electronic package, the second covering part is a solid filler.

In the aforementioned electronic package, the plurality of second electronic components are stacked on each other by a plurality of conductive components.

In the aforementioned electronic package, the second electronic element is stacked on the first electronic element by a plurality of conductive elements.

In the aforementioned electronic package, the first electronic element is stacked on the carrier by a plurality of conductive elements.

In the aforementioned electronic package, a plurality of the first electronic elements are stacked on the carrier, and each of the first electronic elements is stacked on each other by a plurality of conductive elements.

The aforementioned electronic package includes an encapsulation layer covering the first electronic component and the second electronic component.

In the aforementioned electronic package, the first layout area defines a first section and a second section adjacent to the first section, so that the first section is cross-shaped or rectangular.

In the aforementioned electronic package, the second layout area defines a first section and a second section adjacent to the first section, so that the first section is cross-shaped or rectangular.

In the aforementioned electronic package, the second covering portion is arranged at the corner of the first or second arrangement area.

In the aforementioned electronic package, the second covering portion is arranged on two opposite outer sides of the first or second arrangement area.

It can be seen from the above that the electronic package of the present invention is mainly designed by the combination of the first and second cladding parts to generate strains in different directions. Therefore, compared with the prior art, the present invention can be based on the electronic package For the overall strain condition, the first and second cladding parts are arranged to adjust the stress distribution of the electronic package, so that the degree of warpage of the electronic package can be optimally controlled.

1,2,3,4: electronic package

1a: The first package module

1b: The second package module

1c: cladding structure

10: Carrier

11: The first electronic component

11a: Flip chip side

11b: Stack side

12: The second electronic component

12a: Flip chip side

12b: Stack side

13: conductive element

14,24: The first cladding part

15,25: The second covering part

16: Encapsulation layer

A: The first deployment area

A’: The second deployment area

A1: The first section

A2: Second section

F: Fill in the direction

L: Stress balance line

S1: The first filling space

S2: second filling space

S3: third filling space

S4: The fourth filling space

W1, W2: Warpage direction

FIG. 1 is a schematic cross-sectional view of one embodiment of the electronic package of the present invention.

Figures 1'and 1" are schematic top views of Figure 1 in different aspects.

Figures 1A and 1A' are schematic cross-sectional views of other aspects of Figure 1.

Figure 2 is a schematic cross-sectional view of another embodiment of the electronic package of the present invention.

Figures 2', 2A and 2A' are schematic cross-sectional views of other aspects of Figure 2.

FIG. 3 is a schematic cross-sectional view of other embodiments of the electronic package of the present invention.

Figures 3A and 3A' are schematic cross-sectional views of other aspects of Figure 3.

Figures 4 and 4'are schematic cross-sectional views of other different embodiments of Figure 1.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment, without affecting the effects and objectives that can be achieved by the present invention, should still fall within the scope of the present invention. The technical content disclosed by the invention can be covered. At the same time, references in this specification include "first", "second", "third", "shang", The terms "下" and "一" are only for ease of description and are not used to limit the scope of implementation of the present invention. The change or adjustment of the relative relationship between them, without substantive changes to the technical content, should be It is regarded as the scope where the present invention can be implemented.

FIG. 1 is a schematic cross-sectional view of the electronic package 1 of the present invention. As shown in Fig. 1, the electronic package 1 includes: a carrier 10, a first package module 1a arranged on the carrier 10, and a first package module 1a stacked on the first package module 1a The second encapsulation module 1b, the first encapsulation module 1a and the second encapsulation module 1b stacked on each other by a plurality of conductive elements 13, and the first encapsulation module 1a and the second encapsulation module 1b are covered by an encapsulation layer 16 The second package module 1b.

The first packaging module 1a includes at least one first electronic component 11, and the lower surface of the first electronic component 11 defines a first layout area A for arranging the covering structure 1c, wherein the covering The structure 1c includes a first coating portion 14 and/or a second coating portion 15, and the material of the second coating portion 15 is different from the material of the first coating portion 14.

The second package module 1b includes a plurality of second electronic components 12 stacked, and the lower surface of the second electronic component 12 defines a second layout area A'to lay the first covering portion 14 And/or the second covering portion 15, wherein the first electronic element 11 and the second electronic element 12 are stacked on each other by a plurality of conductive elements 13, so that the covering structure 1c covers the conductive elements 13.

The carrier 10 is, for example, a package substrate with a core layer and a circuit structure or a coreless circuit structure, which includes at least one insulating layer and at least one circuit layer combining the insulating layer, such as at least one fan Fan out type redistribution layer (RDL). It should be understood that the carrier 10 can also be other chip-carrying plates, such as a lead frame, a wafer, or other carrier with metal routing, and is not limited to the above.

In this embodiment, the carrier 10 has various manufacturing processes. For example, a copper circuit layer can be fabricated by a wafer process, and silicon nitride or silicon oxide can be formed by chemical vapor deposition (CVD). As an insulating layer; alternatively, the copper circuit layer can be formed by a general non-wafer process, that is, a low-cost polymer dielectric material is used as the insulating layer, such as polyimide (PI), polyimide Polybenzoxazole (PBO for short), Prepreg (PP for short), molding compound, photosensitive dielectric layer or other materials are formed by coating.

In this embodiment, the number of the first electronic components 11 is two, the first electronic components 11 are stacked on each other and one of them is connected to the carrier 10, and the plurality of second electronic components 12 are Stacked on each other and one of them is stacked on the first electronic component 11.

In this embodiment, the first electronic element 11 is an active element, a passive element, or a combination thereof, wherein the active element is a semiconductor chip, and the passive element is a resistor, a capacitor, and an inductor. For example, the first electronic component 11 is a semiconductor chip, the upper surface of which is used as the stacking side 11b, and the lower surface is used as the flip chip side 11a, so that the first electronic components 11 have their flip chip sides 11a by a plurality of Bump-shaped conductive elements 13 such as solder materials, metal pillars or others are flip-chip bonded to the stacking side 11b of the other to be electrically connected to each other, and the first electronic element 11 at the bottom is connected to each other through the flip chip The conductive elements 13 are flip-chip bonded to the carrier 10 and electrically connected to the circuit layer of the carrier 10.

Furthermore, the second electronic component 12 is an active component, a passive component, or a combination thereof, wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. For example, the second electronic component 12 is a semiconductor chip, the upper surface of which is used as the stack side 12b, and the lower surface is used as the flip chip side 12a, so that the second electronic components 12 pass through the flip chip side 12a. Some conductive elements 13 are flip-chip bonded to the stack side 12b of the other to be electrically connected to each other The second electronic component 12 at the bottom is connected to the stacking side 11b of the first electronic component 11 through the conductive components 13 and electrically connected to the first electronic component 11.

Furthermore, the entire lower surface of each of the first electronic components 11 (such as the flip chip side 11a) and the entire bottom surface of each of the second electronic components 12 (such as the flip chip side 12a) are used as the first and second layout regions A,A'. For example, the first and second layout areas A, A'are rectangular such as squares, but there is no particular limitation. Specifically, the first or second layout area A, A'can define a first section A1 and a second section A2 adjacent to the first section A1 according to requirements, as shown in Figure 1'. Glyph-shaped first section A1, or rectangular first section A1 like a rectangle as shown in Figure 1".

In addition, a first filling space S1 is formed between the first electronic component 11 and the carrier 10, and a second filling space S2 is formed between each of the first electronic components 11, and each of the first electronic components A third filling space S3 is formed between the component 11 and the second electronic component 12, and a fourth filling space S4 is formed between each second electronic component 12. It should be understood that the number of the second filling space S2 can be determined according to requirements, such as zero layer (such as the embodiment of the first electronic component 11 shown in Figure 4 or 4') or multiple layers, and nothing special It is limited, and the number of the fourth filling space S4 can also be determined according to requirements, such as one or more layers, and there is no particular limitation.

The first coating part 14 is a base rubber material in a fluid state, and its CTE value is about 52 to 109.

In this embodiment, the first covering portion 14 is partially arranged on the first and second arrangement areas A, A'. For example, the first covering portion 14 is only arranged on the first section A1, as shown in Figure 1'or 1". Specifically, the first covering portion 14 is partially arranged on the first to the first section A1. The four filling spaces S1, S2, S3, and S4 are on the layout area A.

Furthermore, in another embodiment, such as the electronic package 2 shown in Figures 2, 2', 2A, and 2A', the first covering portion 24 can also be all arranged in the first and second arrangement areas A, A'up. For example, the first covering portion 24 may be completely arranged in the first to fourth filling spaces S1, S2, S3, S4 At least one of them (the first filling space S1 as shown in Figure 2, the second to fourth filling spaces S2, S3, S4 as shown in Figure 2A, or the first and The third filling space S1, S3) on the layout area. It should be understood that, as shown in Fig. 3A', the first covering parts 14, 24 can be partially and completely arranged on different first and/or second arrangement areas A, A'at the same time.

The second coating portion 15 is a solid filler, such as a non-conductive film (NCF), with a CTE value of about 32 to 98, so the material of the first coating portion 14 is different from The material of the second covering portion 15, for example, the thermal expansion coefficient of the first covering portion 14 is different from the thermal expansion coefficient of the second covering portion 15.

In this embodiment, the second covering portion 15 is partially arranged on the first and second arrangement areas A, A'. For example, the second covering portion 15 is only arranged on the second section A2, at the corners as shown in Figure 1'or on the two opposite outer sides as shown in Figure 1". Specifically, the second wrapper The covering portion 15 is partially arranged on each of the first to fourth filling spaces S1, S2, S3, and S4. It should be understood that the first covering portion 14 and the second covering portion 15 are in the first The configuration shown in'and 1” can be arranged in interchangeable sections.

Furthermore, in another embodiment, as shown in Figures 2, 2', 2A, and 2A', the second covering portion 25 can also be all arranged in the first and/or second arrangement areas A, A 'on. For example, the second covering portion 25 may be completely arranged in at least one of the first to third filling spaces S1, S2, S3, S4 (such as the second to third filling spaces S2, S3, S4, the first filling space S1 as shown in Figure 2A, or the second and third filling spaces S2, S4 as shown in Figure 2A'). It should be understood that, as in the electronic package 3 shown in Fig. 3 or 3A, the second cladding portions 15, 25 can be partially arranged and completely arranged in different first and/or second arrangement areas A, A at the same time. 'on.

Therefore, the layout patterns of these layout areas can be the same (as shown in Figure 1 or 1A) or different (as shown in Figure 1A', 2, 2', 2A, 2A', 3, 3A, or 3A' ). It should be understood that there are many filling methods for the first to fourth filling spaces S1, S2, S3, and S4, which can be configured according to requirements The layout type of the first and/or second layout areas A, A', such as based on the first to fourth filling spaces S1, S2, S3, S4 (such as longitudinal) or based on the first section A1 and the first section Two sections A2 (such as horizontal), symmetrical (as shown in Figures 3 and 3A') or asymmetrical (as shown in Figure 3A), staggered (as shown in Figure 1A' or 2A') or non-staggered (As shown in Figure 3), regular (as shown in Figure 1 or 1A) or irregular (as shown in Figure 2 or 2A) and other permutations and combinations are not limited to the above-mentioned Figures 1 to 3A' State.

In addition, the electronic package 1 defines a stress balance line L according to its overall stress distribution to facilitate adjustment of the layout patterns of the first and second layout areas A, A'. For example, the cladding structures 1c of the first to fourth filling spaces S1, S2, S3, S4 complementarily cooperate to appropriately control the warpage degree of the electronic package 1, so the stress balance line L is The electronic package 1 defines a first package module 1a (the lower half as shown in Figure 1) and a second package module 1b (the upper half as shown in Figure 1) that are adjacent to each other to Make the strain of the first package module 1a (the warpage direction W1 of the upper convex arc line shown in Figure 1) and the strain of the second package module 1b (the warpage of the lower concave arc line shown in Figure 1 The directions W2) are substantially complementary (for example, the warping directions W1 and W2 are opposite to each other), and the stresses of the two are almost eliminated from each other. Specifically, as shown in Figures 1 to 4, the stress balance line L is located at the uppermost first electronic component 11 (or at the lowermost second electronic component 12), so that the first package module 1a At least one first electronic component 11 is included, and the second package module 1b includes a plurality of second electronic components 12. It should be understood that when the first packaging module 1a is configured with the first covering portion 14, the second packaging module 1b must be configured with the second covering portion 15; when the first packaging module 1a is configured with the second covering portion 15 When covering the portion 15, the second packaging module 1 b must be provided with the first covering portion 14. Therefore, in the present invention, the first and second cladding portions 14, 15 of different materials are arranged on the first and second package modules 1a, 1b according to the stress distribution.

In addition, if the first and second covering parts 14, 15 need to be arranged in a single deployment area (as shown in Figures 1'and 1"), the solid second covering part 15 can be attached to the The first Or on the surface of the second electronic component 11, 12 so that the second cladding portion 15 forms a channel (that is, the first section A1), after the first electronic component 11 or the second electronic component 12 undergoes the stacking step , Fill the fluid-like first covering part 14 into one of the four ports of the channel (ie the first section A1) by dispensing (the filling direction F as shown in Figure 1') , The first covering portion 14 is filled into the filling space corresponding to the first section A1. Specifically, the multi-axial channel shown in Fig. 1'facilitates the diffusion and overflow of the first cladding portion 14 to fill up the filling space corresponding to the first section A1 (but its production is more complicated), and The uniaxial channel shown in Figure 1" is good for manufacturing (but it is less likely to fill up the filling space).

The encapsulation layer 16 is an insulating material, such as polyimide (PI), dry film, encapsulation gel such as epoxy or molding compound, which can be laminated ( It is formed by lamination, coating or molding.

In summary, in the electronic package 1, 2, 3, and 4 of the present invention, the coating structure 1c mainly includes two different materials of coating portions (the first and second coating portions 14, 15) , In order to generate strains in different directions, so when the cladding structure 1c is applied to the electronic packages 1, 2, 3, and 4 of the multi-layer filled spaces (the first to fourth filled spaces S1, S2, S3, S4), The stress distribution of the electronic package 1, 2, 3, 4 can be adjusted by the layout of the first and second cladding parts 14, 15 to make the electronic package 1, 2, 3, 4 warp The degree can be optimally controlled, that is, the deformation of the electronic package 1, 2, 3, 4 is minimized. For example, because the thermal expansion coefficient of the first coating portion 14 is different from the thermal expansion coefficient of the second coating portion 15, the filling methods of the first to fourth filling spaces S1, S2, S3, and S4 can be configured according to requirements. The layout patterns of the first and second layout areas A, A'present a variety of permutations and combinations, so that the stress distribution of the electronic package 1, 2, 3, and 4 can be in a balanced state.

Furthermore, the solid NCF (the second coating part 15) has the characteristic of uniform stress spreading, which is beneficial to suppress the uneven spread of the stress of the fluid base rubber material (the first coating part 14). Therefore, when the two are matched with each other , The stress can be reduced each other, so compared to the conventional technology that uses a fluid primer to cover all conductive bumps, the coating structure 1c of the present invention can effectively avoid the layers (the first to fourth filling spaces S1, S2, S3, S4) The effect of stress accumulation, that is, the stresses from opposite sides of the stress balance line L almost cancel each other.

In addition, as shown in Figures 2 and 2', the thermal expansion coefficient of the first cladding portion 24 is greater than that of the second cladding portion 25, and the solid NCF (second cladding portion 25) has uniform stress Due to the diffusion characteristics, the first cladding portion 24 can be arranged in the first and/or second filling space S1, S2 (that is, corresponding to the first layout area A of the first packaging module 1a). Therefore, in manufacturing, The manufacturing process of the second cladding part 25 on the upper part of the electronic package 1, 2, 3, 4 can be performed first, and then the manufacturing process of the first cladding part 24 at the lower part is performed. At this time, the second coating part 25 is The stress distribution and the degree of warpage have been set, so it is less affected by the high-temperature thermal process of the first cladding portion 24. Therefore, when the first cladding portion 24 is filled in the final step, the overall stress distribution of the electronic package 2 can be effectively and well controlled. Specifically, when the first coating portion 24 is filled in to complete solidification, the first coating portion 24 will shrink during the cooling process, causing the strain direction to be reversed and the degree of warping will be reduced. The error range to achieve the expected degree of warpage.

In addition, if the first and second covering parts 14, 15 need to be arranged on a single deployment area, the second covering part 15 can be used to form a fluid channel during the manufacturing process, so as to follow the first covering part. In the glue dispensing process of the part 14, the remaining filling space corresponding to the first or second layout area A, A'can be filled up along the channel by dispensing glue only once, thus speeding up the overall production time.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

1: Electronic package

1a: The first package module

1b: The second package module

1c: cladding structure

10: Carrier

11: The first electronic component

11a: Flip chip side

11b: Stack side

12: The second electronic component

12a: Flip chip side

12b: Stack side

13: conductive element

14: The first covering part

15: The second covering part

16: Encapsulation layer

A: The first deployment area

A’: The second deployment area

A1: The first section

A2: Second section

L: Stress balance line

S1: The first filling space

S2: second filling space

S3, S4: third filling space

W1, W2: Warpage direction

Claims (17)

An electronic package comprising: a carrier; a covering structure comprising a first covering part and/or a second covering part, and the material of the second covering part is different from the material of the first covering part ; The first package module is set on the carrier, and includes at least one first electronic component, and the lower surface of the first electronic component defines a first layout area, the first layout area is arranged with the first One of a covering portion and a second covering portion, wherein the first electronic element is stacked on the carrier by a plurality of conductive elements to form a filling space between the first electronic element and the carrier Between, the cladding structure fills the filled space and contacts the plurality of conductive elements; and the second package module is stacked on the first package module and includes a plurality of second electronic components stacked to Let another filling space be formed between each of the second electronic components and between the first electronic component and the second electronic component, and the lower surface of each of the second electronic components defines a second layout area, so as to Make at least one of the plurality of second deployment areas to be provided with the first covering portion and the second covering portion relative to the other of the first deployment area, so that the covering structure fills the other one Filling space, wherein a stress balance line is defined between the first package module and the second package module, so that the first encapsulation part and the second encapsulation part are arranged so that the first The strain of the package module and the strain of the second package module are complementary, and the stress of the first package module and the stress of the second package module substantially cancel each other out. According to the electronic package described in item 1 of the scope of patent application, the first covering portion and the second covering portion are partially arranged on the first arrangement area. The electronic package described in item 1 of the scope of patent application, wherein the first The covering part and the second covering part are partially arranged on the second arrangement area. According to the electronic package described in item 1 of the scope of patent application, the first covering part is all arranged on the first arrangement area. According to the electronic package described in item 1 of the scope of patent application, the first covering part is all arranged on the second arrangement area. According to the electronic package described in item 1 of the scope of the patent application, the second covering part is all arranged on the first arrangement area. According to the electronic package described in item 1 of the scope of patent application, the second covering part is all arranged on the second arrangement area. According to the electronic package described in claim 1, wherein the coefficient of thermal expansion of the first covering portion is different from the coefficient of thermal expansion of the second covering portion. According to the electronic package described in item 1 of the scope of the patent application, the second covering part is a solid filler. According to the electronic package described in claim 1, wherein the plurality of second electronic elements are stacked on each other by a plurality of other conductive elements. According to the electronic package described in claim 1, wherein the second electronic element is stacked on the first electronic element by a plurality of other conductive elements. According to the electronic package described in claim 1, wherein a plurality of the first electronic elements are stacked on the carrier, and each of the first electronic elements is stacked on each other by a plurality of other conductive elements. The electronic package described in item 1 of the scope of the patent application includes an encapsulation layer covering the first electronic component and the second electronic component. For the electronic package described in item 1 of the scope of the patent application, wherein the first layout area defines a first section and a second section adjacent to the first section, so that the first section is Cross or rectangle. For example, the electronic package described in item 1 of the scope of patent application, wherein the second layout area defines a first section and a second section adjacent to the first section, so that the first section is Cross or rectangle. According to the electronic package described in item 1 of the scope of patent application, the second covering part is arranged at the corner of the first or second arrangement area. According to the electronic package described in item 1 of the scope of patent application, the second covering portion is arranged on two opposite outer sides of the first or second arrangement area.

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