TWI729794B - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes insulating layers and conductive layers alternately stacked along a first direction. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a three-dimensional semiconductor device and a manufacturing method thereof.

Recently, as the demand for more excellent memory devices has gradually increased, various three-dimensional (3D) memory devices have been provided, such as 3D NAND memory devices, 3D NAND or memory devices (3D NOR) Or three-dimensional and memory device (3D AND).

Generally speaking, a three-dimensional memory device includes a substrate and a stack structure disposed on the substrate. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately. In addition, the three-dimensional memory device includes an array area and a step area adjacent to the array area. The memory serial structure and the dummy memory serial structure can be respectively formed in the array area and the step area by the same process. Among them, the memory serial structure and the dummy memory serial structure respectively include an epitaxial growth layer extending upward from the substrate.

However, in current three-dimensional memory devices, it is often found that the growth of the epitaxial growth layer of the dummy memory tandem structure in part of the step area is not good (for example, epitaxial growth). The crystal growth layer is skewed or not high enough), which may cause a short circuit and cause electrical problems (such as leakage current).

The present invention relates to a semiconductor device. The body portion of the step area of the semiconductor device includes a first area and a second area. In the first area, the number of conductive layers corresponding to the dummy memory serial structure is between 1-10. In the second area, the number of conductive layers corresponding to the dummy memory serial structure is greater than 10. Because in the same unit area in the top view, the area of the dummy memory serial structure in the first area is larger than the area of the dummy memory serial structure in the second area (that is, the area of the first area used to form the dummy memory The area of the first opening of the memory serial structure is larger than the area of the first opening of the second region for forming the dummy memory serial structure), during the formation of the dummy memory serial structure including the epitaxial growth layer, The effect of exhausting the etching gas in the first region is better than the effect of exhausting the etching gas in the second region, which can reduce the adverse effects of the etching gas on the epitaxial growth layer in the first region. Therefore, compared with the comparative example in which the area of the dummy memory string structure in the first area is not larger than the area of the dummy memory string structure in the second area, the area of the dummy memory string structure in the first area of this case The epitaxial growth layer can have better growth conditions, which can prevent the epitaxial growth layer from being skewed or insufficient in height, thereby avoiding short circuit and leakage current problems.

According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a stack structure disposed on the substrate, and a plurality of dummy memory serial structures. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The dummy memory serial structure is disposed in a step area of the semiconductor device and passes through the stack structure along the first direction, wherein the step area includes a body portion, and the body portion includes adjacent A first zone and a second zone. In the first area, the number of conductive layers corresponding to the dummy memory serial structure is between 1-10; in the second area, the number of conductive layers corresponding to the dummy memory serial structure is greater than 10. In a top view, in the same unit area, the area of the dummy memory serial structure in the first area is larger than the area of the dummy memory serial structure in the second area.

According to another aspect of the present invention, a method of manufacturing a semiconductor device is provided. The manufacturing method of the semiconductor device includes the following steps. First, a substrate and a stack structure arranged on the substrate are provided. After that, a plurality of first openings are formed in the step region of the semiconductor device. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The first opening passes through the stack structure along the first direction, wherein the step area includes a body portion, and the body portion includes a first area and a second area adjacent to each other. In the first region, the number of conductive layers corresponding to the first opening is between 1-10; in the second region, the number of conductive layers corresponding to the first opening is greater than 10. In a top view, in the same unit area, the area of the first opening in the first zone is larger than the area of the first opening in the second zone.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100, 100A, 100P, 200, 300: semiconductor device

110: substrate

110a: upper surface

112: Insulation layer

114: conductive layer

116: Memory serial structure

116h: array opening

118,118p,218,318,418: Dummy memory serial structure

118h, 118hp, 218h, 318h, 418h: first opening

120: contact structure

120’: Predetermined position of contact structure

1161,1181: epitaxial growth layer

A,A’,B,B’: the end of the section line

AR: Array area

AS: Step area

AS1: Main unit

AS1a: Zone 1

AS1b: Zone 2

AS2: Dummy part

C1~C5, Ca1, Cb1, Ca2, Cb2, Ca3, Cb3, Ca4, Cb4: center point

R1, R2: row

S1: Stacked structure

UA: unit area

Figures 1A~2B show a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention; Figure 3A shows a partial top view of a semiconductor device according to a comparative example; Figure 3B shows A of Figure 3A -A' cross-sectional view of the connection line; Fig. 4A shows a partial top view of a semiconductor device according to an embodiment of the present invention; Fig. 4B shows a cross-sectional view of the A-A' connection of Fig. 4A; Fig. 5 shows a cross-sectional view of a connection according to an embodiment of the present invention A graph of the formation height of the epitaxial growth layer of the dummy memory tandem structure of the semiconductor device and the semiconductor device of the comparative example; FIG. 6A shows the epitaxial growth of the abnormal dummy memory tandem structure of the semiconductor device of the comparative example Figure 6B shows a scanning result of an epitaxial growth layer of an abnormal dummy memory tandem structure of a semiconductor device according to an embodiment of the present invention; Figure 7 shows a scanning result of an epitaxial growth layer according to another embodiment of the present invention A partial top view of a semiconductor device; FIG. 8A shows a partial top view of a semiconductor device according to another embodiment of the present invention; FIG. 8B shows a cross-sectional view of the A-A' connection of FIG. 8A; FIG. 9A shows The scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device of the comparative example is shown; FIG. 9B shows the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device according to an embodiment of the present invention The scanning result of the growth layer; Fig. 9C shows the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device according to another embodiment of the present invention; and Fig. 10 shows another according to the present invention A partial top view of the semiconductor device of the embodiment.

In the following detailed description, for the convenience of explanation, various specific details are provided to understand the embodiments of the present disclosure as a whole. However, it should be understood that one or more embodiments can be implemented without employing these specific details. In other cases, in order to simplify the drawings, the known structures and components are shown in schematic diagrams.

FIGS. 1A to 2B show a flowchart of a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention. Among them, FIGS. 1A and 2A are top views of the manufacturing process of the semiconductor device 100 according to an embodiment of the present invention. Figure 1B is a cross-sectional view of the line A-A' and the line B-B' of Figure 1A. Figure 2B shows a cross-sectional view of the line A-A' and the line B-B' of Figure 2A.

Please refer to FIGS. 1A and 1B at the same time to provide a substrate 110 and a stack structure S1 disposed on the substrate 110. The stack structure S1 is, for example, disposed on the upper surface 110a of the substrate 110 along the first direction (for example, the Z direction). The stacked structure S1 includes a plurality of insulating layers 112 and a plurality of conductive layers 114 alternately stacked along a first direction (for example, the Z direction). Then, the conductive layer 114 is trimmed through general memory processing steps, so that the edge portion of the conductive layer 114 has a stepped structure, so as to form the semiconductor device 100 including the array region AR and the stepped region AS. Thereafter, a plurality of array openings 116h and a plurality of first openings 118h are respectively formed in the array area AR and the step area AS by the same process (for example, an etching process). The array opening 116h and the first opening 118h pass through the stack structure S1 along the first direction (for example, the Z direction) and expose the substrate 110.

The step area AS includes a body portion AS1 electrically connected to the array area AR and a dummy portion AS2 not electrically connected to the array area AR. In the upper view, the first opening 118h is staggered with the predetermined position 120' of the contact structure of the main body AS1. And, the step area AS The main body AS1 includes a first area AS1a and a second area AS1b that are adjacent to each other. Since the conductive layer 114 in the body portion AS1 of the step region AS has a stepped structure, the number of the conductive layers 114 corresponding to the first opening 118h in different regions is different. In the first area AS1a, the number of conductive layers 114 corresponding to the first opening 118h is between 1 and 10, that is, the first area AS1a corresponds to the first opening 118h passing through the bottom (mostly adjacent to the substrate 110).的) 1-10 layers of conductive layer 114 area. In the second area AS1b, the number of conductive layers 114 corresponding to the first opening 118h is greater than 10, that is, the second area AS1b corresponds to the first opening 118h through the bottom (most adjacent to the substrate 110) greater than 10 layers of conductive layer 114 area. For example, in the first area AS1a, when the number of conductive layers 114 corresponding to the first opening 118h is 10, the 10th conductive layer 114 from the bottom is filled with insulating material without a conductive layer When the number of conductive layers 114 corresponding to the first opening 118h is 5, the fifth conductive layer 114 from the bottom is filled with insulating material without a conductive layer, and so on. In the second area AS1b, when the number of conductive layers 114 corresponding to the first opening 118h is 11, the eleventh conductive layer 114 from the bottom is filled with insulating material without a conductive layer; When the number of conductive layers 114 corresponding to an opening 118h is 15, the 15th conductive layer 114 from the bottom is filled with insulating material without a conductive layer, and so on. Therefore, when it is stated that "the number of conductive layers 114 corresponding to the first opening 118h in the first area AS1a is between 1 and 10", it means that the first opening 118h in the first area AS1a exists from the bottom. The number of conductive layers 114 is between 1 and 10; when it is stated that "the number of conductive layers 114 corresponding to the first opening 118h in the second area AS1b is greater than 10", it means that the number of conductive layers 114 in the second area AS1b The first opening 118h exists in an environment where the number of conductive layers 114 from the bottom is greater than 10 And, the first opening 118h in the first area AS1a and the first opening 118h in the second area AS1b may have the same depth.

From the perspective of the top view, the pattern formed by the first opening 118h in the first area AS1a is different from the pattern formed by the first opening 118h in the second area AS1b. In detail, in a same unit area in a top view, the area of the first opening 118h in the first area AS1a is larger than the area of the first opening 118h in the second area AS1b. According to this embodiment, in the same unit area, the number of first openings 118h in the first area AS1a is greater than the number of first openings 118h in the second area AS1b, and in the top view, each of the first areas AS1a The area of each first opening 118h is equal to the area of each first opening 118h in the second area AS1b. For example, in the same unit area, the number of first openings 118h in the first area AS1a is twice the number of first openings 118h in the second area AS1b, but the present invention is not limited to this. In other embodiments, the number of the first openings 118h in the first area AS1a may be three times or more than the number of the first openings 118h in the second area AS1b (in a same unit area), and the upper In the view, the area of each first opening 118h in the first area AS1a may be different from the area of each first opening 118h in the second area AS1b. For example, in the top view, each first opening 118h in the first area AS1a The area of may be greater than the area of each first opening 118h of the second region AS1b.

FIG. 1B only exemplarily shows eight conductive layers 114, but the present invention is not limited to this. The stacked structure S1 may include more than eight conductive layers 114, which can be adjusted according to requirements. In an embodiment, the stacked structure S1 may include 60 conductive layers 114.

In some embodiments, the substrate 110 may be a silicon substrate or other suitable substrates. The insulating layer 112 may be formed of oxide, such as silicon dioxide (SiO ₂ ). The conductive layer 114 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly-silicon). ) Or other suitable materials. The insulating layer 112 and the conductive layer 114 can be formed by deposition methods, respectively. The deposition method for forming the insulating layer 112 is, for example, plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), for example, using the reactive gases silane (SiH ₄ ) and nitrous oxide (N ₂ O). . When the insulating layer 112 made of silicon dioxide is formed by the plasma-assisted chemical vapor deposition method, the reaction formula is as follows: SiH ₄ +2N ₂ O→SiO ₂ +2N ₂ +2H ₂ Formula 1

In some embodiments, the gas generated in Formula 1 (for example, nitrogen and hydrogen) may remain in the substrate 110.

In some embodiments, the array opening 116h and the first opening 118h can be formed by an etching method, such as a dry etching method. In some embodiments, the substrate 110 may be overetched so that the bottoms of the array opening 116h and the first opening 118h are lower than the upper surface 110a of the substrate 110. However, the etching step may react with the gas remaining in the substrate 110 to produce ammonia (NH ₃ ) as a by-product. Ammonia (NH ₃ ) will not be conducive to the formation of subsequent epitaxial growth layers 1161 and 1181 (shown in Figure 2B). In particular, compared to the second area AS1b, the substrate 110 in the first area AS1a may have a higher concentration of ammonia remaining.

According to this embodiment, since the area of the first opening 118h in the first area AS1a is larger than the area of the first opening 118h in the second area AS1b in the same unit area, the first area AS1a is compared with the second area AS1b. In terms of having more paths for exhausting etching gas (such as ammonia) (through the first opening 118h), the effect of exhausting etching gas (such as ammonia) in the first zone AS1a is better than that of the second zone AS1b. , It can reduce The epitaxial growth layer 1161 (shown in Figure 2B) of the light first region AS1a is adversely affected by the etching gas.

After that, please refer to FIGS. 2A and 2B at the same time to respectively form a memory serial structure 116 and a dummy memory serial structure 118 in the array opening 116h and the first opening 118h, wherein each memory serial structure 116 and each dummy memory The bulk tandem structure 118 includes an epitaxial growth layer 1161 and 1181 respectively. The epitaxial growth layer 1161 and 1181 are extended from the substrate 110 along a first direction (for example, the Z direction). The epitaxial growth layers 1161 and 1181 are, for example, silicon epitaxial growth layers. Next, a contact structure 120 is formed at a predetermined position 120' of the contact structure of the main body AS1. The contact structure 120 is disposed in the body portion AS1 of the step area AS, and the contact structure 120 located in the body portion AS1 is electrically connected to the corresponding conductive layer 114, respectively. The dummy memory serial structure 118 of the dummy portion AS2 is a structure for supporting the semiconductor device 100 and is not electrically connected to other devices or components.

According to an embodiment of the present invention, in the same unit area in the top view, the area of the dummy memory string structure 118 in the first area AS1a is larger than the area of the dummy memory string structure 118 in the second area AS1b. In addition, in a same unit area, the number of dummy memory serial structures 118 in the first area AS1a may be greater than the number of dummy memory serial structures 118 in the second area AS1b (for example, twice).

In some embodiments, the memory serial structure 116 and the dummy memory serial structure 118 include the same structure and materials. For example, in addition to the epitaxial growth layers 1161 and 1181, the memory serial structure 116 and the dummy memory serial structure 118 further include a memory layer, a channel layer, and an insulating pillar (not shown). In some embodiments, the memory serial structure 116 and the dummy memory serial structure 118 may have different sizes.

In some embodiments, the memory serial structure 116, the array opening 116h, the dummy memory serial structure 118, the first opening 118h, and the contact structure 120 have rectangular cross-sections. However, the present invention is not limited thereto. In other implementations In an example, the cross-sections of the memory serial structure 116, the array opening 116h, the dummy memory serial structure 118, the first opening 118h, and the contact structure 120 may have a circular shape, an oval shape, or other suitable geometric shapes.

In some embodiments, the bottom conductive layer 114 in the conductive layer 114 (that is, the conductive layer 114 closest to the substrate 110) can be used as a ground selection line; the conductive layer 114 in the middle part of the stack structure S1 can be used as a character element Line; the topmost conductive layer 114 (that is, the conductive layer 114 farthest from the substrate 110) can be used as a series selection line.

In the same unit area in the upper view, the area of the dummy memory serial structure 118 in the first area AS1a is larger than the area of the dummy memory serial structure 118 in the second area AS1b (that is, the first area AS1a The area of the first opening 118h for forming the dummy memory string structure 118 is larger than the area of the first opening 118h for forming the dummy memory string structure 118 in the second region AS1b), and the formation includes an epitaxial growth layer During the dummy memory tandem structures 116 and 118 of 1161 and 1181, the effect of exhausting the etching gas in the first area AS1a is better than the effect of exhausting the etching gas in the second area AS1b, which can reduce the epitaxial growth layer in the first area AS1a 1181 is adversely affected by the etching gas. Therefore, compared with the comparative example in which the area of the dummy memory serial structure in the first area is not larger than the area of the dummy memory serial structure in the second area, the dummy memory serial structure in the first area AS1a of this case The epitaxial growth layer 1181 of 118 can have better growth conditions, which can prevent the epitaxial growth layer 1181 from being skewed or insufficient in height, thereby avoiding short circuit and leakage current problems (such as poor growth of the epitaxial growth layer and ground selection Line short-circuit).

In this embodiment, even in the first region AS1a, the height of the epitaxial growth layer 1181 can still be greater than the height of the top surface of the conductive layer 114 of the conductive layer 114 that is closest to the first layer of the substrate 110.

FIG. 3A shows a partial top view of a semiconductor device 100P according to a comparative example. Figure 3B shows a cross-sectional view of the line A-A' in Figure 3A. FIG. 4A shows a partial top view of a semiconductor device 100A according to an embodiment of the invention. Fig. 4B shows a cross-sectional view of the line A-A' in Fig. 4A. The semiconductor device 100A of the present invention is similar to the semiconductor device 100, except that the memory serial structure 116, the array opening 116h, the dummy memory serial structure 118, the first opening 118h and the contact structure between the semiconductor device 100A and the semiconductor device 100 The shape of the cross section of 120 is different.

The difference between the semiconductor device 100P of the comparative example and the semiconductor device 100A of this case lies in the pattern of the first opening 118hp (or the dummy memory serial structure 118p) in the first region AS1a, and the other structures are the same or similar. That is, the first opening 118hp (or the dummy memory serial structure 118p) has the same pattern in the first area AS1a and the second area AS1b (as shown in FIG. 3A), and the first opening 118h (or the dummy memory serial structure 118p) The memory serial structure 118) has different patterns in the first area AS1a and the second area AS1b (as shown in FIG. 4A). More specifically, from the top view of Figure 3A, under the same unit area UA, the area of the first opening 118hp (or the dummy memory serial structure 118p) of the first area AS1a is equal to the second The area of the first opening 118hp (or the dummy memory serial structure 118p) of the area AS1b. In contrast, from the top view of FIG. 4A, under the same unit area UA, the area of the first opening 118h (or the dummy memory serial structure 118) of the first area AS1a is larger than that of the second area AS1b Of the first opening 118h (or a dummy The area of the memory tandem structure 118). In this embodiment, the unit area UA, for example, takes the center point C1 of the predetermined position 120' of the contact structure as the center point, and extends in the second direction (for example, the X direction) and the third direction (Y direction) to two adjacent contacts. A rectangular area enclosed by the center points C2~C5 between the predetermined positions 120' of the structure. In other words, from the top view of FIG. 3A, under the same unit area UA, the area of the first opening 118hp (or the dummy memory serial structure 118p) of the first area AS1a is two first openings 118hp (Or the total area of the dummy memory serial structure 118p) (1/2*4=2); the area of the first opening 118hp of the second area AS1b (or the dummy memory serial structure 118p) is also 2 The total area (1/2*4=2) of the first opening 118hp (or the dummy memory serial structure 118p). From the top view of Figure 4A, under the same unit area UA, the area of the first opening 118h (or the dummy memory serial structure 118) of the first area AS1a is 4 first openings 118h (or Is the total area of the dummy memory string structure 118; the area of the first opening 118h (or the dummy memory string structure 118) of the second area AS1b is 2 first openings 118h (or the dummy memory string The total area (1/2*4=2) of the column structure 118). In this embodiment, under the same unit area UA, the area of the first opening 118h in the first area AS1a is twice the area of the first opening 118h in the second area AS1b, but the present invention is not limited to this. In this embodiment, each first opening 118h has the same area, but the present invention is not limited to this.

According to some embodiments of the present invention, under the same unit area UA, the number of first openings 118h (or the dummy memory serial structure 118) in the first area AS1a is greater than the number of first openings 118h in the second area AS1b ( Or the number of dummy memory serial structures 118). For example, in the first area AS1a and the second area of the semiconductor device 100P In AS1b, the multiple first openings 118hp (or the dummy memory serial structure 118p) are arranged in a row along the third direction (for example, the Y direction) (for example, a row of the first openings 118hp of R1 (or is The dummy memory serial structure 118p)) is arranged in multiple rows along the second direction (for example, the X direction), and two adjacent rows of contact structures arranged along the third direction (for example, the Y direction) are arranged at the predetermined position 120 A row of first openings 118hp (or a dummy memory serial structure 118p) arranged along the third direction (for example, the Y direction) is arranged between them. In the semiconductor device 100, the plurality of first openings 118h (or the dummy memory serial structure 118) are arranged in a row (for example, a row of the first openings 118h of R2) along the third direction (for example, the Y direction) (Or the dummy memory serial structure 118)), and arranged in multiple rows along the second direction (for example, the X direction). In the first area AS1a, two adjacent rows of contact structures arranged along the third direction (for example, Y direction) are arranged between predetermined positions 120', and 2 rows are arranged along the third direction (for example, Y direction). The first opening 118h (or the dummy memory serial structure 118). In the second area AS1b, two adjacent rows of contact structures arranged along the third direction (for example, the Y direction) are arranged with one row arranged along the third direction (for example, the Y direction) between the predetermined positions 120' The first opening 118h (or the dummy memory serial structure 118). In this embodiment, under the same unit area UA, the number of first openings 118h (or dummy memory serial structure 118) in the first area AS1a is equal to the number of first openings 118h (or is The number of the dummy memory serial structure 118) is twice, but the present invention is not limited to this.

In this embodiment, the first opening 118h (or the dummy memory serial structure 118) is provided on the substrate 110 along a second direction (for example, the X direction), and the second direction is perpendicular to the first direction. In the second direction, the center point Ca1 of the first opening 118h (or the dummy memory serial structure 118) provided in the first area AS1a is the same as the center point Ca1 provided in the second area AS1b. The center point Cb1 of the first opening 118h (or the dummy memory serial structure 118) is aligned.

According to some embodiments of the present invention, in a top view, when the area ratio of the total area of the first opening 118h (or the dummy memory serial structure 118) to the total area of the step area AS is equal to or greater than 8%, This can effectively release the gas that is unfavorable for the growth of the epitaxial growth layer, so that the epitaxial growth layer 1181 in the first region AS1a of the present invention can still have a good growth condition. For example, in the semiconductor device 100P of the comparative example, from the perspective of the top view, the area ratio of the total area of the first opening 118hp (or the dummy memory serial structure 118p) to the total area of the step region AS1 is equal to 5.44 %. In the semiconductor device 100A of an embodiment of the present invention, from the perspective of the top view, the area ratio of the total area of the first opening 118h (or the dummy memory serial structure 118) to the total area of the step area AS is equal to 8.99%.

FIG. 5 is a graph showing the formation height of the epitaxial growth layer of the dummy memory tandem structure of the semiconductor device 100A according to an embodiment of the present invention and the semiconductor device 100p of the comparative example.

FIG. 5 is the result of measuring the epitaxial growth layers of the dummy memory tandem structure at corresponding positions in the semiconductor device 100A and the semiconductor device 100P, respectively. The height of the epitaxial growth layer is, for example, defined as the vertical height between the upper surface 110a of the substrate 110 and the top surface of the epitaxial growth layer. The X coordinate represents the serial structure number of the dummy memory, where S1~S9 represent the serial number of the dummy memory serial structure of the first area AS1a of the main body AS1, and D0~D10 represent the serial structure of the dummy memory of the dummy part AS2. Numbering.

Generally speaking, when the height of the epitaxial growth layer is equal to or greater than 800 Angstroms (Å), good electrical effects can be achieved. It can be seen from the results in Fig. 5 that the semiconductor device 100P In the first area AS1a, the height of the epitaxial growth layer of at least the dummy memory tandem structure numbered S5 and S1 is less than 800 angstroms. In the first region AS1a of the semiconductor device 100A according to an embodiment of the present invention, the height of the epitaxial growth layer 1181 of all the dummy memory tandem structures 118 is greater than 800 angstroms.

FIG. 6A shows the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device 100P of the comparative example. FIG. 6B shows the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device 100A according to an embodiment of the present invention.

Please refer to FIGS. 6A and 6B at the same time. If the height of the epitaxial growth layer of the dummy memory tandem structure is less than 200 angstroms, it is marked with a black dot as an abnormal dummy memory tandem structure epitaxial growth layer. Fig. 6A shows that the semiconductor device 100P of the comparative example has an epitaxial growth layer with some abnormal dummy memory series structure; Fig. 6B shows that the semiconductor device 100A of an embodiment of the present invention does not have abnormal dummy memory series Structure of epitaxial growth layer.

It can be seen from the results of FIGS. 5-6B that, compared with the semiconductor device 100P of the comparative example, the first opening 118h (or the dummy memory serial structure) of the first region AS1a of the semiconductor device 100A of an embodiment of the present invention The area of 118) is larger than the area of the first opening 118h (or the dummy memory tandem structure 118) of the second region AS1b (under the same unit area UA), which can effectively eliminate the unfavorable epitaxial growth layer growth in the substrate 110 Even the epitaxial growth layer 1181 of the dummy memory series structure 118 in the first region AS1a can have better growth conditions, thereby avoiding the above-mentioned short circuit and leakage current problems.

FIG. 7 illustrates the semiconductor device 200 according to another embodiment of the present invention Partial top view.

Referring to Figure 7, in the same unit area UA, the area of the first opening 218h (or the dummy memory serial structure 218) of the first area AS1a is larger than the area of the first opening 218h (or Is the area of the dummy memory serial structure 218). The semiconductor device 200 is similar to the semiconductor device 100A, except that the pattern of the first opening 218h (or the dummy memory serial structure 218) of the first area AS1a (as shown in FIG. 7) is different from that of the first area The pattern of the first opening 118h (or the dummy memory serial structure 118) of the AS1a (as shown in FIG. 4A). Furthermore, the first opening 218h (or the dummy memory serial structure 218) is provided on the substrate 110 along the second direction (for example, the X direction) and the third direction (for example, the Y direction). The first direction, The second direction and the third direction are, for example, perpendicular to each other. In the second direction, the center point Ca2 of the first opening 218h (or the dummy memory serial structure 218) provided in the first area AS1a is the same as the first opening 218h (or the dummy memory serial structure 218) provided in the second area AS1b. The center point Cb2 of the body tandem structure 218) is staggered.

In the semiconductor devices 100A and 200, the center points Ca1 and Ca2 of the first openings 118h and 218h (or the dummy memory serial structures 118 and 218) of the first area AS1a are aligned with each other along the second direction, but the present invention It is not limited to this. In other embodiments, the center points Ca1 and Ca2 of the first openings 118h and 218h (or the dummy memory serial structures 118 and 218) of the first area AS1a in two adjacent rows are at the The two directions can be staggered from each other.

The number and arrangement of the first openings 118h and 218h (or the dummy memory serial structures 118 and 218) of the present invention can be adjusted arbitrarily, as long as the first opening 118h of the first area AS1a is in the same unit area UA And 218h (or dummy memory serial structures 118 and 218) are larger than the first opening 118h of the second area AS1b and The area of 218h (or the dummy memory serial structures 118 and 218) is the scope of the invention.

FIG. 8A shows a partial top view of a semiconductor device 300 according to another embodiment of the present invention. Fig. 8B is a cross-sectional view taken along the line A-A' in Fig. 8A.

Please refer to FIGS. 8A and 8B at the same time. In the same unit area UA, the area of the first opening 318h (or the dummy memory serial structure 318) of the first area AS1a is larger than the first opening of the second area AS1b The area of 318h (or the dummy memory serial structure 318). The semiconductor device 300 is similar to the semiconductor device 100A, except that the pattern of the first opening 318h (or the dummy memory serial structure 318) of the first area AS1a (as shown in FIG. 8A) is different from that of the first area The pattern of the first opening 118h (or the dummy memory serial structure 118) of the AS1a (as shown in FIG. 4A). Furthermore, the diameter D1 of the first opening 318h (or the dummy memory serial structure 318) of the first area AS1a is larger than the first opening 318h (or the dummy memory serial structure 318) of the second area AS1b. Diameter D2. In one embodiment, the diameter D1 of the first opening 318h (or the dummy memory serial structure 318) of the first area AS1a is larger than that of the first opening 318h (or the dummy memory serial structure 318) of the second area AS1b. The diameter D2 of) is more than 10%. For example, when the diameter D2 of the first opening 318h (or the dummy memory serial structure 318) of the second area AS1b is 80 nm, the first opening 318h (or the dummy memory serial structure 318) of the first area AS1a The diameter D1 can be any value above 88nm, such as 90nm or 100nm.

In some embodiments, the first opening 318h (or the dummy memory serial structure 318) is provided on the substrate 110 along the second direction (for example, the X direction) and the third direction (for example, the Y direction). The direction, the second direction and the third direction may be perpendicular to each other. In the first In the two directions, the center point Ca3 of the first opening 318h (or the dummy memory string structure 318) provided in the first area AS1a is the same as the first opening 318h (or the dummy memory string structure) provided in the second area AS1b. The center point Cb3 of the column structure 318) is aligned.

FIG. 9A shows the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device 100P of the comparative example. FIG. 9B illustrates the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device 300 according to an embodiment of the present invention. FIG. 9C shows the scanning result of the epitaxial growth layer of the abnormal dummy memory tandem structure of the semiconductor device 300 according to another embodiment of the present invention.

In the comparative example shown in FIG. 9A, the diameter of the first opening 118hp of the first region AS1a is 80 nm. In an embodiment of the semiconductor device 300 in FIG. 9B, the diameter of the first opening 318h of the first region AS1a is 90 nm. In another embodiment of the semiconductor device 300 in FIG. 9C, the diameter of the first opening 318h of the first region AS1a is 100 nm.

Please also refer to Figures 9A to 9C. If the height of the epitaxial growth layer of the dummy memory tandem structure is less than 200 angstroms, it is marked with a black dot as an abnormal dummy memory tandem structure epitaxial growth layer. Figure 9A shows that the semiconductor device 100P of the comparative example has some abnormal dummy memory tandem structure epitaxial growth layers; Figures 9B and 9C show that the semiconductor device 300 of some embodiments of the present invention does not have abnormal dummy memory The epitaxial growth layer of the tandem structure.

FIG. 10 shows a partial top view of a semiconductor device 400 according to another embodiment of the present invention.

Please refer to FIG. 10, in the same unit area UA, the area of the first opening 418h (or the dummy memory serial structure 418) of the first area AS1a is large The area of the first opening 418h (or the dummy memory serial structure 418) in the second area AS1b. The semiconductor device 400 is similar to the semiconductor device 300, except that the pattern of the first opening 418h (or the dummy memory serial structure 418) of the first region AS1a (as shown in FIG. 10) is different from that of the first region. The pattern of the first opening 318h (or the dummy memory serial structure 318) of the AS1a (as shown in FIG. 8A). Furthermore, the first opening 418h (or the dummy memory serial structure 418) is provided on the substrate 110 along the second direction (for example, the X direction) and the third direction (for example, the Y direction). The first direction, The second direction and the third direction are, for example, perpendicular to each other. In the second direction, the center point Ca4 of the first opening 418h (or the dummy memory serial structure 418) provided in the first area AS1a is the same as the first opening 418h (or the dummy memory serial structure 418) provided in the second area AS1b. The center point Cb4 of the body tandem structure 418) is staggered.

The number and arrangement of the first openings 318h and 418h (or the dummy memory serial structures 318 and 418) of the present invention can be adjusted arbitrarily, as long as the first opening 318h of the first area AS1a is in the same unit area UA And 418h (or the dummy memory serial structures 318 and 418) are larger than the area of the first openings 318h and 418h (or the dummy memory serial structures 318 and 418) of the second area AS1b, which is the invention The scope of the desired protection.

According to some embodiments of the present invention, in the same unit area UA, it is only necessary to increase the area of the first opening 118h (or the dummy memory serial structure 118) of the first area AS1a (for example, by increasing the first area The number or diameter of the first opening 118h of AS1a can be used to prevent the epitaxial growth layer from being skewed or insufficient in height. There is no need to increase the first opening 118h (or dummy memory) of the first area AS1a and the second area AS1b at the same time. Body string The area of the column structure 118), so the cost can be greatly saved.

The invention provides a semiconductor device and a manufacturing method thereof. According to an embodiment, a semiconductor device includes a substrate, a stack structure disposed on the substrate, and a plurality of dummy memory serial structures. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The dummy memory serial structure is disposed in a step area of the semiconductor device and passes through the stack structure along the first direction, wherein the step area includes a body portion, and the body portion includes a first area and a second area adjacent to each other . In the first area, the number of conductive layers corresponding to the dummy memory serial structure is between 1-10; in the second area, the number of conductive layers corresponding to the dummy memory serial structure is greater than 10. In a same unit area, the area of the dummy memory serial structure in the first area is larger than the area of the dummy memory serial structure in the second area.

Compared with the comparative example in which the area of the dummy memory string structure in the first region is not larger than the area (in the same unit area) of the dummy memory string structure in the second region, the semiconductor device of the present invention The area of the dummy memory tandem structure in the first region is larger than the area of the dummy memory tandem structure in the second region (in the same unit area), which can more effectively release the gas that is unfavorable to the epitaxial growth layer. Therefore, the epitaxial growth layer of the dummy memory tandem structure in the first region of this case can have better growth conditions, which can prevent the epitaxial growth layer from being skewed or insufficient in height, thereby avoiding electrical properties such as short circuits and leakage currents. problem.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

100: Semiconductor device

116: Memory serial structure

116h: array opening

118: Dummy memory serial structure

118h: first opening

120: contact structure

A,A’,B,B’: the end of the section line

AR: Array area

AS: Step area

AS1: Main unit

AS1a: Zone 1

AS1b: Zone 2

AS2: Dummy part

Claims (10)

A semiconductor device includes: a substrate and a stack structure arranged on the substrate, the stack structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; and a plurality of dummy memory series The structure is arranged in a step area of the semiconductor device and passes through the stack structure along the first direction, wherein the step area includes a body portion, and the body portion includes an adjacent first area and a second area In the first area, the number of conductive layers corresponding to the dummy memory serial structures is between 1 and 10; in the second area, the dummy memory serial structures correspond to The number of the conductive layers is greater than 10, wherein in a top view, in a same unit area, the area of the dummy memory serial structures in the first region is greater than the area of the dummy memory tandem structures in the second region The area of the dummy memory serial structure. The semiconductor device according to claim 1, wherein in the same unit area, the number of the dummy memory serial structures in the first region is greater than the number of the dummy memory serial structures in the second region Quantity. The semiconductor device according to claim 2, wherein the dummy memory serial structures are arranged on the substrate along a second direction, the second direction being perpendicular to the first direction, In the second direction, the central points of the dummy memory serial structures arranged in the first area are aligned with the central points of the dummy memory serial structures arranged in the second area. The semiconductor device according to claim 2, wherein the dummy memory serial structures are arranged on the substrate along a second direction, the second direction is perpendicular to the first direction, and in the second direction, the The central points of the dummy memory serial structures in the first area are staggered from the central points of the dummy memory serial structures arranged in the second area. The semiconductor device according to claim 1, wherein a diameter of each of the dummy memory serial structures in the first region is larger than a diameter of each of the dummy memory serial structures in the second region. The semiconductor device according to claim 5, wherein the diameter of each of the dummy memory serial structures in the first region is more than 10% greater than the diameter of each of the dummy memory serial structures in the second region. The semiconductor device according to claim 5, wherein the dummy memory serial structures are arranged on the substrate along a second direction, the second direction is perpendicular to the first direction, and in the second direction, the The center points of the dummy memory serial structures in the first area are aligned with the center points of the dummy memory serial structures disposed in the second area. The semiconductor device according to claim 5, wherein the dummy memory serial structures are arranged on the substrate along a second direction, the second direction is perpendicular to the first direction, and in the second direction, the The central points of the dummy memory serial structures in the first area are staggered from the central points of the dummy memory serial structures arranged in the second area. The semiconductor device according to claim 1, wherein in the top view, an area ratio of the total area of the dummy memory string structures to the total area of the stepped region is equal to or greater than 8%. A method for manufacturing a semiconductor device includes: providing a substrate and a stacked structure disposed on the substrate, the stacked structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; and forming a plurality of The first opening is in a step area of the semiconductor device, the first openings pass through the stack structure along the first direction, wherein the step area includes a body portion, and the body portion includes an adjacent first Area and a second area. In the first area, the number of the conductive layers corresponding to the first openings is between 1-10; in the second area, the number of the first openings corresponds to The number of the conductive layers is greater than 10. In a top view, in a same unit area, the area of the first openings in the first region is larger than that of the first openings in the second region area.

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