TWI729493B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a substrate, data lines, gate lines, pixel structures, transfer lines and an electrostatic protection circuit. The data lines are arranged in a first direction. The gate lines are arranged in a second direction. The transfer lines are arranged in the first direction and electrically connected to the gate lines respectively. The electrostatic protection circuit is disposed between an edge of the substrate and the pixel structures. The electrostatic protection circuit includes electrostatic protection components, data ground lines and at least one gate ground line. The electrostatic protection elements include first electrostatic protection elements and second electrostatic protection elements. The first electrostatic protection elements are electrically connected between the data lines and the data ground lines. The second electrostatic protection elements are electrically connected between the transfer lines and the at least one gate ground. The at least one gate ground line and the data ground lines are arranged in the second direction and spaced apart from each other.

Description

Pixel array substrate

The present invention relates to a pixel array substrate.

With the popularization of multimedia applications, displays with high resolution and large visual range have become the mainstream of technological development. As the resolution of the display increases, the number of wires located in the peripheral area of the display also increases. In addition, in order to prevent the display from being damaged by static electricity, an electrostatic protection circuit must be provided around the pixel array substrate of the display. Therefore, a certain space needs to be reserved around the conventional pixel array substrate to accommodate a large number of wires and various static electricity protection circuits, so that the frame of the display cannot be further reduced.

The invention provides a pixel array substrate with good electrostatic protection effect.

The pixel array substrate of the present invention includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures, a plurality of transfer wires and an electrostatic protection circuit. A plurality of data lines are arranged on the substrate and arranged in the first direction. A plurality of gate lines are arranged on the substrate and arranged in the second direction. The first direction is staggered with the second direction. A plurality of pixel structures are arranged on the substrate. Each pixel structure is electrically connected to a data line and a gate line. A plurality of transfer wires are arranged on the substrate and arranged in the first direction. The multiple transfer wires are electrically connected to the multiple gate wires respectively. The electrostatic protection circuit is arranged between an edge of the substrate and the plurality of pixel structures. The electrostatic protection circuit includes a plurality of electrostatic protection components, a plurality of data ground wires and at least one gate ground wire. The plurality of electrostatic protection elements includes a plurality of first electrostatic protection elements and a plurality of second electrostatic protection elements. The plurality of first electrostatic protection components are electrically connected between the plurality of data lines and the plurality of data grounding lines. The plurality of second electrostatic protection components are electrically connected between the plurality of transfer wires and at least one gate ground wire. At least one gate ground wire and a plurality of data ground wires are arranged in the second direction and separated from each other.

In an embodiment of the present invention, the above-mentioned plurality of electrostatic protection components are arranged on opposite sides of the plurality of data grounding lines and at least one gate grounding line.

In an embodiment of the present invention, each of the above-mentioned electrostatic protection elements includes a thin film transistor, the thin film transistor has a first end, a second end, a control end and a semiconductor pattern, the first end and the second end The terminals are electrically connected to two different regions of the semiconductor pattern, and the first terminal is electrically connected to the control terminal; the thin film transistor of a first electrostatic protection element has a channel width-to-length ratio W1/L1, and a second electrostatic protection element The thin film transistor has a channel width to length ratio W2/L2, and (W2/L2)>(W1/L1).

In an embodiment of the present invention, the above-mentioned plurality of gate lines includes a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines, and the plurality of transfer lines include electrically connected to a plurality of odd-numbered gate lines A plurality of first transfer wires and a plurality of second transfer wires electrically connected to a plurality of even-numbered gate lines. The at least one gate ground wire of the electrostatic protection circuit includes a first gate ground wire and a second gate ground wire. A part of the plurality of second electrostatic protection elements is electrically connected between the plurality of first transfer wires and the first gate ground wire. The other part of the plurality of second electrostatic protection elements is electrically connected between the plurality of second transfer wires and the second gate ground wire. The first gate ground line, the second gate ground line and the multiple data ground lines are arranged in the second direction and separated from each other.

In an embodiment of the present invention, the aforementioned pixel array substrate further includes a pad set. The pad set includes a plurality of pads, wherein the plurality of pads are arranged along the edge of the substrate and are respectively electrically connected to a plurality of data lines and a plurality of transfer lines, and at least one gate ground line, a plurality of data ground lines, and The pad groups are arranged in the second direction.

In an embodiment of the present invention, the aforementioned pixel array substrate further includes a fan-out wiring group. The fan-out wiring set includes multiple fan-out wirings, of which multiple fan-out wirings are respectively electrically connected to multiple data lines and multiple transition wires, and at least one gate ground wire, multiple data ground wires, and fan-out wiring set Arrange in the second direction.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the invention.

2 shows the layout of the data line DL, the transfer line gl, the electrostatic protection elements 120dl, 120gl, the data ground line CLdl, and the gate ground line CLgl of the pixel array substrate 100 according to an embodiment of the present invention.

Figure 1 uses circuit symbols to represent the data line DL, the transfer line gl, the electrostatic protection components 120dl, 120gl, the data ground line CLdl, and the gate ground line CLgl. The actual layout can refer to Figure 2.

1 and FIG. 2, the pixel array substrate 100 includes a substrate 110. The substrate 110 is mainly used to carry elements of the pixel array substrate 100. In this embodiment, the material of the substrate 110 may be glass, quartz, organic polymers, or opaque/reflective materials (for example, wafers, ceramics, or other applicable materials), or other applicable materials. material.

The pixel array substrate 100 includes a plurality of data lines DL and a plurality of gate lines GL. A plurality of data lines DL are disposed on the substrate 110 and arranged in the first direction x. A plurality of gate lines GL are disposed on the substrate 110 and arranged in the second direction y. The first direction x is staggered with the second direction y. For example, in this embodiment, the first direction x and the second direction y may be substantially perpendicular, but the invention is not limited thereto.

For example, in this embodiment, the gate line GL can selectively belong to the first metal layer, and the data line DL can selectively belong to the second metal layer, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the gate line GL and the data line DL are made of metal materials. However, the present invention is not limited to this. According to other embodiments, the gate line GL and the data line DL may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and oxynitrides of metal materials. , Or stacked layers of metal materials and other conductive materials.

The pixel array substrate 100 further includes a plurality of pixel structures PX. A plurality of pixel structures PX are disposed on the substrate 110. Each pixel structure PX is electrically connected to a corresponding one A data line DL and a corresponding gate line GL. Specifically, in this embodiment, each pixel structure PX may include a thin film transistor (not shown) and a pixel electrode (not shown), wherein the first end of the thin film transistor is electrically connected to the data line DL, the control terminal of the thin film transistor is electrically connected to the gate line GL, and the second terminal of the thin film transistor is electrically connected to the pixel electrode.

The multiple pixel structures PX are arranged in multiple pixel rows. The multiple pixel structures PX in each pixel row are arranged in the extending direction (for example, the second direction y) of the data line DL. In this embodiment, two adjacent pixel structures PX in the same pixel row can be electrically connected to the two data lines DL located on the left and right sides of the pixel row, and a plurality of the adjacent two pixel structures PX Thin film transistors can be turned on at the same time. In other words, in this embodiment, the multiple pixel structure PX may adopt a 2DhG (two data lines and half gate line) architecture. However, the present invention is not limited to this. According to other embodiments, the multiple pixel structures PX may also adopt 2D1G (two data lines and one gate line), 1D1G (one data line and one gate line) or other types of architectures.

The pixel array substrate 100 includes a plurality of transfer wires gl. A plurality of transfer wires gl is disposed on the substrate 110 and arranged in the first direction x. In other words, the multiple transfer lines gl and the multiple data lines DL are arranged in the same direction. The plurality of transfer lines gl are electrically connected to the plurality of gate lines GL, respectively. For example, in this embodiment, the gate line GL may belong to the first metal layer, the transfer line gl may belong to the second metal layer, and the insulating layer (not shown) is disposed on the first metal layer and the second metal layer. In between, and each transfer line gl can be electrically connected to a corresponding gate line GL through a contact window (not shown) of the insulating layer, but the present invention is not limited to this.

The pixel array substrate 100 further includes an electrostatic protection circuit ESDC. The electrostatic protection circuit ESDC is disposed between an edge 110a of the substrate 110 and the pixel structures PX. In other words, the electrostatic protection circuit ESDC is disposed between an edge 110 a of the substrate 110 and the active area (AA) of the pixel array substrate 100.

In this embodiment, the pixel array substrate 100 further includes a pad group G140. The pad group G140 includes a plurality of pads 140. The plurality of pads 140 are arranged along the edge 110a of the substrate 110 and are electrically connected to the plurality of pads. Data line DL and multiple transfer lines gl. The pixel array substrate 100 further includes a fan-out wiring group G130. The fan-out wiring group G130 includes a plurality of fan-out wirings 130, wherein the plurality of fan-out wirings 130 are electrically connected to the data lines DL and the transfer lines gl, respectively.

Specifically, in this embodiment, a plurality of data lines DL and a plurality of transfer wires gl are electrically connected to the electrostatic protection elements 120d1, 120gl of the electrostatic protection circuit ESDC, and the electrostatic protection elements 120d1, 120gl, of the electrostatic protection circuit ESDC A plurality of data lines DL and a plurality of transfer lines gl are electrically connected to a plurality of fan-out wires 130, a plurality of fan-out wires 130 are electrically connected to a plurality of pads 140, and a plurality of pads 140 are electrically connected to drive The driving element 150 of a plurality of pixel structures PX.

For example, in this embodiment, the driving element 150 may include a chip, and the chip may be bonded to the pixel array substrate 100 by a chip-on-film bonding process (COF). However, the present invention is not limited to this. In other embodiments, the chip may also be processed by a chip-on-glass bonding process (Chip On Glass; COG), a chip-on-board bonding process (Chip On Board, COB), Tape Automated Bonding (TAB) or other methods are bonded to the pixel array substrate 100.

The electrostatic protection circuit ESDC includes a plurality of electrostatic protection elements 120dl, 120gl, a plurality of data ground lines CLdl and at least one gate ground line CLgl. The plurality of static electricity protection elements 120dl and 120gl includes a plurality of static electricity protection elements 120dl and a plurality of static electricity protection elements 120gl. The electrostatic protection element 120dl is electrically connected between the data line DL and the data ground line CLdl. The electrostatic protection element 120gl is electrically connected between the transfer line gl and the gate ground line CLgl.

For example, in this embodiment, the plurality of pixel structures PX includes a pixel structure PXR, a pixel structure PXG, and a pixel structure PXB for displaying a first color, a second color, and a third color, respectively. The data line DL includes a data line DLR, a data line DLG, and a data line DLB that are electrically connected to the pixel structure PXR, the pixel structure PXG, and the pixel structure PXB, respectively. The multiple data ground lines CLdl include a data ground line CLdlr and a data ground. Line CLdlg and data ground line CLdlb, a plurality of static electricity protection elements 120dlr are electrically connected between a plurality of data lines DLR and a data ground line CLdlr, and a plurality of static electricity protection elements 120dlg are electrically connected to a plurality of data lines DLG and a data ground line Between CLdlg, a plurality of static electricity protection elements 120dlb are electrically connected between a plurality of data lines DLB and a data ground line CLdlb. In this embodiment, the first color, the second color, and the third color are, for example, red, green, and blue, but the invention is not limited thereto.

For example, in this embodiment, each ESD protection element 120d1, 120gl includes a plurality of thin film transistors T1, T2, and each thin film transistor T1, T2 has a first terminal T1a, T2a, and a second terminal T1b, T2b. , The control terminals T1c, T2c and the semiconductor patterns T1d, T2d, wherein the first terminals T1a, T2a and the second terminals T1b, T2b are electrically connected to two different regions of the semiconductor patterns T1d, T2d, and the first terminals T1a, T2a are electrically connected Sexually connected to the control terminals T1c and T2c.

In this embodiment, the plurality of thin film transistors T1 and T2 of each ESD protection element 120dl, 120gl includes a thin film transistor T1 and a thin film transistor T2, wherein the first terminal T1a and the control terminal T1c of the thin film transistor T1 are electrically conductive Connected to the second terminal T2b of the thin film transistor T2, and the first terminal T2a and the control terminal T2c of the thin film transistor T2 are electrically connected to the second terminal T1b of the thin film transistor T1. In short, in this embodiment, each static electricity protection element 120dl, 120gl includes a pair of thin film transistors connected in a back-to-back manner, and each static electricity protection element 120dl, 120gl may be a diode type. However, the present invention is not limited to this. In other embodiments, the electrostatic protection elements 120dl, 120gl may also be of other types.

In this embodiment, a plurality of static electricity protection elements 120dl, 120gl may be disposed on opposite sides of the plurality of data ground lines CLdl and gate ground lines CLgl. That is, a part of the plurality of static electricity protection elements 120dl, 120gl may be arranged between the plurality of pixel structures PX and the gate ground line CLgl, and another part of the plurality of static electricity protection elements 120dl, 120gl may be arranged on the gate ground. Between the line CLgl and the edge 110a of the substrate 110. However, the present invention is not limited to this. In other embodiments, a plurality of static electricity protection elements 120dl, 120gl may also be arranged on a single side of a plurality of data ground lines CLdl and gate ground lines CLgl.

It should be noted that the electrostatic protection circuit ESDC is disposed between an edge 110a of the substrate 110 and the pixel structures PX. In this embodiment, the gate ground line CLgl, the data ground line CLdlr, the data ground line CLdlg and the data ground line CLdlb, the fan-out wiring group G130 and the pad group G140 of the electrostatic protection circuit ESDC are arranged in the second direction y And it is located between a plurality of pixel structures PX and an edge 110a of the substrate 110. That is, the plurality of fan-out traces 130, the plurality of pads 140, and the electrostatic protection circuit ESDC that are electrically connected to the data line DL and the gate line GL are arranged on a single side of the active area of the pixel array substrate 100, so that The distance between the other edge 110b of the substrate 110 and the active area can be reduced to a very small, or even zero, so as to realize a display with a narrow frame.

More importantly, at least one gate ground line CLgl and a plurality of data ground lines CLdl of the electrostatic protection circuit ESDC are arranged in the second direction y and separated from each other. The gate line GL (or transfer line gl) and the data line DL used to carry different signals are protected against static electricity through the electrostatic protection element 120dl and the gate ground line CLgl, the electrostatic protection element 120gl and the data ground line CLdl respectively. the goal of. In this way, not only a narrow frame can be realized, but also the antistatic ability of the pixel array substrate 100 can be further improved.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 3 is a schematic top view of a pixel array substrate 100A according to another embodiment of the invention.

4 shows the layout of the data line DL, the transfer line gl, the electrostatic protection elements 120dl, 120gl, the data ground line CLdl, and the gate ground line CLgl of the pixel array substrate 100A according to another embodiment of the present invention.

FIG. 3 uses circuit symbols to represent the data line DL, the transfer line gl, the electrostatic protection components 120dl, 120gl, the data ground line CLdl and the gate ground line CLgl, and the actual layout (layout) can refer to FIG. 4.

1 and 3, the pixel array substrate 100A of this embodiment is similar to the aforementioned pixel array substrate 100. The difference between the two is: in the embodiment of FIG. 3, all the pixel structures in the same pixel column PX is electrically connected to the same data line DL, and multiple pixel structures PX in the same pixel row are electrically connected to multiple gate lines GL, respectively. In other words, in the embodiment of FIG. 3, the multiple pixel structure PX adopts a 1D1G (one data line and one gate line) architecture.

2 and 4, in addition, in the aforementioned pixel array substrate 100, each thin film transistor T1, T2 of each electrostatic protection element 120dl, 120gl may have the same channel width to length ratio. However, in the pixel array substrate 100A of this embodiment, the static electricity protection elements 120dl and 120gl may have different channel width to length ratios.

3 and 4, specifically, in this embodiment, each thin film transistor T1, T2 of the electrostatic protection element 120dl electrically connected between the data line DL and the data ground line CLdl has a channel width W1 and a channel length L1, the channel width-to-length ratio of each thin film transistor T1 and T2 of the electrostatic protection element 120dl is W1/L1; the electrostatic protection element is electrically connected between the patch cord gl and the gate ground line CLgl Each thin film transistor T1 and T2 of 120gl has a channel width W2 and a channel length L2. The ratio of the channel width to length of each thin film transistor T1 and T2 of the electrostatic protection element 120gl is W2/L2; in particular, (W2/ L2)>(W1/L1).

That is to say, in this embodiment, considering that the signal amplitude of the transfer line gl (or gate line GL) is different from the signal amplitude of the data line DL, it can be compared with the transfer line gl (or gate line GL). GL) The width-to-length ratio W2/L2 of the electrical connection of the electrostatic protection component 120gl is designed to be smaller to achieve the effect of grading protection.

FIG. 5 is a schematic top view of a pixel array substrate 100B according to another embodiment of the present invention.

Fig. 5 is a circuit symbol representing the data line DL, the transfer line gl, the electrostatic protection components 120dl, 120gl, the data ground line CLdl and the gate ground line CLgl. The actual layout is similar to the embodiment of Fig. 4, here It will no longer be shown.

The pixel array substrate 100B of FIG. 5 is similar to the pixel array substrate 100A of FIG. 3. The difference between the two is: in the embodiment of FIG. 3, all the second electrostatic protection elements 120gl are electrically connected to the same gate. Ground line CLgl; but in the embodiment of FIG. 5, the plurality of electrostatic protection elements 120gl are electrically connected to a plurality of gate ground lines CLgl spaced apart from each other.

5, specifically, in this embodiment, the multiple gate lines GL include multiple odd-numbered gate lines GL1 and multiple even-numbered gate lines GL2, and the multiple transition lines gl include electrical connections Multiple patch cords gl1 to odd-numbered gate lines GL1 and multiple patch cords gl2 electrically connected to multiple even-numbered gate lines GL2, at least one gate ground line CLgl of the electrostatic protection circuit ESDC includes gate ground Line CLgl1 and gate ground line CLgl2, a part of the plurality of electrostatic protection elements 120gl is electrically connected between the transfer line gl1 and the gate ground line CLgl1, and another part of the plurality of static protection elements 120gl is electrically connected to the transfer line Between gl2 and the gate ground line CLgl2, the gate ground line CLgl1, the gate ground line CLgl2, the data ground line CLdlr, the data ground line CLdlg, and the data ground line CLdlb are arranged in the second direction y and separated from each other.

100, 100A, 100B: pixel array substrate 110: substrate 110a, 110b: edge 120dl, 120dlr, 120dlg, 120dlb, 120gl: electrostatic protection components 130: fan out routing 140: pad 150: drive element CLdl, CLdlr, CLdlg, CLdlb: data ground wire CLgl, CLgl1, CLgl2: gate ground wire DL, DLR, DLG, DLB: data line ESDC: Electrostatic protection circuit GL, GL1, GL2: gate line G130: Fan-out wiring group G140: Pad set gl, gl1, gl2: adapter cable L1, L2: channel length PX, PXR, PXG, PXB: pixel structure T1, T2: thin film transistor T1a, T2a: first end T1b, T2b: second end T1c, T2c: control terminal T1d, T2d: semiconductor pattern W1, W2: channel width x: first direction y: second direction

FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the invention. 2 shows the layout of the data line DL, the transfer line gl, the electrostatic protection elements 120dl, 120gl, the data ground line CLdl, and the gate ground line CLgl of the pixel array substrate 100 according to an embodiment of the present invention. FIG. 3 is a schematic top view of a pixel array substrate 100A according to another embodiment of the invention. 4 shows the layout of the data line DL, the transfer line gl, the electrostatic protection elements 120dl, 120gl, the data ground line CLdl, and the gate ground line CLgl of the pixel array substrate 100A according to another embodiment of the present invention. FIG. 5 is a schematic top view of a pixel array substrate 100B according to another embodiment of the present invention.

100: Pixel array substrate

110: substrate

110a, 110b: edge

120dl, 120dlr, 120dlg, 120dlb, 120gl: electrostatic protection components

130: fan out routing

140: pad

150: drive element

CLdl, CLdlr, CLdlg, CLdlb: data ground wire

CLgl: gate ground wire

DL, DLR, DLG, DLB: data line

ESDC: Electrostatic protection circuit

GL: Gate line

G130: Fan-out wiring group

G140: Pad set

gl: adapter cable

PX, PXR, PXG, PXB: pixel structure

x: first direction

y: second direction

Claims (5)

A pixel array substrate includes: a substrate; a plurality of data lines arranged on the substrate and arranged in a first direction; a plurality of gate lines arranged on the substrate and arranged in a second direction Arrangement, wherein the first direction and the second direction are staggered; a plurality of pixel structures are disposed on the substrate, and each of the pixel structures is electrically connected to a data line and a gate line; a plurality of The patch cords are arranged on the substrate and arranged in the first direction, wherein the patch cords are respectively electrically connected to the gate lines; and an electrostatic protection circuit is provided on an edge of the substrate and Between the pixel structures, the electrostatic protection circuit includes: a plurality of electrostatic protection components, including a plurality of first electrostatic protection components and a plurality of second electrostatic protection components; a plurality of data grounding lines, the first electrostatic protection The element is electrically connected between the data lines and the data ground lines; and at least one gate ground line, and the second electrostatic protection elements are electrically connected to the transition lines and the at least one gate ground line Wherein, the at least one gate ground line and the data ground lines are arranged in the second direction and are separated from each other; each of the electrostatic protection components includes a thin film transistor, the thin film transistor having a first Terminal, a second terminal, a control terminal and a semiconductor pattern, the first The terminal and the second terminal are respectively electrically connected to two different regions of the semiconductor pattern, and the first terminal is electrically connected to the control terminal; the thin film transistor of the first electrostatic protection element has a channel width to length ratio W1/L1, the thin film transistor of the second electrostatic protection element has a channel width to length ratio W2/L2, and (W2/L2)<(W1/L1). According to the pixel array substrate described in claim 1, wherein the electrostatic protection components are arranged on opposite sides of the data grounding line and the at least one gate grounding line. For the pixel array substrate described in claim 1, wherein the gate lines include a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines, and the transition lines include electrical connections to the A plurality of first transition wires of odd-numbered gate wires and a plurality of second transition wires that are electrically connected to the even-numbered gate wires, and the at least one gate ground wire of the electrostatic protection circuit includes: a first A gate ground wire, a part of the second electrostatic protection components are electrically connected between the first transfer wires and the first gate ground wire; and a second gate ground wire, the second Another part of the electrostatic protection element is electrically connected between the second transfer wires and the second gate ground wire; wherein, the first gate ground wire, the second gate ground wire and the data ground The lines are arranged in the second direction and spaced apart from each other. The pixel array substrate described in item 1 of the scope of the patent application further includes: a pad set including a plurality of pads, wherein the pads are arranged along the edge of the substrate and are electrically connected to the pads. The data line and the transfer lines, and the at least one gate ground line, the data ground lines and the pad group are arranged in the second direction. For example, the pixel array substrate described in item 1 of the scope of the patent application further includes: a fan-out wiring set, including a plurality of fan-out wirings, wherein the fan-out wirings are electrically connected to the data lines and the switching lines, respectively Wiring, and the at least one gate ground wire, the data ground wires and the fan-out wiring group are arranged in the second direction.

Images