TWI729035B - Transistor with a sub-fin dielectric region under a gate, semiconductor device and process for fabricating the same, and computing device - Google Patents

Abstract

Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

Description

Transistor with sub-fin dielectric region under the gate, semiconductor device, and process and computing device for manufacturing the same

The embodiments of the present disclosure generally relate to semiconductor integrated circuits (ICs), and more specifically to semiconductor ICs with metal oxide semiconductor field-effect transistors (MOSFETs), where the MOSFET has a dielectric material region under the gate region. Sub-fin area.

In order to increase the performance and capacity of integrated circuits (IC), multi-gate MOSFET transistors, such as triple-gate MOSFET transistors, have been implemented. These transistors allow continuous reduction in the feature size of ICs, while providing certain performance advantages over planar transistors. With continued drive to reduce feature size, transistor design may require new semiconductor materials, which can be used alone or in combination with silicon, and may need to include design features to maintain and/or improve IC performance and capacity, because the reduced size contributes to physical boundaries . One measure of the performance of MOSFET transistors includes the ability to have minimal current leakage between the source and drain when the gate is closed. Minimizing current leakage may require design considerations Quantity and material selection considerations.

10‧‧‧Wafer format

11‧‧‧wafer

100‧‧‧Single form

102, 103a, 103b‧‧‧grains

102a‧‧‧Semiconductor substrate

102b‧‧‧Device layer

102c‧‧‧Interconnect layer

104‧‧‧Transistor structure

106‧‧‧grain level interconnect structure

110‧‧‧Solder pad

112‧‧‧Solder Ball

121‧‧‧Packaging substrate

122‧‧‧Circuit board

200‧‧‧Integrated Circuit Assembly

300, 500‧‧‧Multi-Gate Transistor

302‧‧‧Substrate

302.1‧‧‧Substrate fins

304‧‧‧First fin

305‧‧‧Second fin

306‧‧‧third fin

306.1‧‧‧Top surface

306.2, 306.3, 320.4‧‧‧ side

306H‧‧‧Height

306W‧‧‧Width

307‧‧‧Semiconductor fin

308‧‧‧Source

309‧‧‧Source Region

310‧‧‧Dip pole

311‧‧‧Dip pole area

312‧‧‧Shallow groove isolation structure

314‧‧‧Spacer

314.1‧‧‧Under the interior

315‧‧‧Gate area

316‧‧‧Dielectric layer

318‧‧‧Gate electrode

319‧‧‧Open Space

320‧‧‧Dielectric Fin

320.1, 320.2‧‧‧Expansion area

320.3‧‧‧Length

321‧‧‧Subfin Space

322‧‧‧Interlayer Dielectric

323、327‧‧‧Dielectric materials

329‧‧‧Gate electrode material

Sections 330, 340, 350‧‧‧

360‧‧‧source centerline

362‧‧‧Dip pole centerline

400‧‧‧Program

600、700‧‧‧Calculating device

602, 702‧‧‧ motherboard

604, 704‧‧‧ processor

606‧‧‧Communication chip

608、726‧‧‧Shell

610‧‧‧Camera

612, 710‧‧‧chipset

614‧‧‧Dynamic Random Access Memory

616‧‧‧Random access memory

618‧‧‧Read only memory

620‧‧‧Global Positioning System (GPS) device

622‧‧‧Compass

624‧‧‧Power Amplifier

626‧‧‧Graphics Processor

628‧‧‧Touch Screen Controller

630‧‧‧controller

632‧‧‧antenna

634‧‧‧Speaker

636‧‧‧Touch screen display

638‧‧‧Microphone

640‧‧‧Socket

642‧‧‧Micro Electro Mechanical System (MEMS) Sensor

644‧‧‧Battery

706‧‧‧Liquid cooling system components

708‧‧‧Heat exchanger

712‧‧‧Memory

714‧‧‧Expansion slot

716‧‧‧Computer bus interface

718‧‧‧Local Area Network (LAN) Controller

720‧‧‧Port

722‧‧‧Cooling System

724‧‧‧Interface device

The embodiments will be easily understood through the following detailed description in conjunction with the accompanying drawings. For ease of description, similar numbers refer to similar structural elements. The embodiments are described by way of example rather than by being limited to the drawings.

Fig. 1 schematically depicts a top view of an integrated circuit (IC) component according to several embodiments.

Figure 2 schematically depicts a cross-sectional side view of an integrated circuit (IC) component according to several embodiments.

3A to 3E schematically depict selected components of a multi-gate metal oxide semiconductor field effect transistor according to several embodiments.

Fig. 4 schematically depicts the process of manufacturing a multi-gate transistor according to several embodiments.

5A to 5F schematically depict various embodiments of multi-gate transistors at various stages of the process of FIG. 4.

FIG. 6 schematically depicts a computing device with a multi-gate metal oxide semiconductor field effect transistor according to several embodiments. As described in the text, the multi-gate metal oxide semiconductor field effect transistor has a dielectric fin under the gate. Area.

FIG. 7 schematically depicts a computing device with a multi-gate metal oxide semiconductor field effect transistor according to several embodiments. As described in the text, the multi-gate metal oxide semiconductor field effect transistor has a dielectric fin under the gate. Area.

[Content and Implementation of the Invention]

The embodiment of the present disclosure depicts a multi-gate transistor with a dielectric fin region under the gate region, and further depicts the process of manufacturing the multi-gate transistor. Further embodiments depicted include devices and systems with multiple gate transistors disclosed in the text.

In the following description, many specific details are presented in order to provide a thorough understanding of various embodiments. In other situations, well-known semiconductor processes and/or manufacturing techniques are not described in particular in detail, so as not to unnecessarily obscure the embodiments described in the text. In addition, the description of the embodiments in the text may omit certain structures and/or details so as not to confuse the embodiments described in the text.

In the following detailed description, reference is made to the accompanying drawings that form a part of this text, in which like numbers throughout the text refer to similar parts, and which are shown by depicting embodiments that can realize the technical subject of the present disclosure. It should be understood that other embodiments can be utilized and structural or logical changes can be implemented without departing from the scope of the present disclosure. Therefore, the following detailed description does not take the meaning of limitation, and the scope of the embodiment is defined by the application item and its equivalent discussion.

For the purposes of this disclosure, the term "A and/or B" means (A), (B), or (A and B). For the purpose of this disclosure, the term "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A , B and C).

The description can use perspective-based descriptions, such as top/bottom, side, top/bottom, and so on. These descriptions are only used to facilitate discussion, and are not intended to limit the application of the embodiments described in the text to any particular direction.

The description may use the term "in an embodiment" to refer to one or more identical or different embodiments. In addition, as compared to the embodiment of the present disclosure As used, the terms "include", "include", and "have" are synonymous. The term "coupling" can refer to direct connection, indirect connection, or indirect communication.

The terms "coupled to" and "coupled to" and their derivatives can be used in the text. "Coupling" can mean one or more of the following discussions. "Coupling" can mean that two or more components are in direct physical and/or electrical contact. However, "coupled" can also mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between elements that are said to be coupled to each other. The term "directly coupled" can mean that two or more components are in direct contact. By way of example and not limitation, “coupled” may mean that two or more components or devices are coupled by electrical connection on a printed circuit board, such as a motherboard. The electrical connection can provide a direct physical coupling through the electrical connection. By way of example and not limitation, “coupled” may mean that two or more components/devices cooperate and/or interact via one or more network links, such as wired and/or wireless networks. By way of example and not limitation, the computing device may include two or more computing devices, "coupled" via one or more network links.

In various embodiments, the term "the first part is formed, deposited, or disposed on the second part" can mean that the first part is formed, deposited, or disposed on the second part, and at least part of the first part It may be in direct contact (for example, direct physical and/or electrical contact) or indirect contact (for example, having one or more other parts between the first part and the second part) at least part of the second part.

As used in the text, the term "circuit" can refer to part or including dedicated integrated circuits (ASIC), electronic circuits, processors (shared, dedicated, or group), and/or memory (shared, dedicated, or group) ), It executes one or more software or firmware programs, combinational logic circuits, state machines, and/or other suitable components that provide the described functionality.

FIG. 1 schematically depicts a top view of an example die 102 of a wafer form 10 and a single form 100 according to several embodiments. In some embodiments, the die 102 may be one of a plurality of die (eg, die 102, 103a, 103b) of the wafer 11 composed of a semiconductor material, where the semiconductor material is such as silicon or other suitable materials. A plurality of dies can be formed on the surface of the wafer 11. Each die can be a repeating unit of a semiconductor product, which includes one or more transistor components, and/or other device components, which includes a multi-gate transistor with a dielectric fin region under the gate region, as in the text Revealed. The dielectric fin region may be referred to as a dielectric material region or a dielectric material region of a sub-fin region, wherein the sub-fin region may be a region on the semiconductor fin formed on the semiconductor substrate. In some embodiments, the dielectric fin region may be amorphous silicon. In some embodiments, the multi-gate transistor may be a tri-gate transistor. For example, the die 102 may include a circuit with a transistor structure 104 and/or other device structures including a multi-gate transistor with a dielectric fin region under the gate region, as described herein. A multi-gate transistor with a dielectric fin region under the gate region can provide better isolation between the source and drain, compared to a multi-gate transistor without a dielectric fin region under the gate region, resulting in Leakage current reduction and better channel control.

Although for simplicity, the transistor structure 104 is depicted in columns, traversing the substantial part of the die 102 in FIG. 1, it should be understood that in other embodiments, the transistor structure 104 can be configured in any wide range of other suitable configurations and is assembled in the crystal. The particles 102, including, for example, vertical and horizontal parts, have a relatively high The profiler is smaller in size. After the manufacturing process of the semiconductor product embodied in the die is completed, the wafer 11 may undergo a singulation process, where each die (eg, die 102) is separated from each other to provide discrete "chips" of the semiconductor product. The wafer 11 can be any size. In some embodiments, the wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. In other embodiments, the wafer 11 may include other sizes and/or other shapes. According to various embodiments, the transistor structure 104 can be arranged in a wafer format 10 or a single format 100 on a semiconductor substrate. The transistor structure 104 described herein can be incorporated into the die 102 for use in logic or memory, or a combination thereof. In some embodiments, the transistor structure 104 may be a part of a system-on-a-chip (SoC) component.

FIG. 2 schematically depicts a cross-sectional side view of an integrated circuit (IC) assembly 200 according to several embodiments. In some embodiments, the IC component 200 may include one or more dies (hereinafter referred to as “die 102”) that are electrically and/or physically coupled to the package substrate 121. In some embodiments, the packaging substrate 121 may be electrically coupled with the circuit board 122, as can be seen. In some embodiments, the integrated circuit (IC) component 200 may include one or more dies 102, a package substrate 121, and/or a circuit board 122 according to various embodiments. According to the embodiments of the multi-gate transistor described in the text, there is a dielectric fin region under the gate region, and one or more dies 102 can be incorporated. In some embodiments, the dielectric fin region may be, for example, amorphous silicon. In some embodiments, the multi-gate transistor may be a tri-gate transistor. A multi-gate transistor with a dielectric fin region under the gate region can be formed as described and disclosed in the text. Multi-gate transistor with dielectric fin area under the gate area can provide The better isolation between the source and drain leads to a reduction in leakage current and better channel control compared to a multi-gate transistor without a dielectric fin region under the gate region.

Die 102 may represent discrete products manufactured from semiconductor materials (such as silicon) using semiconductor manufacturing technology, such as thin film deposition, lithography, etching, etc., for bonding to form a complementary metal oxide semiconductor (CMOS) device. In some embodiments, the die 102 may include or be a part of a processor, memory, system-on-chip (SoC), or ASIC. In some embodiments, an electrically insulating material such as a molding compound or a filler material (not shown) can encapsulate at least a portion of the die 102 and/or the die-level interconnect structure 106.

The die 102 can be attached to the package substrate 121 according to a wide range of suitable configurations, including, for example, direct coupling with the package substrate 121 in a flip chip configuration, as depicted. In the flip-chip configuration, the movable side S1 of the die 102 including the circuit uses the die-level interconnect structure 106, such as bumps, pillars, or other suitable ones that can electrically couple the die 102 and the package substrate 121 Structure and attached to the surface of the package substrate 121. The movable side S1 of the die 102 may include a movable device, such as a transistor device. The inactive side S2 can be arranged opposite to the movable side S1 as if visible.

The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter referred to as "device layer 102b"), and one or more interconnection layers (hereinafter referred to as "interconnect layer 102c"). In some embodiments, the semiconductor substrate 102a may substantially comprise bulk semiconductor material, such as silicon. The device layer 102b may represent a region in which the activity of the transistor device such as The moving device is formed on the semiconductor substrate. The device layer 102b may include, for example, a transistor structure, such as a channel body and/or source/drain regions of a transistor device. The interconnection layer 102c may include interconnection structures (such as electrode terminals) that are configured to transmit electrical signals to or from the active devices of the device layer 102b. For example, the interconnection layer 102c may include horizontal lines (for example, grooves) and/or vertical plugs (for example, through holes) or other suitable components to provide circuit routing and/or contacts.

In some embodiments, the die-level interconnect structure 106 may be electrically coupled to the interconnect layer 102c and configured to transmit electrical signals between the die 102 and other electrical devices. The electrical signal may include, for example, an input/output (I/O) signal and/or a power/ground signal, which is used for the operation of bonding the die 102.

In some embodiments, the packaging substrate 121 is an epoxy resin-based laminate substrate with a core and/or built-in layer, such as an Aquino Morta Building Film (ABF) substrate. In other embodiments, the package substrate 121 may include other suitable types of substrates, including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The packaging substrate 121 may include circuit components, which are assembled to transmit electrical signals to or from the die 102. The circuit components may include, for example, solder pads or traces (not shown), which are disposed on one or more surfaces of the package substrate 121 and/or internal routing components (not shown), such as grooves, vias, or other interconnect structures , And the electrical signal is transmitted through the packaging substrate 121. For example, in some embodiments, the package substrate 121 may include circuit components, such as bonding pads (not shown), which are assembled to receive individual die-level interconnects of the die 102 Structure 106.

The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulating material, such as epoxy laminate. For example, the circuit board 122 may include an electrical insulating layer composed of the following materials, such as polytetrafluoroethylene, phenolic tissue paper materials such as flame retardant 4 (FR-4), FR-1, tissue paper, and materials such as CEM-1 Or CEM-3 epoxy resin material, or woven glass material laminated with epoxy prepreg material. An interconnection structure (not shown) such as traces, grooves, or vias may be formed through an electrical insulating layer, and electrical signals of the die 102 may be transmitted through the circuit board 122. In other embodiments, the circuit board 122 may be composed of other suitable materials. In some embodiments, the circuit board 122 is a motherboard.

Package-level interconnects such as solder balls 112 can be coupled to one or more solder pads (hereinafter referred to as “pads 110”) on the package substrate 121 and/or the circuit board 122 to form corresponding solder joints. Furthermore, electrical signals are transmitted between the packaging substrate 121 and the circuit board 122. The bonding pad 110 may be composed of any suitable conductive material such as metal, including, for example, nickel (Ni), platinum (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques for physically and/or electrically coupling the packaging substrate 121 and the circuit board 122 may be used in other embodiments.

In other embodiments, the IC component 200 may include a wide range of other suitable configurations, including, for example, flip-chip and/or wire bonding configurations, interposers, including system-in-package (SiP) and/or package-on-package (PoP) configurations Suitable combination of multiple chip package configurations. Other suitable techniques for transmitting electrical signals between the die 102 and the other components of the IC component 200 can be used if Dry examples.

3A to 3E schematically depict selected components of a multi-gate metal oxide semiconductor field effect transistor 300 (hereinafter referred to as a multi-gate transistor 300) according to several embodiments. FIG. 3A schematically depicts a perspective view of a multi-gate transistor 300. As shown in FIG. FIG. 3B schematically depicts a cross-section 330 of the multi-gate transistor 300 along an axis corresponding to the length of the gate. 3C schematically depicts the cross section 340 of the fin of the gate region 315 of the multi-gate transistor 300 along the axis corresponding to the gate width. FIG. 3D schematically depicts the cross section 350 of the source region 309 and/or the drain region 311 of the fin of the multi-gate transistor 300 along the axis parallel to the gate width. FIG. 3E schematically depicts a three-dimensional view of selected components of the multi-gate transistor 300. In some embodiments, the multi-gate transistor 300 may be a completely depleted substrate transistor. In some embodiments, the multi-gate transistor 300 may be a completely depleted silicon insulator (SOI) transistor. In some embodiments, the multi-gate transistor may be a tri-gate transistor.

3A to 3E, the multi-gate transistor 300 may include a substrate 302 having a substrate fin 302.1 extending from the surface of the substrate 302, as depicted. The substrate fin 302.1 can span the source region 309, the gate region 315, and the drain region 311 of the multi-gate transistor 300. The substrate fin 302.1 may be referred to as a substrate sub-fin. In some embodiments, the substrate 302 may be, for example, a semiconductor (eg silicon) substrate or an insulating substrate. In several embodiments, the substrate 302 may be, for example, a group III-V semiconductor material. The substrate 302 may include a dielectric isolation structure (not shown) to be electrically insulated from the multi-gate transistor 300. The dielectric isolation structure may be an oxide layer buried in the substrate. The dielectric isolation structure may be an oxide layer in the substrate fin 302.1. In several embodiments, The substrate 302 may be an insulating substrate. For example, the substrate 302 may include a lower single crystal silicon substrate on which an insulating layer, such as a silicon dioxide film, is formed. In some embodiments, the multi-gate transistor 300 can be formed on any well-known insulating substrate, such as a substrate formed from silicon dioxide, silicon nitride, silicon oxide, and/or sapphire. In some embodiments, the substrate 302 may be a semiconductor substrate, such as but not limited to a single crystal silicon substrate or a gallium arsenide substrate.

The substrate fin 302.1 may have a first fin 304 coupled to the top surface of the substrate fin 302.1, and may have a second fin 305 coupled to the top surface of the substrate fin 302.1, as depicted. The first and second fins 304 and 305 may be referred to as first and second sub-fins, or as sub-fins or sub-fin structures. The first and second fins 304 and 305 may be III-V group semiconductor materials. III-V semiconductors may include boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum phosphide, aluminum arsenide, aluminum antimonide, gallium nitride, gallium phosphide, gallium arsenide, gallium antimonide Combinations of, indium nitride, indium phosphide, indium arsenide, and indium antimonide, and other group III and/or group V elements to provide group III-V semiconductors with three or more elements. The first and second fins 304 and 305 may be formed from a single fin structure coupled to the substrate fin 302.1 during the manufacturing of the multi-gate transistor 300. The first and second fins 304 and 305 and/or the single fin structure can be formed by the aspect ratio captured on the substrate 302. In several embodiments, the substrate 302 may include III-V group materials. For example, the substrate may include a gallium arsenide semiconductor material. In some embodiments, the first and second fins may be replaced by substrate fins 302.1 extending into the space occupied by the first and second fins 304, 305, as depicted. In other words, the substrate fin 302.1 and the first and second fins 304 and 305 may be part of the same fin structure including the substrate material Minute. If the substrate fin 302.1 and the first and second fins 304 and 305 include a fin structure, a fin structure may refer to its component fins. In some embodiments, the substrate fin 302.1 is missing, and the first and second fins 304 and 305 can be directly coupled to the surface of the substrate 302.

The multi-gate transistor 300 may include a dielectric fin 320, coupled between the first and second fins 304, 305, and coupled to the top of the substrate fin 302.1, as depicted. In some embodiments, the dielectric fin may be composed of, for example, amorphous silicon. The dielectric fin 320 may be referred to as an amorphous silicon fin or a sub-fin, as a sub-fin or a sub-fin structure. The dielectric fin 320 and the first and second fins 304 and 305 can form a continuous fin, spanning the source region 309, the gate region 315, and the drain region 311 of the multi-gate transistor 300. The term "spanning" means that the length, width, and/or depth of the first structure and the second structure overlap in a linear direction corresponding to the length, width, and/or depth of the second structure, where the amount of overlap is approximately equal to that of the second structure The length, width, and/or depth. The first structure can extend beyond overlap.

Continuous fins can be called sub-fins or sub-fin structures. The continuous fin formed by the first fin 304, the second fin 305 and the amorphous fin 320 may be referred to as a sub-fin or a sub-fin structure. The dielectric fin 320 may include expansion regions 320.1 and 320.2, which extend from the central fin region of the dielectric fin 320 in a parallel direction corresponding to the axis of the gate width of the gate region 315. In other words, the expansion areas 320.1, 320.2 can expand in a direction corresponding to the cross section 340 shown in FIG. 3A. The expansion regions 320.1 and 320.2 may be limited to the gate region 315 between the spacers 314 of the multi-gate transistor 300. The dielectric fin 320 can span the length 320.3 of the gate of the gate region 315 of the multi-gate transistor 300. Introduce The fin 320 can provide better isolation between the source region 309 and the drain region 311 of the multi-gate transistor 300. Better isolation can reduce the leakage current of the multi-gate transistor 300, resulting in lower power loss for the device including the multi-gate transistor 300.

The multi-gate transistor 300 may include a shallow trench isolation (STI) structure 312 coupled to the substrate fin 302.1, the dielectric fin 320, the first fin 304, and the second fin 305, as depicted. The expansion regions 320.1, 320.2 of the dielectric fin 320 can be coupled to the top surface of the STI structure 312, as depicted. The STI structure 312 can be formed on the substrate 302 using standard manufacturing techniques. For example, the STI structure can be manufactured early in the semiconductor device manufacturing process, typically before the formation of the multi-gate transistor 300. Generally, the process of forming an STI structure includes etching groove patterns in a silicon substrate, depositing one or more dielectric materials to fill the grooves, and removing excessive dielectric materials using techniques such as chemical mechanical planarization. The dielectric material used to form the STI structure 312 may be, for example, silicon dioxide, or several other suitable dielectric materials, such as oxide or silicon of another material or nitride of another material.

The multi-gate transistor 300 may include a third fin 306 coupled to the first fin 304, the dielectric fin 320, and the second fin 305, as depicted. The third fin 306 may be referred to as a channel, a fin, a channel fin, or a fin structure. The third fin 306 can span the source region 309, the gate region 315, and the drain region 311 of the multi-gate transistor 300. The top surface 306.1 (FIG. 3C) of the third fin 306 can be a conductive channel for one of the gates of the multi-gate transistor 300. The side surfaces 306.2 and 306.3 (FIG. 3C) of the third fin 306 can be the conduction channels of the gate of the multi-gate transistor 300. In other words, the top 306.1 And the two sides 306.2 and 306.3 can be the three conduction channels of the multi-gate transistor 300. The sum of the widths of the two side surfaces 306.2, 306.3 and the top surface 306.1 defines the gate width of the multi-gate transistor 300. The third fin 306 may include a group III-V semiconductor material. For example, the third fin 306 may include indium gallium arsenide. In some embodiments, when the multi-gate transistor 300 is operating, the third fin 306 may be designed to operate in a fully depleted mode of operation. In some embodiments, the third fin 306 may include undoped indium gallium arsenide.

The combination of the substrate fin portion 302.1, the first fin portion 304, the second fin portion 305, the dielectric fin portion 320, and the third fin portion 306 can be referred to as the fin portion of the multi-gate transistor 300. The combination of the substrate fin portion 302.1, the first fin portion 304, the second fin portion 305, and the dielectric fin portion 320 can be referred to as the sub-fin region of the fin portion of the multi-gate transistor 300. The third fin 306 can be referred to as the active area of the fin of the multi-gate transistor 300. The fins of the multi-gate transistor 300 can be referred to as semiconductor fins, which span and extend from the surface of the semiconductor substrate 302. To facilitate the description of various embodiments, the shape of the fin is depicted as a rectangular structure; however, the shape of the fin may be other shapes, such as a cone, in addition to the rectangle. The shape of the fin can be determined at least in part by the procedures used to form the various components and regions of the fin. Regarding the tapered example, the substrate fin 302.1 may be wider than the first and second fins 305 on average. Similarly, the first fin part and the second fin part 305 may be wider than the third fin part 306. In addition, the third fin 306 may be sharply tapered and/or round, and may have rounded edges, such as the transition between the side surfaces 306.2, 306.3 and the top surface 306.1 of the third fin 306. In some embodiments, the top surface 306.1 of the third fin 306 may not have a flat surface, and may circulate along the entire top surface 306.1.

3D, the third fin 306 of the multi-gate transistor 300 may have a characteristic width 306W and a height 306H. In some embodiments, the height 306H can be between one-half the width 306W and two times the width 306W. In several embodiments, the height 306H and the width 306W may be approximately the same. In some embodiments, the height 306H and the width 306W may be less than 30 nanometers. In some embodiments, the height 306H and the width 306W may be less than 20 nanometers. In some embodiments, the height 306H and the width 306W may be less than 12 nanometers.

In the gate region 315, the multi-gate transistor 300 may include a gate region 315 and a spacer 314 between the source and drain regions 309 and 311. The spacer 314 can be coupled to the STI structure 312 on both sides of the fin of the multi-gate transistor 300. The spacer 314 can be coupled to the third fin 306 and includes a top surface 306.1 and side surfaces 306.2 and 306.3 of the third fin 306. The spacer 314 may have a lower inner portion 314.1, coupled to the side surface 320.4 of the dielectric fin 320, including expansion areas 320.1 and 320.2. The spacer 314 can be coupled to the side surfaces of the first fin 304 and the second fin 305. The spacer 314 can provide isolation between the gate of the multi-gate transistor and the source region 309 and the drain region 311. The spacer 314 can be used to replace the gate process and replace the temporary gate with the last transistor gate. In the replacement gate process, conventional manufacturing techniques can be used to remove temporary gates, such as virtual polysilicon gates, while leaving spacers 314 in the appropriate positions of the new gates on the multi-gate transistor 300.

The gate region 315 of the multi-gate transistor 300 may include a dielectric layer 316 including a high-K dielectric material. The dielectric layer 316 may be coupled to the dielectric fin 320, which includes the extended region 320.1, the spacer 314, and the top surface 306.1 and the side surfaces 306.2, 306.3 of the third fin 306, as depicted. The dielectric layer can isolate the gate electrode 318 of the gate region 315 of the multi-gate transistor 300. High-K dielectric materials can be made of hafnium-based high-K dielectric, hafnium nitride silicate (HfSiON) dielectric, hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, tantalum pentoxide (Ta ₂ O ₅ ), and titanium oxide (TiO ₂ ) composition. The dielectric material layer includes a high-K dielectric material, and can be deposited using, for example, atomic layer deposition or chemical vapor deposition, or by any other suitable method for manufacturing semiconductor devices. High-K dielectric can refer to materials with a higher dielectric constant value than silicon nitride, and silicon nitride can have a dielectric constant value of about 7. Low-K dielectric can refer to materials having a dielectric constant value smaller than that of silicon dioxide, and silicon dioxide can have a dielectric constant value of about 3.9.

The gate region 315 of the multi-gate transistor 300 may include a gate electrode 318, coupled to the dielectric layer 316, as depicted. The gate electrode 318 can be electrically insulated from the third fin 306, the source region 309, and the drain region 311 by the dielectric layer 316. The gate electrode 318 may comprise any suitable metal gate electrode material. In some embodiments, the gate electrode may be a metal gate electrode or an alloy metal gate electrode. For example, the metal gate electrode may include aluminum, tungsten, tantalum, or titanium, or alloys thereof. In some embodiments, the gate electrode can be formed from one or more materials having an intermediate energy gap work function between 4.6 and 4.8 eV. In several embodiments, the gate electrode 318 may be a thin film stack. In some embodiments, the gate electrode 318 and the dielectric layer 316 are formed by a replacement gate process.

The multi-gate transistor 300 may have a source region 309 and a drain region 311. The source region 309 and the drain region 311 can be a pair of the gate region 315 side. The source region 309 may have a source 308 coupled to the third fin 306. The source electrode 308 may be coupled to the second fin 304. The source electrode 308 may be a raised source electrode. The source electrode 308 may comprise any suitable semiconductor material suitably doped with N-type or P-type multi-gate transistors. The drain region 311 may have a drain 310 coupled to the third fin 306. The drain 310 can be coupled to the second fin 304. The drain 310 may be a convex drain. The drain 310 may include any suitable semiconductor material suitably doped with N-type or P-type multi-gate transistors. The raised source and drain can be formed by epitaxy.

The spacer 314 can separate the source electrode 308 and the drain electrode 310 from the gate electrode 318. The source electrode 308 and the drain electrode 310 may be coupled to the spacer 314. The source electrode 308 and the drain electrode 310 may be formed of the same conductivity type, such as N-type or P-type conductivity. In some embodiments, the source electrode 308 and the drain electrode 310 may have a doping concentration between ^{about 1×10 19} and 1×10 ²¹ atoms/cm ^3. In some embodiments, the source 308 and drain 310 may have a uniform concentration of dopants or may include different concentration sub-regions or doping profiles, such as tip regions (eg, source/drain extension). In some embodiments, when the transistor 300 is a symmetrical transistor, the source 308 and the drain 310 may have the same doping concentration and profile. In some embodiments, when the multi-gate transistor 300 is formed as an asymmetric transistor, the doping concentration and setting of the source 308 and the drain 310 can be changed to obtain specific electrical characteristics.

The multi-gate transistor 300 may have an interlayer dielectric 322, which may encapsulate the source region 309 and the drain region 311, as depicted in FIGS. 3B and 3D. The interlayer dielectric 322 can be coupled to the source and drain electrodes 308 and 310, the STI structure 312, and the spacer 314. The interlayer dielectric 322 can be coupled to the first fin 304, the exposed parts of the second fin 305, and the third fin 306. The interlayer dielectric 322 may have a top surface that is flush with or approximately flush with the top surface of the gate electrode 318. The interlayer dielectric 322 can be any suitable dielectric material for electrically isolating the source 308 and the drain 310, and can be applied using any suitable semiconductor manufacturing technique. The interlayer dielectric 322 may be a low-K dielectric material. The interlayer dielectric 322 can be, for example, silicon dioxide.

The multi-gate transistor 300 can be one of a plurality of multi-gate transistors having a fin structure as described in the various embodiments, two or more of which can be coupled to the substrate, having a source pad coupling The source region connected, the drain region coupled by the drain pad, and the gate region across each fin and coupled to the substrate. The multi-gate transistor 300 may further include components, typically added during the semiconductor manufacturing process, including, for example, heavily doped source/drain contact regions, dielectric isolation structures, various oxide and/or nitride materials, Deposited silicon and silicide on the source/drain/gate contact area.

FIG. 4 depicts a process 400 for manufacturing a multi-gate transistor according to several embodiments. 5A to 5F schematically depict various embodiments of the multi-gate transistor 500 at each stage of the process 400 of FIG. 4. In some embodiments, the multi-gate transistor 500 may be a tri-gate transistor. In order to facilitate the understanding of the procedure 400 of FIG. 4, FIGS. 5A to 5F will be depicted in conjunction with the procedure 400 of FIG. 4. The process 400 depicted in FIGS. 4 and 5A to 5F may include pre-processing, which may include manufacturing semiconductor fins (302.1, 307, 306) on the semiconductor substrate 302, as depicted in FIG. 5A. The semiconductor fins (302.1, 307, 306) may include sub-fin regions (302.1, 307) adjacent to the semiconductor substrate 302, and active on top of the sub-fin regions (302.1, 307). Dynamic area 306. The semiconductor fins (302.1, 307, 306) may include III-V semiconductors. The pre-processing may further include forming a sacrificial gate electrode structure on the semiconductor fins (302.1, 307, 306). The pre-processing may further include depositing a pair of spacers 314 on opposite sides of the sacrificial gate electrode structure. The pre-processing may further include etching the sacrificial gate electrode structure between the spacers 314 to expose a part of the sub-fin region 307 of the semiconductor fins (302.1, 307, 306). The etching of the sacrificial gate electrode structure can provide an open space 319.

At 402, the process 400 may include providing a semiconductor substrate with a partially formed multi-gate transistor 500 ("transistor 500") with an open space 319 between two spacers 314, which separates the source 308 and the drain 310 and open space 319, as depicted in FIG. 5A. In the replacement gate process of manufacturing a semiconductor device for pre-processing as previously discussed, by removing the replacement gate from the transistor 500, an open space 319 can be formed. The replacement gate process may include etching off the polysilicon gate to provide an open space 319. Transistor 500 can be as depicted in FIG. 5A, which depicts the cross section of transistor 500, along the length of gate 330 (gate cut), along the width of gate region 340 (fin cut under the gate), and Along the source/drain 350 (source/drain fin cut). The cross sections 330, 340, and 350 correspond to the cross sections of the manufactured multi-gate transistor 500 depicted in FIGS. 3B, 3C, and 3D, respectively. Transistor 500 may include substrate 302 with substrate fins 302.1, as previously described. The transistor 500 may include a sub-fin 307, which is coupled to the substrate fin 302.1 and extends. The section of the sub-fin 307 under the source 308 can be similar to the sub-fin 304 depicted in FIGS. 3A to 3E with. The section of the sub-fin 307 under the drain 310 may be the same as the sub-fin 305 depicted in FIGS. 3A to 3E. Sub-fin 307 may include a III-V semiconductor, as depicted for sub-fins 304 and 305. Transistor 500 may include third fin 306, as previously depicted. The third fin 306 may be referred to as a fin, as previously described. Transistor 500 may include interlayer dielectric 322, as previously described. Transistor 500 may include STI structure 312, as previously depicted.

At 404, the procedure 400 may include removing the section of the sub-fin 307 under the open space 319 to provide the sub-fin space 321, while a part of the fin 306 is coupled to the sub-fin 307 and kept in the open space 319, such as Depicted in Figure 5B. The section of the sub-fin 307 can be removed by a selective etching process under the fin 306. The selective etching process may include dry etching or wet etching, and various combinations of different dry and wet etching processes. The sub-fin open space 321 may be referred to as a cavity, and the size and shape of the cavity may depend on the etching process and the type of chemical used in the process. In some embodiments, the sub-fin open space 321 may extend laterally toward the source centerline 360 and/or the drain centerline 362. In some embodiments, the sub-fin open space 321 may extend upward to the source centerline 360 and/or the drain centerline 362. In some embodiments, the etching process can remove the surface portions of the substrate fin 302.1, the STI structure 312, and the fin 306.

At 406, the process 400 may include filling the sub-fin space 321 with a dielectric material 323, as depicted in FIG. 5C. In some embodiments, the dielectric material may be, for example, amorphous silicon. During the filling of the sub-fin space 321, the dielectric material can fill the open space 319, the package fin 306, and the cover interlayer dielectric 322, as depicted. In other words, the dielectric material can be A coating is formed on the surface of the body 500, as depicted. The dielectric material can be directly coupled to the substrate fin 302.1 of the substrate 302 under the open space 319. The dielectric material 323 may be deposited by chemical vapor deposition or physical vapor deposition or another suitable method. In several embodiments, the dielectric material 323 may be doped. In some embodiments, the dopant may be a P-type dopant or an N-type dopant. After the sub-fin space 321 is filled, the dielectric material 323 can be planarized to eliminate the dielectric material 323 on the surface of the transistor 500. Regarding the example, planarization can be accomplished by using a chemical mechanical polishing procedure. In some embodiments, the sub-fin open space 321 may extend laterally toward the source centerline 360 and/or the drain centerline 362, causing the dielectric material 323 to fill the laterally extending space. In some embodiments, the sub-fin open space 321 can extend upward to the source centerline 360 and/or the drain centerline 362, causing the dielectric material 323 to fill up the laterally extending space to the source centerline 360 and/or drain.极中心线362. In some embodiments, the etching process can remove the surface portions of the substrate fin 302.1, STI structure 312, and fin 306, causing the dielectric material 323 to fill the substrate fin 302.1, STI structure 312, and fin removed during etching. The surface part of section 306.

At 408, the process 400 may include removing the excessive insulating material 323 from the open space 319 and from the fin 306 in the open space 319 to form an insulator fin 320, coupled to the bottom of the fin 306 in the open space 319, and It is coupled to the sub-fin 307 as depicted in FIG. 5D. The excessive insulating material 323 can be removed by a dry etching process or by another suitable process. The multi-gate transistor 500 with the dielectric fin region under the gate region can provide better isolation between the source and drain, compared to the dielectric without the gate region Multi-gate transistors in the fin area result in reduced leakage current and better channel control.

After the dielectric material 323 is removed, the transistor 500 can receive the replacement gate in the replacement gate process. Therefore, the procedure 400 may further include depositing a dielectric material 327 in the open space 319, as depicted in FIG. 5E. The dielectric material 327 may be a high-K dielectric material. The dielectric material 327 can be coupled to the spacer 314, the dielectric fin region 320, and the fin 306 in the open space 319. The dielectric material can be coupled to the interlayer dielectric 322, as depicted. The procedure 400 may further include depositing a gate electrode material 329 on the dielectric material 327 to fill the open space 319, as depicted in FIG. 5E. The dielectric material 327 and the gate electrode material 329 may be deposited by atomic layer deposition or some other suitable procedures. The process 400 may further include removing the excessive gate electrode material 329 and the dielectric material 327 on the surface of the multi-gate transistor 500 to form a gate electrode insulated by the dielectric material 327, as depicted in FIG. 5F. The excessive gate electrode material and dielectric material 327 can be removed by, for example, a chemical mechanical process or another suitable process. The transistor 500 of the program 400 can be further processed to provide a semiconductor integrated circuit suitable for packaging and coupling to a circuit board of a computing device.

The embodiments of the present disclosure can use any suitable hardware and/or software to be configured as desired and implemented in the system. FIG. 6 schematically depicts a computing device 600 with a multi-gate metal oxide semiconductor field effect transistor according to several embodiments. The multi-gate metal oxide semiconductor field effect transistor has a dielectric fin region under the gate, as in the text Portrayed. In some embodiments, the dielectric fin region 320 may be, for example, amorphous silicon. In several embodiments, more The gate transistor may be a tri-gate transistor.

A multi-gate transistor with a dielectric fin region under the gate region can provide better isolation between the source and drain, compared to a multi-gate transistor without a dielectric fin region under the gate region, resulting in Reduced leakage current and better channel control.

The computing device 600 can house a board, such as a motherboard 602 (for example, in a housing 608). The motherboard 602 may include several components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 can be physically and electrically coupled to the motherboard 602. In some implementations, at least one communication chip 606 can also be physically and electrically coupled to the motherboard 602. In a further implementation, the communication chip 606 may be a part of the processor 604.

Depending on its application, the computing device 600 may include other components, and may or may not be physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (such as dynamic random access memory (DRAM) 614), non-volatile memory (such as read-only memory (ROM) 618), flash memory, Random access memory (RAM) 616, graphics processor 626, digital signal processor, encryption processor, chipset 612, antenna 632, display, touch screen display 636, touch screen controller 628, battery 644, audio Codec, video codec, power amplifier 624, global positioning system (GPS) device 620, compass 622, micro-electromechanical system (MEMS) sensor 642, Geiger counter, accelerometer, gyroscope, speaker 634, camera 610 , And mass storage devices (such as hard drives), compact discs (CD), digital audio-visual discs (DVD), controller 630, microphone 638, and/ Or socket 640 and so on. Not all of these components are depicted in the figure.

The communication chip 606 can enable wireless communication for transferring data to and from the computing device 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., and can transmit data through the use of modulated electromagnetic radiation through non-solid media. This term does not imply that the related device does not include any wiring, although some embodiments may not include any wiring. The communication chip 606 can implement any number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including WiGig, Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (for example, IEEE 802.16-2005 revision) , Long Term Evolution (LTE) project together with any amendments, updates, and/or amendments (for example, the new LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2", etc.). IEEE 802.16 compatible broadband wireless access ( BWA) network, generally called WiMAX network, is the abbreviation of Global Interoperability Microwave Access Standard. It is a qualified product that has passed the compliance and interoperability test of the IEEE 802.16 standard. The communication chip 606 can be based on the GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network operation. The communication chip 606 can be evolved according to GSM enhanced data (EDGE), GSM Enhanced Data Evolution Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN) operation. The communication chip 606 can be accessed based on code division multiplexing ( CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolution Data Optimization (EV-DO ), its derivatives, and any other wireless protocol operations assigned to 3G, 4G, 5G and more advanced versions. In other embodiments, the communication chip 606 can operate according to other wireless protocols.

The computing device 600 may include a complex communication chip 606. For example, the first communication chip 606 can be dedicated to short-distance wireless communication, such as WiGig, Wi-Fi and Bluetooth, and the second communication chip 606 can be dedicated to long-distance wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

The processor 604, the communication chip 606, the chipset 612, the memory chips 614, 616, 618, and other devices with the chips shown in the computing device 600 may include the multi-gate transistors described in the text. The term "processor" can refer to any device or part of a device that processes electronic data from a register and/or memory, and converts the electronic data into other electronic data that can be stored in the register and/or memory .

In various implementations, the computing device 600 can be a laptop computer, a light-saving laptop, a notebook computer, a super laptop, a smart phone, a tablet computer, a personal digital assistant (PDA), a super mobile PC, a mobile phone, a desk PC, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In some embodiments, the computing device 600 may be a mobile computing device. In a further implementation, the computing device 600 can be any other electronic device that processes data.

In various implementations, the computing device 600 can be a computer system, a server, a rack server, a blade server, and a supercomputer system. System, the components that are commonly used in mobile devices can be absent. In a further implementation, the computing device 600 can be any other electronic device that processes data.

The various components of the computing device 600 shown are included on the motherboard 602, which is a description of the embodiment and is not intended to be limited.

FIG. 7 schematically depicts a computing device 700 with a multi-gate metal oxide semiconductor field effect transistor according to several embodiments. As depicted in the text, the multi-gate metal oxide semiconductor field effect transistor has dielectric electrons under the gate. Fin area. In some embodiments, the dielectric fin region 320 may be, for example, amorphous silicon. In some embodiments, the multi-gate transistor may be a tri-gate transistor. A multi-gate transistor with a dielectric fin region under the gate region can provide better isolation between the source and drain, compared to a multi-gate transistor without a dielectric fin region under the gate region, resulting in Reduced leakage current and better channel control.

The computing device 700 can accommodate a board, such as a motherboard 702 (for example, in a housing 726). The motherboard 702 may include several components, including but not limited to a processor 704, a liquid cooling system component 706, a chipset 710, a memory 712, an expansion slot 714, a computer bus interface 716, a local area network (LAN) controller 718, The cooling system 722, the interface device 724, and the port 720. The chipset 710 may include communication chips. The components may be physically and electrically coupled to the motherboard 702, and may include other components. The term "processor" can refer to any device or part of a device that processes electronic data from a register and/or memory, and converts the electronic data into other electronic data that can be stored in the register and/or memory .

In several embodiments, the cooling system component 706 may include The routing of the cooling fluid and the pumping device is used for pumping and draining the cooling fluid. In some embodiments, the heat exchanger 708 can be coupled to various heat generating components of the computing device 700. The cooling system component 706 may be coupled to one or more heat exchangers 708 to transfer cooling fluid through the heat exchangers 708.

Depending on its application, the computing device 700 may include other components, and may or may not be physically and electrically coupled to the motherboard 702. These other components may include, but are not limited to, liquid cooling systems, interface devices (keyboard, display, mouse), memory, graphics processors, digital signal processors, encryption processors, chipsets, touch screen displays, touch Controls the screen controller, battery, audio codec, video codec, power amplifier, speakers, camera, and mass storage devices (such as hard drives), compact discs (CD), digital audio-visual discs (DVD), etc. In various implementations, the computing device 700 can be a computer system, a server, a rack server, a blade server, and a super computer system. In a further implementation, the computing device 700 can be any other electronic device that processes data.

The various components of the computing device 700 shown are included on the motherboard 702, which is a description of the embodiment and is not intended to be limited.

example

According to various embodiments of the present disclosure, a semiconductor IC with a multi-gate metal oxide semiconductor field effect transistor (MOSFET) with a gate region intervening an electronic fin region is depicted, as described and described in various embodiments.

The semiconductor device of Example 1 may include a semiconductor substrate; the semiconductor fin portion extends from the semiconductor substrate and includes a sub-fin region adjacent to the semiconductor substrate The body substrate and the active region on the top of the sub-fin region; the source region and the drain region are formed in the active region of the fin; the gate electrode structure is formed on the active region of the fin and is arranged in the source region Between the drain region and the drain region; and the dielectric material region is formed in the sub-fin region under at least a part of the gate electrode structure, wherein the dielectric material region does not extend beyond the center line of the source region or the center line of the drain region .

Example 2 may include the technical topics of Example 1 and other examples in the text, wherein the sub-fin region includes a first III-V semiconductor material, the active region includes a second III-V semiconductor material, and the dielectric material region includes amorphous silicon .

Example 3 may include the technical topics of Example 1 and other examples in the text, in which the semiconductor substrate includes a dielectric isolation structure.

Example 4 may include the technical topics of Example 1 and other examples in the text, wherein the sub-fin region further includes a substrate region adjacent to the semiconductor substrate, wherein the substrate region and the semiconductor substrate include semiconductor materials.

Example 5 may include the technical topics of Example 1 and other examples in the text, wherein the semiconductor device may further include a shallow trench isolation structure coupled to the opposite side of the sub-fin region.

Example 6 may include the technical topics of Example 5 and other examples in the text, in which the top surface of the shallow trench isolation structure is below the interface between the sub-fin area and the active area of the semiconductor fin.

Example 7 may include the technical themes of Example 6 and other examples in the text, wherein the dielectric material region may further include an expansion region coupled to the top surface of the shallow trench isolation structure, wherein the expansion region is along the width direction of the gate.

Example 8 may include the technical topics of Example 7 and other examples in the text. The semiconductor device may further include a high-K dielectric layer, coupled to the top surface and two opposite side surfaces of the active area, and coupled to the expansion of the dielectric material area. Region, and coupled to the spacer, which separates the gate electrode structure from the source region and the drain region; and the gate electrode, which is coupled to the high-K dielectric layer.

Example 9 may include the technical themes of Example 8 and other examples in the text, in which the high-K dielectric layer and the gate electrode are replacement structures formed in the replacement gate process.

Example 10 may include the technical theme of Example 8 and other examples in the text, wherein the source region includes a raised source and the drain region includes a raised drain.

Example 11 may include the technical subject matter of Example 10 and other examples in the text, wherein the semiconductor device may further include an interlayer dielectric material coupled to the raised source, the raised drain, the shallow trench isolation structure, and the spacer.

Example 12 may include the technical topics of any one of Examples 1-11 and other examples in the text, wherein the semiconductor substrate includes silicon, the sub-fin region includes gallium arsenide, and the active region includes indium gallium arsenide.

The process of manufacturing a semiconductor device of Example 13 may include manufacturing a semiconductor fin on a semiconductor substrate, wherein the semiconductor fin includes a sub-fin region adjacent to the semiconductor substrate and an active region on top of the sub-fin region, wherein the semiconductor fin includes III- Group V semiconductor; forming a sacrificial gate electrode structure on the semiconductor fin; depositing a pair of spacers on opposite sides of the sacrificial gate electrode structure; etching the sacrificial gate electrode structure between the spacer pairs to expose a part of the semiconductor fin Sub-fin area; etching the exposed part of the sub-fin area, and in A cavity in the sub-fin area is formed under the active area of the semiconductor fin; and an insulating material is deposited in the cavity.

Example 14 may include the technical topics of Example 13 and other examples in the text, in which the insulating material is amorphous silicon.

Example 15 may include the technical topics of Example 13 and other examples in the text, wherein the process may further include planarizing the insulating material to remove excessive insulating material; and etching the insulating material to re-expose the active area of the semiconductor fin.

Example 16 may include the technical topics of Example 15 and other examples in the text. The process may further include depositing a high-K dielectric material layer on the spacer, insulating material, and active area; depositing a gate electrode on the high-K dielectric material layer Electrode material; and removing the excessive gate electrode material and excessive high-K dielectric material layer.

Example 17 may include the technical topics of Example 13 and other examples in the text, wherein the sub-fin region includes the first III-V semiconductor material, and the active region includes the second III-V semiconductor material.

Example 18 may include the technical theme of Example 13 and other examples in the text, in which the acupuncture point spans the length between the pair of spacers.

The computing device of Example 19 may include a circuit board; and a semiconductor device, coupled to the circuit board, and includes a plurality of multi-gate transistors disposed on the semiconductor device; one or more multi-gate transistors include: a semiconductor substrate with The semiconductor fin extends from the semiconductor substrate and includes a sub-fin area adjacent to the semiconductor substrate and an active area on top of the sub-fin area; a source area and a drain area formed in the active area of the fin; a gate electrode structure, Formed in fins Is located on the active area of the part and is arranged between the source area and the drain area; and the dielectric material area is formed in the sub-fin area under at least a part of the gate electrode structure, wherein the dielectric material area does not extend beyond the source The centerline of the polar region or the centerline of the drain region.

Example 20 may include the technical theme of Example 19 and other examples in the text. The sub-fin region includes III-V semiconductor material, the active region includes the second III-V semiconductor material, and the dielectric material region is amorphous silicon.

Example 21 may include the technical subjects of Example 19 and other examples in the text, wherein the sub-fin region further includes a substrate region adjacent to the semiconductor substrate, and the computing device further includes a shallow trench isolation structure coupled to the opposite side of the sub-fin region, wherein, The top surface of the shallow trench isolation structure is below the interface between the sub-fin region and the active area, wherein the dielectric material region further includes an expansion region coupled to the top surface of the shallow trench isolation structure, and the expansion region is along the gate electrode structure Width direction; high-K dielectric layer, coupled to the top and side surfaces of the active area, coupled to the expansion area of the dielectric material area, and coupled to the spacer, which separates the gate electrode structure from the source area and drain And the gate electrode of the gate electrode structure, the gate electrode is coupled to the high-K dielectric layer, wherein the high-K dielectric layer and the gate electrode are replacement structures formed in the replacement gate process.

Example 22 may include the technical theme of Example 21 and other examples in the text, wherein the source region includes a raised source, coupled to the active region, and the drain region includes a raised drain, coupled to the active region, and an interlayer dielectric Material, coupled to the raised source, the raised drain, the shallow trench isolation structure, and the spacer.

Example 23 may include any one of Examples 19-22 and the technical topics of other examples in the text, wherein the semiconductor substrate includes silicon, the sub-fin area includes a gallium arsenide semiconductor, and the active area includes an indium gallium arsenide semiconductor.

Example 24 may include the technical topics of Example 19 and other examples in the text. The computing device is a wearable device or a mobile computing device, and the wearable device or mobile computing device includes one or more of the following: antenna, display, touch screen display , Touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, Geiger counter, accelerometer, gyroscope, speaker, or coupled with circuit board Of the camera.

Example 25 may include the technical topics of Example 19 and other examples in the text. The computing device is a desktop computer, server, or supercomputer, and includes one or more of the following: display, processor, cooling system, chipset , Memory, expansion slot, computer bus interface, LAN controller, port, or interface device coupled with circuit board.

Various embodiments may include any suitable combination of the above-mentioned embodiments, including alternative embodiments (or) of the embodiments, which are described (and) in combination with the above-mentioned forms (for example, "and" may be "and/or"). In addition, several embodiments may include one or more articles (for example, non-transitory computer readable media) with instructions stored thereon that, when executed, result in the actions of any of the above embodiments. Furthermore, several embodiments may include equipment or systems, with any suitable mechanism for implementing various operations of the above-mentioned embodiments. The above description of the described implementation includes those described in the "Summary of the Invention", and it is not intended to exhaust or limit the embodiments of this disclosure to the precise form of the disclosure. Although the text Specific implementations and examples are described for the purpose of description. Those familiar with the relevant skills will agree that various equivalent modifications can fall within the scope of this disclosure. In view of the above detailed description, the embodiments of the present disclosure can implement these modifications. The terms used in the following application items should not be interpreted as limiting the various embodiments disclosed in this disclosure to the specific implementations disclosed in the specification and application items. Rather, the scope will be completely determined by the following application items, which will be based on the doctrine translation organized by the interpretation of the application items.

300‧‧‧Multi-Gate Transistor

302‧‧‧Substrate

302.1‧‧‧Substrate fins

304‧‧‧First fin

305‧‧‧Second fin

306‧‧‧third fin

308‧‧‧Source

309‧‧‧Source Region

310‧‧‧Dip pole

311‧‧‧Dip pole area

312‧‧‧Shallow groove isolation structure

314‧‧‧Spacer

315‧‧‧Gate area

316‧‧‧Dielectric layer

318‧‧‧Gate electrode

320‧‧‧Dielectric Fin

320.3‧‧‧Length

Sections 330, 340, 350‧‧‧

Claims (23)

A semiconductor device includes: a semiconductor substrate; a semiconductor fin extending from the semiconductor substrate and including a sub-fin region adjacent to the semiconductor substrate and an active region on top of the sub-fin region; source regions and drain regions formed in In the active region of the fin; a gate electrode structure formed on the active region of the fin and arranged between the source region and the drain region; a shallow trench isolation structure coupled to the The opposite side of the sub-fin region; and a dielectric material region formed in the sub-fin region under at least a portion of the gate electrode structure, wherein the dielectric material region does not extend beyond the center line of the source region or the drain The center line of the pole region, and wherein the dielectric material region further includes an expansion region coupled to the top surface of the shallow trench isolation structure, wherein the expansion region is along the width direction of the gate electrode structure. For example, the semiconductor device of claim 1, wherein the sub-fin region includes a first III-V semiconductor material, the active region includes a second III-V semiconductor material, and the dielectric material region includes amorphous silicon . For example, the semiconductor device of the first item of the patent application, wherein the semiconductor substrate includes a dielectric isolation structure. For example, the semiconductor device of claim 1, wherein the sub-fin region further includes a substrate region adjacent to the semiconductor substrate, wherein the substrate region and the semiconductor substrate include semiconductor materials. For example, the semiconductor device of claim 1, wherein the top surface of the shallow trench isolation structure is in the sub-fin region of the semiconductor fin and the active Below the interface of the moving section. For example, the semiconductor device of claim 1 further includes: a high-K dielectric layer coupled to the top surface of the active area and the two opposite side surfaces, coupled to the expansion area of the dielectric material area, and It is coupled to a spacer, which separates the gate electrode structure from the source region and the drain region; and the gate electrode is coupled to the high-K dielectric layer. For example, the semiconductor device of item 6 of the scope of patent application, wherein the high-K dielectric layer and the gate electrode are replacement structures formed in a replacement gate process. For example, the semiconductor device of claim 6, wherein the source region includes a raised source, and the drain region includes a raised drain. For example, the semiconductor device of claim 8 further includes: an interlayer dielectric material coupled to the raised source, the raised drain, the shallow trench isolation structure, and the spacer. For example, the semiconductor device of the first item of the patent application, wherein the semiconductor substrate includes silicon, the sub-fin region includes gallium arsenide, and the active region includes indium gallium arsenide. A process for manufacturing a semiconductor device includes: manufacturing a semiconductor fin on a semiconductor substrate, wherein the semiconductor fin includes a sub-fin area adjacent to the semiconductor substrate and an active area on top of the sub-fin area, wherein the semiconductor fin portion Including III-V semiconductor; forming a sacrificial gate electrode structure on the semiconductor fin; Depositing a pair of spacers on opposite sides of the sacrificial gate electrode structure; etching the sacrificial gate electrode structure between the pair of spacers to expose a part of the sub-fin region of the semiconductor fin; etching the sub-fin region Exposing a portion, and forming a cavity in the sub-fin area under the active area of the semiconductor fin; and depositing an insulating material in the cavity. Such as the procedure of item 11 in the scope of patent application, wherein the insulating material is amorphous silicon. For example, the procedure of claim 11 further includes: planarizing the insulating material to remove excessive insulating material; and etching the insulating material to the active area of the semiconductor fin between the pair of spacers. For example, the procedure of item 13 of the scope of patent application further includes: depositing a high-K dielectric material layer on the spacer, the insulating material, and the active area; depositing a gate electrode material on the high-K dielectric material layer; And remove the excessive gate electrode material and excessive high-K dielectric material layer. Such as the procedure of item 11 of the scope of patent application, wherein the sub-fin region includes a first III-V semiconductor material, and the active region includes a second III-V semiconductor material. Such as the procedure of item 11 of the scope of patent application, wherein the cavity spans the length between the pair of spacers. An arithmetic device, including: a circuit board; and A semiconductor device is coupled to the circuit board and includes a plurality of multi-gate transistors arranged on the semiconductor device. One or more of the multi-gate transistors includes a semiconductor substrate with semiconductor fins extending from the semiconductor substrate , And includes a sub-fin area adjacent to the semiconductor substrate, and an active area on top of the sub-fin area, a source area and a drain area formed in the active area of the fin, and a gate electrode structure formed in the fin Part of the active region and disposed between the source region and the drain region, and the dielectric material region is formed in the sub-fin region under at least a part of the gate electrode structure, wherein the dielectric material region is formed in the sub-fin region under at least a part of the gate electrode structure. The electrical material region does not extend beyond the center line of the source region or the center line of the drain region. For example, the computing device of the 17th patent application, wherein the sub-fin region includes a III-V group semiconductor material, the active region includes a second III-V group semiconductor material, and the dielectric material region is amorphous silicon. For example, the computing device of claim 17, wherein the sub-fin region further includes a substrate region adjacent to the semiconductor substrate, and the computing device further includes: a shallow trench isolation structure coupled to the opposite side of the sub-fin region, wherein , The top surface of the shallow trench isolation structure is below the interface between the sub-fin area and the active area, wherein the dielectric material region further includes an expansion area coupled to the top surface of the shallow trench isolation structure, and the expansion The area is along the width direction of the gate electrode structure; the high-K dielectric layer is coupled to the top and side surfaces of the active area, and is coupled to The expansion region of the dielectric material region, and is coupled to a spacer, which separates the gate electrode structure from the source region and the drain region; and the gate electrode of the gate electrode structure, the gate electrode Coupled to the high-K dielectric layer, wherein the high-K dielectric layer and the gate electrode are replacement structures formed in a replacement gate process. For example, the computing device of claim 19, wherein the source region includes a raised source, coupled to the active region, and the drain region includes a raised drain, coupled to the active region, and an interlayer An electrical material is coupled to the raised source, the raised drain, the shallow trench isolation structure, and the spacer. Such as the operation device of the 17th patent application, wherein the semiconductor substrate includes silicon, the sub-fin area includes a gallium arsenide semiconductor, and the active area includes an indium gallium arsenide semiconductor. For example, the computing device of item 17 of the scope of patent application, wherein the computing device is a wearable device or a mobile computing device, and the wearable device or the mobile computing device includes one or more of the following: antenna, display, touch screen display , Touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, Geiger counter, accelerometer, gyroscope, speaker, or coupled with the circuit board Pick up the camera. For example, the computing device of item 17 of the scope of patent application, where the computing device is a desktop computer, server, or supercomputer, and includes one or more of the following: display, processor, cooling system, chipset, memory Body, expansion slot, computer bus interface, LAN controller, port 口, or an interface device coupled with the circuit board.

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