TWI724506B - Semiconductor memory device - Google Patents

Abstract

Embodiments described herein relate generally to a semiconductor memory device. According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Description

Semiconductor memory device

The embodiments described herein are generally related to a semiconductor memory device.

A memory device with a three-dimensional structure has been proposed. In the memory device, a memory hole is formed in a stacked body including a plurality of electrode layers stacked through an insulating layer. The electrode layer is used as the control gate in the memory cell. The silicon body used as the channel is arranged on the sidewall of the memory hole through the charge storage film.

In order to reduce the space factor of the control circuit of the three-dimensional memory array in the chip, a technique for providing the control circuit directly under the array is also proposed. For example, a configuration is proposed in which the bit line is connected to the transistor formed on the substrate via a contact plug formed at the end portion of the array and a bit line extension layer provided on the lower side of the memory array.

Therefore, a fine interconnection layer equivalent to the bit line is also required under the array. The area around the array is necessary for deep contact. In addition, there is a problem, for example, the bit line is substantially long, the bit line capacity increases, and the operation speed is affected.

According to one embodiment, a semiconductor memory device includes an array chip, a circuit chip, a bonding metal, a pad, and an external connection electrode. The array chip includes a plurality of storage memory cells arranged three-dimensionally and a memory side interconnection layer connected to the memory cells. The array chip does not include a substrate. The circuit chip includes a substrate, a control circuit arranged on the substrate, and a circuit side interconnection layer arranged on the control circuit and connected to the control circuit. The circuit chip is adhered to the array chip, wherein the circuit-side interconnection layer faces the memory-side interconnection layer. The bonding metal is disposed between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer. The pad is arranged in the array wafer. The external connection electrode reaches the pad from a surface side of the array chip.

According to the embodiment, the reliability of the semiconductor memory device can be improved.

The embodiments are described below with reference to the drawings. Note that in the drawings, the same components are denoted by the same reference numerals and signs.

FIG. 1 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment.

The semiconductor memory device of the first embodiment has the following structure: an array chip 100 including a plurality of memory cells arranged three-dimensionally and a circuit chip 200 including a control circuit for controlling data writing, erasing and reading of the memory cells are pasted together .

As described below, after the array wafer and the circuit wafer are pasted together on a wafer-by-wafer basis, the wafer bonding body is cut and divided into wafers.

First, the array wafer 100 is described. The array chip 100 includes a memory cell array 1 with a three-dimensional structure.

FIG. 3 is a schematic perspective view of the memory cell array 1. It should be noted that in FIG. 3, in order to clearly show the figure, an interlayer insulating layer, an insulating separation film, and the like are not shown.

In FIG. 3, the two directions orthogonal to each other are denoted as the X direction and the Y direction. The direction orthogonal to the X direction and the Y direction (XY plane) and in which the multilayer electrode layer WL is stacked is denoted as the Z direction (stacking direction).

The memory cell array 1 includes a plurality of memory strings MS. FIG. 4 is a schematic cross-sectional view of the memory string MS. Fig. 4 shows a cross section parallel to the YZ plane in Fig. 3.

The memory cell array 1 includes a stacked body including a plurality of electrode layers WL and a plurality of insulating layers 40. The electrode layer WL and the insulating layer 40 are alternately stacked. The stack body is arranged on the back gate BG used as the lower gate layer. It should be noted that the number of electrode layers WL shown in the figure is an example. The number of electrode layers WL can be any number.

As shown below with reference to FIG. 6, the back gate BG is provided on the first substrate 10 via insulating films 48 and 45. After the array wafer W1 and the circuit wafer W2 are pasted together, the first substrate is removed.

The back gate BG and the electrode layer WL are layers containing silicon as a main component. In addition, the back gate BG and the electrode layer WL contain, for example, boron as an impurity for imparting conductivity to the silicon layer. The electrode layer WL may contain metal silicide. Alternatively, the electrode layer WL is a metal layer.

The insulating layer 40 mainly contains, for example, silicon oxide. For example, the insulating film 48 is a silicon oxide film, and the insulating film 45 is a silicon nitride film.

A memory string MS is formed in a U shape and includes a pair of columnar sections CL extending in the Z direction and a connecting section JP coupled to the respective lower ends of the pair of columnar sections CL. The columnar section CL is formed in, for example, a columnar shape or an elliptical columnar shape, penetrates the stack body, and reaches the back gate BG.

The drain-side selector gate SGD is disposed at an end portion above one of a pair of columnar sections CL in the U-shaped memory string MS. The source side selection gate SGS is provided at the other upper end portion. The drain-side select gate SGD and the source-side select gate SGS are disposed on the electrode layer WL of the top layer via the interlayer insulating layer 43.

The drain-side select gate SGD and the source-side select gate SGS are layers containing silicon as a main component. In addition, the drain-side select gate SGD and the source-side select gate SGS contain, for example, boron as an impurity for imparting conductivity to the silicon layer.

The drain-side select gate SGD and the source-side select gate SGS used as the upper select gate and the back gate BG used as the lower select gate are thicker than one electrode layer WL.

The drain-side selection gate SGD and the source-side selection gate SGS are separated in the Y direction by an insulating separation film 47. The stacked body under the drain-side select gate SGD and the stacked body under the source-side select gate SGS are separated in the Y direction by an insulating separation film 46. That is, the stack body between one pair of columnar sections CL of the memory string MS is separated in the Y direction by the insulating separation films 46 and 47.

On the source-side select gate SGS, a source line (for example, a metal film) SL is provided via an insulating layer 44. A plurality of bit lines (for example, metal films) BL shown in FIG. 1 are disposed on the drain-side select gate SGD and the source line SL via an insulating layer 44. The bit line BL extends in the Y direction.

FIG. 5 is an enlarged schematic cross-sectional view of a part of the columnar section CL.

The columnar section CL is formed in a U-shaped memory hole formed in a stacked body including a plurality of electrode layers WL, a plurality of insulating layers 40, and a back gate BG. In the memory hole, a channel body 20 serving as a semiconductor body is provided. The channel main body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than the impurity concentration of the electrode layer WL.

The memory film 30 is disposed between the inner wall of the storage hole and the channel main body 20. The memory film 30 includes a blocking insulating film 35, a charge storage film 32, and a tunnel insulating film 31.

The blocking insulating film 35, the charge storage film 32, and the tunnel insulating film 31 are provided in this order from the electrode layer WL side between the electrode layer WL and the channel main body 20.

The channel main body 20 is arranged in a cylindrical shape extending in the stacking direction of the stacked main body. The memory film 30 is arranged in a cylindrical shape to surround the outer peripheral surface of the channel main body 20 while extending in the stacking direction of the stacked main body. The electrode layer WL surrounds the channel main body 20 via the memory film 30. The core insulating film 50 is provided inside the channel main body 20. The core insulating film 50 is, for example, a silicon oxide film.

The barrier insulating film 35 is in contact with the electrode layer WL. The tunnel insulating film 31 is in contact with the channel main body 20. The charge storage film 32 is provided between the blocking insulating film 35 and the tunnel insulating film 31.

The channel main body 20 serves as a channel in the memory cell MC. The electrode layer WL serves as the control gate of the memory cell. The charge storage film 32 is used as a data storage layer for accumulating charges injected from the channel main body 20. That is, a memory cell MC having a structure in which the control gate surrounds the channel is formed in the intersection of the channel main body 20 and the electrode layer WL.

The semiconductor memory device of the first embodiment is a non-volatile semiconductor memory device, which can perform erasing and writing of data electrically and freely, and can retain the stored content even if the power is cut off.

The memory cell MC is, for example, a charge trap type memory cell. The charge storage film 32 includes a large number of trap sites for trapping charges. The charge storage film 32 is, for example, a silicon nitride film.

When charges are injected into the charge storage film 32 from the channel main body 20 or when the charges stored in the charge storage film 32 diffuse to the channel main body 20, the tunnel insulating film 31 serves as a potential barrier. The tunnel insulating film 31 is, for example, a silicon oxide film.

Alternatively, as the tunnel insulating film, a stacked film (ONO film) having a structure in which a silicon nitride film is sandwiched by a pair of silicon oxide films can be used. When the ONO film is used as a tunnel insulating film, compared with a single-layer silicon oxide film, the erasing operation can be performed in a low electric field.

The blocking insulating film 35 prevents the charge stored in the charge storage film 32 from diffusing to the electrode layer WL. The blocking insulating film 35 includes a cap film 34 provided in contact with the electrode layer WL and a barrier film 33 provided between the cap film 34 and the charge storage film 32.

The barrier film 33 is, for example, a silicon oxide film. The cap film 34 is a film having a dielectric constant higher than that of silicon oxide, and is, for example, a silicon nitride film. By providing this cap film 34 in contact with the electrode layer WL, the reverse tunnel electrons injected from the electrode layer WL can be suppressed during erasure. That is, by using a stacked film of a silicon oxide film and a silicon nitride film as the blocking insulating film 35, the charge blocking property can be improved.

As shown in FIGS. 3 and 4, the drain-side selection transistor STD is disposed at the end portion of one of the pair of columnar sections CL in the U-shaped memory string MS. The source-side selection transistor STS is provided at the other upper end portion.

The memory cell MC, the drain-side selection transistor STD, and the source-side selection transistor STS are vertical transistors, in which current flows in the stacking direction (Z direction) of the stack body.

The drain-side selection gate SGD is used as the gate electrode (control gate) of the drain-side selection transistor STD. The insulating film 51 (FIG. 4) used as the gate insulating film of the drain side selection transistor STD is provided between the drain side selection gate SGD and the channel main body 20. The channel body 20 of the drain side selection transistor STD is connected to the bit line BL above the drain side selection gate SGD.

The source-side selection gate SGS is used as the gate electrode (control gate) of the source-side selection transistor STS. The insulating film 52 (FIG. 4) used as the gate insulating film of the source-side selection transistor STS is provided between the source-side selection gate SGS and the channel main body 20. The channel body 20 of the source-side select transistor STS is connected to the source line SL above the source-side select gate SGS.

The back gate transistor BGT is arranged in the connection section JP of the memory string MS. The back gate BG is used as the gate electrode (control gate) of the back gate transistor BGT. The memory film 30 provided in the back gate BG serves as the gate insulating film of the back gate transistor BGT.

A plurality of memory cells MC including electrode layers WL as respective layers of control gates are arranged between the drain-side selection transistor STD and the back gate transistor BGT. Similarly, between the back gate transistor BGT and the source-side select transistor STS, a plurality of memory cells MC including electrode layers WL as respective layers of control gates are also provided.

A plurality of memory cells MC, drain-side select transistor STD, back gate transistor BGT, and source-side select transistor STS are connected in series by the channel main body 20 to form a U-shaped memory string MS. A plurality of memory strings MS are arranged in the X direction and the Y direction, so that a plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

The electrode layer WL is divided into a plurality of blocks in the Y direction and extends in the X direction.

In FIG. 1, the end region in the X direction in the memory cell array 1 is shown. A step structure section 96 of the electrode layer WL is formed at one end of the memory cell array area 81 provided with a plurality of memory cells MC.

In the step structure section 96, the end portions of the electrode layers WL of the respective layers in the X direction are formed in a step shape. In the step structure section 96, a plurality of contact plugs 61 are provided, which are connected to the electrode layers WL of respective layers formed in a step shape. The contact plug 61 is connected to the electrode layer WL of the respective layer in a step shape passing through the interlayer insulating layer 69.

In the step structure section 96, the back gate BG is connected to the contact plug 63. The selection gate SG (the drain side selection gate SGD and the source side selection gate SGS) is connected to the contact plug 65.

The contact plug 61 connected to the electrode layer WL is connected to the word interconnection layer 62. The contact plug 63 connected to the back gate BG is connected to the back gate interconnection layer 64. The contact plug 65 connected to the selection gate SG is connected to the selection gate interconnection layer 66.

The word interconnection layer 62, the back gate interconnection layer 64, and the select gate interconnection layer 66 are arranged in the same layer. The source line SL shown in FIG. 3 is also provided in the same layer as the word interconnection layer 62, the back gate interconnection layer 64, and the select gate interconnection layer 66.

The word interconnection layer 62, the back gate interconnection layer 64, the select gate interconnection layer 66, and the source line SL are formed by patterning the same material layer (for example, a metal layer). Therefore, the word interconnection layer 62, the back gate interconnection layer 64, the select gate interconnection layer 66, and the source line SL are formed in the same layer at the same time, and are formed of the same material to the same thickness.

The word interconnection layer 62 is further connected to the surface layer interconnection layer 73 via other plugs and interconnection layers, and the surface layer interconnection layers are formed on the bonding surface side of the circuit chip 200 of the array chip 100.

The back gate interconnection layer 64, the select gate interconnection layer 66 and the source line SL are also connected to the surface layer interconnection layer 73 via other plugs and interconnection layers.

The channel main body 20 and the bit line BL of the columnar section CL are connected via the plug 67. In addition, the bit line BL is connected to the surface layer interconnection layer 73 via other plugs and interconnection layers.

The array chip 100 includes a memory-side interconnection layer for electrically connecting the memory cell array 1 to the circuit chip 200. The memory-side interconnection layer is formed as a multi-layer interconnection including a word interconnection layer 62, a back gate interconnection layer 64, a select gate interconnection layer 66, and a surface layer interconnection layer 73.

The surface layer interconnection layer 73 is connected to the circuit side interconnection layer 76 of the circuit chip 200 via bonding metals 74a and 74b. The circuit wafer 200 includes a substrate 5. The substrate 5 is, for example, a silicon substrate.

The control circuit is formed on the circuit forming surface of the substrate 5 (the surface facing the side of the array chip 100). The control circuit is formed as a semiconductor integrated circuit including a transistor 77. The transistor 77 has a metal oxide semiconductor field effect transistor (MOSFET) structure including, for example, a gate electrode 78 and source/drain regions. The source/drain regions of the MOSFET are connected to the circuit-side interconnection layer 76 via the plug 79.

The circuit-side interconnection layer 76 is formed as a multilayer interconnection on the circuit formation surface via the interlayer insulating film 80.

The bonding metals 74a and 74b are provided between the surface interconnection layer 73 of the array chip 100 and the uppermost interconnection layer of the circuit-side interconnection layer 76 of the circuit chip 200 (the top interconnection layer viewed from the substrate 5). The joining metals 74a and 74b are, for example, copper or a copper alloy containing copper as a main component.

The surface layer interconnection layer 73 of the array chip 100 and the circuit side interconnection layer 76 of the top layer of the circuit chip 200 are bonded to the bonding metals 74a and 74b. An insulating film 75 is provided around the bonding metals 74a and 74b between the array chip 100 and the circuit chip 200. The insulating film 75 is a resin film or an inorganic film.

The array chip 100 and the circuit chip 200 are pasted together via bonding metals 74 a and 74 b and an insulating film 75. The memory-side interconnection layer of the array chip 100 and the circuit-side interconnection layer 76 of the circuit chip 200 are electrically connected through bonding metals 74a and 74b.

Therefore, the memory cell array 1 is connected to the control circuit of the circuit chip 200 via the storage-side interconnection layer, the bonding metals 74a and 74b, and the circuit-side interconnection layer 76.

According to the first embodiment, the external connection electrode 71 is formed on the array wafer 100 side. The pad 70 is disposed in a region closer to the end than the stepped structure section 96 in the array chip 100.

For example, when the word interconnection layer 62, the back gate interconnection layer 64, the select gate interconnection layer 66, and the source line SL are formed, the pad 70 is formed by patterning a metal layer (for example, a tungsten layer). Therefore, the pad 70 is formed in the same layer as the word interconnect layer 62, the back gate interconnect layer 64, the select gate interconnect layer 66, and the source line SL, and are formed of the same material to the same thickness.

The external connection pad 72 is provided on the surface of the array chip 100 (the surface on the opposite side of the bonding surface to the circuit chip 200). The external connection electrode 71 is provided between the external connection pad 72 and the pad 70.

The pad 70 is electrically connected to the circuit-side interconnection layer 76 via the memory-side interconnection layer or a separately provided through hole. Therefore, the control circuit formed in the circuit wafer 200 is electrically connected to the external connection pad 72 via the pad 70 and the external connection electrode 71. The external connection pad 72 may be connected to a mounting substrate or other chip via, for example, solder balls, metal bumps, or bonding wires.

A plurality of bonding metals 74 a and 74 b are arranged in the bonding section of the array chip 100 and the circuit chip 200. The plurality of bonding metals 74a and 74b mainly include a plurality of bit line lead-out sections 74a electrically connected to the bit line BL and a plurality of word line lead-out sections 74b electrically connected to the electrode layer WL.

FIG. 2 is a schematic plan view showing the arrangement relationship of the bit line lead-out section 74a and the word line lead-out section 74b.

The bit line lead-out section 74a is arranged in an area overlapping the memory cell array area 81 along the stacking direction, and a plurality of memory strings MS (area under the memory cell array area 81 in FIG. 1) are arranged therein.

The word line lead-out section 74b is arranged in a region overlapping with the region in which the step structure section 96, the external connection electrode 71, etc., are further formed at the outer side different from the memory cell array region 81 in the stacking direction. In FIG. 1, a plurality of word line lead-out sections 74b are arranged in the area under the step structure section 96 and the area under the external connection electrode 71 (pad 70).

The method for manufacturing the semiconductor memory device of the first embodiment will be described with reference to FIGS. 6 and 7.

The components of the array chip 100 and the components of the circuit chip 200 are respectively formed in a wafer state.

In FIG. 6, the array wafer W1 and the circuit wafer W2 before being pasted together are shown.

Before pasting, the substrate 10 remains on the array wafer W1. The back gate BG is formed on a substrate (for example, a silicon substrate) 10 via a silicon oxide film 48 and a silicon nitride film 45. In addition, a stacking main system including a plurality of electrode layers WL and a selection gate SG is stacked on the back gate BG.

After the stacked body is formed, the memory string MS, the step structure section 96, and the like are formed. In addition, a memory-side interconnection layer is formed. The pad 70 is also formed during the formation of the memory-side interconnection layer.

After the surface layer interconnection layer 73 of the memory side interconnection layer is formed, the first bonding metal 91 and the first insulating film 92 are formed on the bonding surface of the array wafer W1 (the surface on the opposite side of the substrate 10). The first bonding metal 91 is bonded to the surface layer interconnection layer 73. The first insulating film 92 is formed between the first bonding metal 91 and the first bonding metal 91 (around the first bonding metal 91). The surface (bonding surface) of the first bonding metal 91 is exposed from the first insulating film 92.

The components of the circuit wafer W2 are formed on a substrate (for example, a silicon substrate) 5 different from the substrate 10 of the array wafer W1.

After the control circuit (semiconductor integrated circuit) including the transistor 77 is formed on the surface of the substrate 5, the circuit-side interconnection layer 76 is formed via the interlayer insulating layer 80.

The second bonding metal 93 and the second insulating film 94 are formed on the bonding surface of the circuit wafer W2 (the surface on the opposite side of the substrate 5). The second bonding metal 93 is bonded to the circuit interconnection layer 76 of the top layer. The second insulating film 94 is formed between the second bonding metal 93 and the second bonding metal 93 (around the second bonding metal 93). The surface (bonding surface) of the second bonding metal 93 is exposed from the second insulating film 94.

The array wafer W1 and the circuit wafer W2 are joined wafer by wafer by applying mechanical pressure, wherein the surfaces on the opposite sides of the substrates 10 and 5 face each other.

The first bonding metal 91 and the second bonding metal 93 are, for example, copper or copper alloy. The first bonding metal 91 and the second bonding metal 93 are bonded to each other to form an integrally bonded metal 74, as shown in FIG. 7. The first insulating film 92 and the second insulating film 94 are joined to form an integrated insulating film 75.

After the array wafer W1 and the circuit wafer W2 are pasted together, the substrate 10 of the array wafer W1 is removed. For example, the entire substrate 10 is removed by wet etching using nitrohydrofluoric acid.

On the surface from which the substrate 10 is removed, the insulating film (silicon oxide film 48 and silicon nitride film 45) formed on the substrate 10 remains as a passivation film for protecting the surface of the array wafer W1 (array wafer 100).

After the substrate 10 is removed, a through hole 95 reaching the pad 70 is formed from the surface side of the removed substrate 10 (the surface of the silicon oxide film 48). In the through hole 95, as shown in FIG. 1, the external connection electrode 71 is embedded.

Alternatively, the external connection electrode 71 may be formed on the bottom section (the upper surface of the pad 70) of the through hole 95 and the sidewall of the through hole 95 while leaving a space in the through hole 95.

In order to drive the memory cell array 1, a high voltage of, for example, about 20 V is sometimes required. In order to maintain the breakdown voltage of the transistor 77 of the control circuit (CMOS circuit) (to extend the depletion layer), it is desirable to leave a substrate (silicon substrate) 5 with a thickness of about 10 to 20 μm on the side of the circuit chip 200. The thick substrate 5 is used as the support body of the semiconductor memory device.

When connecting the control circuit to an external circuit, it is conceivable to form a through silicon via (TSV) penetrating the substrate 5 from the rear surface side of the substrate 5 and connect the TSV to the circuit-side interconnect layer 76. However, the cost and processing time of etching the thick substrate 5 are large. In addition, in order to prevent short circuits between the silicon substrate 5 and the electrodes in the vias, a process of forming an insulating film on the sidewalls of the vias is also required.

On the other hand, according to the first embodiment, the through hole 95 (FIG. 7) is formed on the side of the array chip 100 from which the substrate 10 is removed. Since the thickness of the array chip 100 is about several micrometers, a deep etching process for penetrating a substrate with a thickness of tens of micrometers is not required. It is possible to reduce costs.

By using wet etching to remove the substrate 10 of the array wafer W1, unlike removing the substrate by grinding, stress applied to the memory cell array 1 is not generated. Therefore, the yield and reliability are improved.

A method for forming a control circuit on a substrate and forming a memory cell array on the control circuit is also conceivable. However, in some cases, forming the three-dimensional memory cell array 1 requires a heating process of 900° C. or higher. If the control circuit is formed under the cell array in advance, there are concerns about problems such as the diffusion of impurities in the transistor and the heat resistance of metal contacts.

In addition, it is expected that the performance of the transistor will be improved in accordance with the increase in interface speed in the future. It may also be necessary to use a process with low heat resistance to form the control circuit, in which a self-aligned silicide or the like is used.

On the other hand, according to the first embodiment, since the array chip 100 including the memory cell array 1 and the circuit chip 200 including the control circuit are formed by a separate chip process, the high heat treatment of the memory cell array 1 does not affect the control circuit. Therefore, it is possible to form the memory cell array 1 and the control circuit with a highly reliable structure.

In the structure in which the control circuit and the memory cell array are sequentially formed on the substrate, when viewed from the substrate, the bit lines are formed on the upper side of the stack body. Therefore, when connecting the bit line to the control circuit, after the bit line is led out to the area outside the memory cell array area through the interconnect layer formed on the bit line, the deep contact plug is connected from the lead interconnect layer To the control circuit on the surface of the substrate. This may result in an increase in chip area due to the wiring area used for interconnection. There are also such problems: the bit line is basically very long, the bit line capacity increases, and the operating speed is affected. The same problem exists with regard to the wiring of the electrode layer (word line).

On the other hand, according to the first embodiment, the side where the bit line BL, the source line SL, the word interconnection layer 62, etc. are formed is bonded to the circuit die 200 via the bonding metals 74a and 74b. Therefore, the interconnection only needs to be led directly downward (toward the bonding surface side).

For example, as described with reference to FIG. 2, the bit line lead-out section 74 a is not drawn out to (not disposed) outside of the memory cell array area 81, but is disposed in an overlapping area under the memory cell array area 81.

Therefore, it is possible to suppress the increase in the interconnection length and the interconnect formation area for connecting the bit line BL, the source line SL, the word interconnection layer 62, etc. to the control circuit, and suppress the operation delay and the increase of the wafer area.

As described above, according to the first embodiment, an increase in the capacity and reliability of the memory cell can be achieved through an inexpensive manufacturing process. In addition, the optimization and speed improvement of the control circuit can be realized.

The pads connected to the external connection electrodes can be formed in the same layer as the back gate BG, as shown in FIG. 8.

Polysilicon is usually used in the back gate BG. Therefore, in order to reduce the resistance of the pad, it is desirable to stack a layer 110 containing a metal such as a metal silicide layer or a metal layer on the back gate BG.

The metal-containing layer 110 is formed on the substrate 10 via the insulating films 48 and 45 in the wafer stage. The back gate BG is formed on the layer 110. The layer 110 containing the metal and the back gate BG is patterned and left as the pads 110 and 111 in the area on the outer side of the step structure section 96.

After the substrate 10 is removed, a through hole reaching the pad 110 is formed from the surface side of the array wafer W1. The external connection electrode 112 is formed in the through hole.

Compared with the structure shown in FIG. 1 in which the pad is formed in the same layer as the word interconnection layer 62 and the like, the through hole may be shallow. The cost can be further reduced and the output can be further increased.

The pad is not limited to being formed in the array wafer 100. As shown in FIG. 9, a part of the circuit-side interconnection layer 76 of the circuit chip 200 can be used as the pad 122. For example, the interconnection layer of the top layer of the circuit-side interconnection layer 76 viewed from the substrate 5 is formed as the pad 122.

After the substrate 10 of the array wafer W1 is removed, a through hole reaching the pad 122 is formed in an area outside the step structure section 96 from the surface side of the array wafer W1. The external connection electrode 121 is formed in the through hole. The external connection electrode 121 is not connected to the circuit-side interconnection layer 76 via the memory-side interconnection layer.

10 is a schematic perspective view of the memory cell array 2 of another example of the semiconductor memory device of the first embodiment. It should be noted that in FIG. 10, as in FIG. 3, in order to clearly show the figure, an insulating layer and the like are not shown.

The source layer SL is provided on the side of the bonding surface opposite to the circuit wafer 200. The source-side select gate (lower select gate layer) SGS is provided on the source layer SL via an insulating layer.

The insulating layer is arranged on the source-side selection gate SGS. The stack body obtained by alternately stacking a plurality of electrode layers WL and a plurality of insulating layers is arranged on the insulating layer.

When viewed from the source layer SL, the insulating layer is disposed on the farthest electrode layer WL. The drain side selection gate (upper selection gate layer) SGD is arranged on the insulating layer.

The columnar section CL extending in the Z direction is provided in the stack body. That is, the columnar section CL pierces the drain-side select gate SGD, the plurality of electrode layers WL, and the source-side select gate SGS. One end of the channel body 20 in the columnar section CL is connected to the bit line BL. The other end of the channel main body 20 is connected to the source line SL.

The source line SL is formed on the substrate. A source-side selection gate SGS, a stacked body including a plurality of electrode layers WL, a drain-side selection gate SGD, and a bit line BL are sequentially formed on the source line SL. The array wafer containing the source line SL, the source-side select gate SGS, the stacked body including a plurality of electrode layers WL, the drain-side select gate SGD and the bit line BL is attached to the circuit wafer W2, wherein the bit line BL The side is opposite to the circuit wafer W2.

After pasting, remove the substrate. A through hole is formed from the surface side of the removed substrate. External connection electrodes are formed in the through holes.

FIG. 11 is a schematic cross-sectional view of the first semiconductor memory device of the embodiment.

The through hole 120 is provided in the array wafer 100. The through hole 120 penetrates the array chip 100 and reaches the pad 122 of the circuit chip 200. The through hole 120 extends along the memory string MS and the columnar section CL. The pad 122 is exposed at the bottom of the through hole 120.

12 is a schematic enlarged cross-sectional view of the wire bonding part of the semiconductor memory device of the first embodiment. FIG. 12 shows the side surface of the wire 500 and the bump 500a.

For example, as shown in FIG. 12, the wire 500 is bonded to the pad 122 through the through hole 120. The wire 500 is, for example, an Au (gold) wire or an Ag (silver) wire. The bump 500 a formed at the tip of the wire 500 is directly bonded to the pad 122. The upper surface of the array wafer 100 is covered with a protective film 49. The protective film 49 is, for example, a resin film.

13A and 13B are schematic enlarged cross-sectional views of the wire bonding portion of the semiconductor memory device of the first embodiment. 13A and 13B show the side surfaces of the wire 500 and the bump 500a.

In the example shown in FIG. 13A, the bump 500a is a stud bump having a plurality of bumps formed at the tip of the wire 500. The stud bump 500a is bonded to the pad 122 through the through hole 120. The height of the stud bump 500 a is greater than the depth of the through hole 120. In this example, the capillary holding the wire 500 may be located above the upper surface of the protective film 49. During the wire bonding process, the capillary tube and the wire 500 do not contact the protective film 49 and the sidewall of the through hole 120. This can reduce wire bonding failures.

In the example shown in FIG. 13B, the conductive body 123 is disposed on the pad 122 inside the through hole 120. The conductive body 123 contacts the pad 122. For example, the conductive body 123 is a Ni-Au alloy and is formed by electroplating. On the conductive body 123, no pads are formed. The bump 500 a formed at the tip of the wire 500 is joined to the upper surface of the conductive body 123.

In the example shown in FIG. 13B, the capillary holding the wire 500 may be located above the upper surface of the protective film 49. During the wire bonding process, the capillary tube and the wire 500 do not contact the protective film 49 and the sidewall of the through hole 120. This can reduce joint failures.

As shown in FIG. 6, the array wafer W1 is bonded to the circuit wafer W2. Then, after removing the substrate 10 of the array wafer W1, a through hole 120 is formed.

FIG. 14 is a scanning electron microscope (SEM) image of the semiconductor memory device of the first embodiment.

The semiconductor memory device shown in FIG. 14 includes a plurality of semiconductor memory devices as shown in FIGS. 11 to 13B.

A plurality of semiconductor memory devices (or chips) 300 are mounted on the wiring substrate 600, wherein a wiring net (not shown) is provided on the surface or inside of the insulating resin substrate. Each semiconductor memory chip 300 includes an array chip 100 and a circuit chip 200 bonded to the array chip 100, as shown in FIGS. 11 to 13B. The semiconductor memory chip 300 is stacked in a stepped configuration along at least one side of the semiconductor memory chip 300. The semiconductor memory chip 300 includes a plurality of pads 122 (through holes 120) arranged along one side edge of the semiconductor memory chip 300 and located at the side edge. Each electrode pad 122 may be exposed for wire bonding. The wiring substrate 600 includes a plurality of electrodes 601. Each electrode 601 is connected to a pad 122 on a different semiconductor memory chip 300 by a wire 500.

FIG. 15 is a block diagram of the semiconductor memory device 300 of the first embodiment.

The semiconductor memory device 300 of the embodiment is connected to a controller (not shown in FIG. 15). The controller receives commands from the host device (not shown) such as data writing, data reading, and data erasing operations.

The controller issues commands in response to these commands and transmits the commands to the semiconductor memory device 300. The semiconductor memory device 300 controls the data reading operation, the data writing operation, and the data erasing operation by the received command.

In FIG. 15, some connections between individual blocks are represented by solid arrow lines, but the connections between blocks are not limited to this.

As shown in the figure, the semiconductor memory device 300 includes an array chip 100 and a circuit chip 200. The array chip 100 includes, for example, a memory cell array 1. The circuit chip 200 includes other components, such as I/O control circuit 210, logic control circuit 211, status register 212, address register 213, command register 214, control circuit 215, ready/busy circuit 216, voltage The generator 217, the column decoder 219, the sense amplifier 220, the data register 221 and the row decoder 222.

The logic control circuit 211 receives, for example, the chip enable signal BCE-0, the command latch enable signal CLE-0, the address latch enable signal ALE-0, the write enable signal BWE-0, and the read enable signal RE-0. And BRE-0. The logic control circuit 211 controls the I/O control circuit 210 and the control circuit 215 in response to the received signal.

The chip enable signal BCE-0 is a signal used to enable the semiconductor memory device 300 and is set to a low level. The command latch enable signal CLE-0 is a signal indicating that the input/output signal I/O is a command, and is set to a high level. The address latch enable signal ALE-0 indicates that the input/output signal I/O is an address signal and is set to a high level. The write enable signal BWE-0 is a signal used to extract the received signal into the semiconductor memory device 300, and the signal is set to a low level whenever a command, address, and data are received from the controller. Therefore, every time BWE-0 is switched, the signal is extracted to the semiconductor memory device 300. The read enable signals RE-0 and BRE-0 are signals used to enable the controller to read each data from the semiconductor memory device 300. For example, the read enable signal BRE-0 is set to a low level, and the read enable signal RE-0 is set to a high level.

The I/O control circuit 210 controls the 8-bit input/output signals I/O<O> to I/O<7 that are transmitted and received between the controller and the semiconductor memory device 300 through the data lines DQ0-0 to DQ7-0 ＞The input and output.

More specifically, the I/O control circuit 210 includes an input circuit and an output circuit, and the input circuit receives command signals, address signals, and data, and transmits them to the command register 214, the address register 213, and the data register.存器221. In addition, the output circuit transmits various data stored in the semiconductor memory device 300 to the controller in response to instructions from the controller.

The various data includes, for example, memory data, ID data, parameter information, and status information. The memory data is, for example, data stored in the data register 221. The ID data is the unique identification information of the semiconductor memory device 300, such as product number, memory capacity, and interface specifications. The parameter information is information such as the setting value of the read voltage in the read operation. The status information is, for example, information indicating the result of the write operation. In the following, the operation of reading memory data from the data register 221 is called "register reading", the operation of reading ID data is called "ID reading", and the operation of reading parameter information is called "Acquisition feature", and the data output by the acquisition feature is called "GF data".

The command register 214 temporarily stores the command signal received from the controller by the I/O control circuit 210 and transmits the command signal to the control circuit 215.

The control circuit 215 responds to the command signal stored in the command register 214 to control the status register 212, the ready/busy circuit 216, the voltage generator 217, the column decoder 219, the sense amplifier 220, the data register 221, and the row The decoder 222 performs data reading operations, data writing operations, and data erasing operations.

The status register 212 temporarily saves the status of data read operation, data write operation, and data erasing operation, and notifies the controller whether the operation has been completed normally.

The ready/busy circuit 216 transmits the ready/busy signal RY/BBY to the controller according to the operating conditions of the control circuit 215. The ready/busy signal RY/BBY indicates whether the semiconductor memory device 300 is in a busy state (whether the semiconductor memory device 300 is in a state where it cannot receive commands from the controller or is in a state where it can receive commands from the controller) and is low in the busy state The signal of quasi.

The voltage generator 217 generates voltages required for data reading operations, data writing operations, and data erasing operations, and applies the voltages to the memory cell array 1, the row decoder 219, and the sensors by, for example, a driver (not shown) Amplifier 220.

The memory cell array 1 includes a plurality of transistors of the memory cell MC (as shown in FIG. 4 and FIG. 5). For example, the transistor saves data corresponding to the threshold level.

The address register 213 temporarily stores the address signal received from the controller through the I/O control circuit 210. Then, the address register 213 transmits the column address to the column decoder 219, and transmits the row address to the row decoder 222.

For example, in the data writing operation and the reading operation, the column decoder 219 decodes the column address and selects the word line WL (electrode layer WL) according to the decoding result.

Then, the column decoder 219 applies an appropriate voltage to the word line WL.

For example, in the data write operation and read operation, the row decoder 222 decodes the row address and selects the latch circuit in the data register 221 according to the decoding result.

The data register 221 includes a plurality of latch circuits (not shown). The latch circuit corresponds to the respective bit line BL and saves the written data and the read data. For example, in a data writing operation, the data register 221 temporarily stores data received from the controller through the I/O control circuit 210. In addition, for example, in a data reading operation, the data register 221 temporarily stores the data read by the sense amplifier 220 and transmits the data to the controller through the I/O control circuit 210.

In the data read operation, the sense amplifier 220 senses the data read to the bit line BL from the transistor connected to the selected word line WL. In addition, in the data writing operation, the sense amplifier 220 transmits the written data to the transistor connected to the selected word line WL. Hereinafter, the data units read and written in batches by the sense amplifier 220 are referred to as "pages".

FIG. 16 is a schematic cross-sectional view 300 of the semiconductor memory device of the first embodiment.

The array chip 100 and the circuit chip 200 shown in FIG. 16 are bonded to each other as shown in FIG. 11. The array chip 100 and the control circuit chip 200 are laminated in the directions indicated by the arrows shown in FIG. 16, respectively.

The array chip 100 and the circuit chip 200 are contained in a package 301. The package 301 is a ball grid array (BGA) or a land grid array (LGA) package. A plurality of conductive balls (or pads) 302 are arranged on the lower surface of the package 301.

Fig. 17 shows a schematic plan view of the BGA (or LGA) pin assignment. The signal code shown in Fig. 17 corresponds to the signal code shown in Fig. 15.

FIG. 18 is a schematic cross-sectional view of the semiconductor memory system 800 of the second embodiment.

The semiconductor memory system 800 shown in FIG. 18 includes an array chip 100 and an integrated control circuit chip 400 bonded to the array chip 100. The combination control circuit chip 400 will be described later. The array chip 100 and the combined control circuit chip 400 are laminated in the directions indicated by the arrows shown in FIG. 18, respectively.

The array chip 100 and the combined control circuit chip 400 are contained in a package 801. The package 801 is a ball grid array (BGA) or a land grid array (LGA) package. A plurality of conductive balls (or pads) 802 are arranged on the lower surface of the package 801.

19 is a schematic plan view of the integrated control circuit chip 400 of the semiconductor memory system of the second embodiment.

The combined control circuit chip 400 includes a control circuit 401 and a solid state drive (SSD) controller 402.

The control circuit 401 includes the I/O control circuit 210, the logic control circuit 211, the status register 212, the address register 213, the command register 214, the control circuit 215, and the ready/busy circuit 216 shown in FIG. 15 , Voltage generator 217, column decoder 219, sense amplifier 220, data register 221, and row decoder 222.

The SSD controller 402 includes an error correction code (ECC), a front-end interface, wear leveling and logic-to-physical conversion, and a NAND back-end interface.

The combined control circuit chip 400 is formed on a single monolithic silicon die.

FIG. 20 is a schematic diagram of the semiconductor memory device of the third embodiment.

This semiconductor memory device includes a stacking device 901. The stacking device 901 is installed on the circuit board 600. The passive device 603 is mounted on the circuit board 600. The passive device 603 is, for example, a chip capacitor. A plurality of conductive balls or pads 602 are arranged on the lower surface of the circuit board 600.

The stacking device 901 includes a circuit chip 700 and a plurality of array chips 100-2, 100-3, and 100-4. The array chips 100-2, 100-3, and 100-4 include the memory cell array 1 mentioned earlier. The circuit chip 700 is a combined control chip including the memory cell array 1, the control circuit 401 shown in FIG. 19, and the SSD controller 402 shown in FIG.

The array chip 100-2 is stacked on the circuit chip 700, the array chip 100-3 is stacked on the array chip 100-2, and the array chip 100-4 is stacked on the array chip 100-3.

FIG. 21A is a schematic plan view of the semiconductor memory device shown in FIG. 20. FIG. In FIG. 21A, the X direction is along one side of the circuit chip 700 and the plurality of array chips 100-2, 100-3, 1004, and the Y direction is perpendicular to the X direction.

The circuit chip 700 and the array chips 100-2, 100-3, and 100-4 are stacked in a stepped configuration along the X direction. The circuit chip 700 is offset in the Y direction to the array chips 100-2, 100-3, and 100-4.

A plurality of pads 101 are arranged on the end portions of the array chips 100-2, 100-3, and 100-4. The end part is formed in a stepped configuration. The pad 101 is arranged along the Y direction.

A plurality of pads 701 are arranged on the end portion of the circuit chip 700 in the X direction and the end portion of the circuit chip 700 in the Y direction. The pads 701 arranged at the end portion of the circuit chip 700 in the X direction are arranged along the Y direction. The pads 701 arranged at the end portion of the circuit chip 700 in the Y direction are arranged along the X direction.

Each of the pads 101 and 701 is electrically connected to a pad formed on the circuit board 600 by a wire 500.

The number of pads of the circuit chip 700 including the memory cell array 1, the control circuit 401 and the SSD controller 402 is greater than the number of pads of the array chips 100-2, 100-3, and 100-4. The pads 701 are arranged along both sides of the circuit chip 700. The circuit chip 700 is offset to the array chips 100-2, 100-3, and 100-4 in the X direction and the Y direction.

As shown in FIG. 21B, the size of the circuit chip 700 in the Y direction can be larger than the size of the array chips 100-2, 100-3, and 100-4 in the Y direction.

As shown in FIG. 22A, a plurality of conductive balls 702 may be disposed on the lower surface of the circuit chip 700. The circuit chip 700 is electrically connected to the circuit board 600 through conductive balls 702.

As shown in FIG. 22B, a plurality of conductive balls or bumps 102 can be connected to the circuit chip 700 and the array chip 100-2. The conductive balls or bumps 102 can connect the array chip 100-2 and the array chip 100-3. The conductive balls or bumps 102 can connect the array chip 100-3 and the array chip 100-4.

As shown in FIG. 23A, a plurality of circuit chips 700-1, 700-2, 700-3, 700-4 can be stacked on the circuit board 600 in a step configuration. Each circuit chip 700-1, 700-2, 700-3, 700-4 is a combined control circuit chip, and includes a memory cell array 1, a control circuit 401, and an SSD controller 402.

As shown in FIG. 23B, a plurality of stacked wafers 901 and 902 may be stacked on the circuit board 600.

The stacked chip 901 includes a circuit chip 700-1, an array chip 100-2, an array chip 100-3, and an array chip 100-4 stacked in a ladder configuration. The stacked chip 902 includes a circuit chip 700-2, an array chip 100-6, an array chip 100-7, and an array chip 100-8 stacked in a ladder configuration.

Each of the circuit chip 700-1, the array chip 100-2, the array chip 100-3, and the array chip 100-4 of the stacked chip 901 includes a first end portion. Compared with the first end portion of the upper wafer, the first end portion of the lower wafer protrudes in the first direction. The first end portion is electrically connected to the circuit board 600 by the wire 500.

Each of the circuit chip 700-2, the array chip 100-6, the array chip 100-7, and the array chip 100-8 of the stacked chip 902 includes a second end portion. Compared with the second end portion of the upper wafer, the second end portion of the lower wafer protrudes in a second direction opposite to the first direction. The second end portion is electrically connected to the circuit board 600 by the wire 500.

As shown in FIG. 24A, the array chips 100-2, 100-3, and 100-4 of the stacked chip 901 can be connected to each other by wires 500. The circuit chip 700-1 can be connected to the array chip 100-2 by wires 500. The circuit chip 700-1 can be connected to the circuit board 600 by wires 500. The array chips 100-6, 100-7, and 100-8 of the stacked chip 902 can be connected to each other by wires 500. The circuit chip 700-2 can be connected to the array chip 100-6 by wires 500. The circuit chip 700-2 can be connected to the circuit board 600 by wires 500.

As shown in FIG. 24B, the array chip 100-2 shown in FIG. 24A can be replaced with a circuit chip 700-3. The array chip 100-3 shown in FIG. 24A can be replaced with a circuit chip 700-4. The array chip 100-4 shown in FIG. 24A can be replaced with a circuit chip 700-5. The array chip 100-6 shown in FIG. 24A can be replaced with a circuit chip 700-6. The array chip 100-7 shown in FIG. 24A can be replaced with a circuit chip 700-8.

FIG. 25 is a schematic cross-sectional view of the circuit chip 700. As shown in FIG. The same components as those in FIG. 11 are denoted by the same reference numerals and signs.

The circuit chip 700 includes an array chip 100 and a circuit chip (or CMOS chip) 200. The array chip 100 is bonded to the circuit chip 200 by bonding metal 74a.

The array chip 100 includes a memory cell array 1.

The circuit chip 200 includes a substrate 5, and a control circuit 401 and an SSD controller 402 arranged on the substrate 5. Each of the control circuit 401 and the SSD controller 402 includes a plurality of transistors 77 and an interconnection layer 76.

The interconnection layer 76 of the control circuit 401 is electrically connected to the interconnection layer 73 of the array chip 100 by the bonding metal 74a.

The control circuit 401 and the SSD controller 402 are electrically connected to each other through the interconnection layer of the circuit chip 200.

FIG. 26 is a block diagram of the circuit chip 700. As shown in FIG.

The circuit chip 700 includes an array chip 100, a control circuit 401, and an SSD controller 402. The control circuit 401 is connected to the input-output (I/O) part of the array chip 100. The SSD controller 402 is connected to the external host system 900. The control circuit 401 and the SSD controller 402 are connected to each other via the data bus 910 and the control bus 920.

The SSD controller 402 includes a host IF (interface) 711, a host IF controller 712, a host command controller 713, a wear leveling controller 714, a NAND block manager 715, a memory location manager 716, a data buffer controller 718, A data buffer 717, a cryptographic module 719, and an error correction code (ECC) processor 720.

The host IF 711 is connected to the host system 900, the data bus 910 and the control bus 920. Host IF controller 712, host command controller 713, wear leveling controller 714, NAND block manager 715, memory location manager 716, data buffer 717, cryptographic module 719, and ECC processor 720 are connected to the control bus 920. The data buffer controller 718, the cryptographic module 719 and the ECC processor 720 are connected to the data bus 910.

The host IF 711 is an interface such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), and high-speed peripheral interconnection/high-speed non-volatile memory (PCIe/NVMe).

The host IF controller 712 controls the host IF 711.

The host command controller 713 interprets the processing request or command (READ, WRITE) received from the host system 900 via the host IF 711, and controls another element in the storage device to fulfill the request.

The data buffer 717 temporarily stores data written from the host system 900 and data read from NAND. The data buffer 717 is, for example, a memory (SRAM, DRAM) or a register. Storage memory is volatile or non-volatile.

The data buffer controller 718 manages the data buffer 717. The data buffer controller 718 manages the use of the data buffer 717 (for example, data in use or free data). The data buffer controller 718 manages which buffer the data is written in which area and which NAND correspondence.

The ECC processor 720 encodes the data to be written to NAND, decodes the data read from NAND, and detects and corrects errors.

The NAND block manager 715 manages the use of NAND blocks. The NAND block manager 715 also manages bad blocks.

The wear leveling controller 714 manages exhaustion. The wear leveling controller 714 monitors the entire NAND and controls it so that the exhaustion of a specific block does not develop too much. The wear leveling controller 714 controls the processing of read disturbance and data retention.

The memory location manager 716 converts so-called logical addresses between physical addresses. When an access between the addresses of the NAND is requested, the memory location manager 716 converts the address specified by the host system 900. The memory location manager 716 determines which NAND area to write the WRITE data to when receiving the WRITE command from the host system 900.

The cryptographic module 719 performs various cryptographic processing on the data.

The control circuit 401 includes a power controller 721, a memory controller 725, an address register 722, a command register 723, a status register 724, a column decoder 726, a row decoder 727, a data cache memory 728 and Sense amplifier 729.

The power controller 721 is connected to the host system 900. The memory controller 725, the address register 722, the command register 723, and the status register 724 are connected to the control bus 920. The row decoder 727 is connected to the data bus 910. The column decoder 726, the row decoder 727, the data cache 728 and the sense amplifier 729 are connected to the memory controller 725. The power controller 721, the column decoder 726 and the sense amplifier 729 are connected to the input/output of the array chip 100.

The column decoder 726 controls the potentials of the electrode layer WL, the drain side selection gate SGD, and the source side selection gate SGS of the memory cell array 1. The sense amplifier 729 reads and amplifies the potential of the bit line BL.

The data writing procedure is described below.

The memory controller 725 receives the write request from the memory location manager 716. When the received write request cannot be executed immediately, the memory controller 725 records the address in the address register 722 and records the command in the command register 723.

When the writing process is involved, the memory controller 725 notifies the data to be written into the data buffer 717. The data is read from the data buffer 717, and the data is encrypted in the encryption module 719. Subsequently, error correction is performed on the data in the ECC processor 720.

Send the encoded data to the data cache 728 and wait until writing starts. After preparation, the data is transferred from the data cache 728 to the array chip 100 and written into the memory cell.

After the program is written, the memory controller 725 reflects the result in the status register 724.

Next, the data reading procedure is described below.

The memory location manager 716 instructs the memory controller 725 to read the data. When the received read request cannot be executed immediately, the memory controller 725 records the address in the address register 722 and records the command in the command register 723.

When it comes to reading processing, the sense amplifier 729 reads data from the memory cell of the array chip 100 and stores the data in the data cache 728.

The memory controller 725 queries the data buffer 717 where the read data should be sent. The data stored in the data cache 728 is sent to the ECC processor 720, and ECC is executed on the data. The corrected data is decrypted in the cryptographic module 719. The decrypted data is stored in the data buffer 717.

The memory controller 725 reflects the end of the reading process in the status register 724. The host command controller 713 instructs the host IF controller 712 to transfer data. Then, the data is transferred from the data buffer 717 to the host system 900.

FIG. 27 is a block diagram of the stacked chip 901 shown in FIG. 20.

The stacked chip 901 includes a circuit chip 700 and a plurality of array chips 100-2, 100-3, and 100-4. The circuit chip 700 is a combined control circuit chip, and includes an SSD controller 402, an array chip 100-1, and control circuits 401-1, 401-2, 401-3, and 401-4. The control circuits 401-1, 401-2, 401-3, and 401-4 include the same components as the control circuit 401 described above.

The control circuit 401-1 is connected to the array chip 100-1. The control circuit 401-2 is connected to the array chip 100-2. The control circuit 401-3 is connected to the array chip 100-3. The control circuit 401-4 is connected to the array chip 100-4.

The array chips 100-1, 100-2, 100-3, and 100-4 are connected to the power supply 15 by wires.

The control circuit 401-2 is connected to the array chip 100-2 by wires or through silicon vias (TSV). The control circuit 401-3 is connected to the array chip 100-3 by wires or TSVs. The control circuit 401-4 is connected to the array chip 100-4 by wires or TSVs.

The SSD controller 402 is connected to the host system 900 by wires.

As shown in FIG. 28, the circuit chip 700 may include a plurality of SSD controllers 402-1, 402-2, 402-3, and 402-4.

The SSD controller 402-1 is connected to the control circuit 401-1. The SSD controller 402-2 is connected to the control circuit 401-2. The SSD controller 402-3 is connected to the control circuit 401-3. The SSD controller 402-4 is connected to the control circuit 401-4.

According to the structure of FIG. 28, the elements that control each array chip 100-1, 100-2, 100-3, and 100-4 are separated. Compared with the structure of FIG. 27, this structure can improve performance.

Compared with the structure of FIG. 28, the structure of FIG. 27 can reduce the circuit area and power consumption.

Fig. 29 is a block diagram of the stacked chip shown in Fig. 23A.

The circuit chip 700-1 includes an SSD controller 402-1, a control circuit 401-1, and an array chip 100-1.

The circuit chip 700-2 includes an SSD controller 402-2, a control circuit 401-2, and an array chip 100-2.

The circuit chip 700-3 includes an SSD controller 402-3, a control circuit 401-3, and an array chip 100-3.

The circuit chip 700-4 includes an SSD controller 402-4, a control circuit 401-4, and an array chip 100-4.

The SSD controllers 402-1, 402-2, 402-3, and 402-4 are connected to the host system 900 by wires.

The array chips 100-1, 100-2, 100-3, and 100-4 are connected to the power supply 15 by wires.

According to the structure of FIG. 29, the SSD controllers 402-1, 402-2, 402-3, and 402-4 are connected to the host system 900 by wires.

Alternatively, as shown in FIG. 30, each of the SSD controllers 402-1, 402-2, 402-3, and 402-4 may be connected to the host system 900 by a separate interconnection line.

FIG. 31 is a block diagram of the stacked chip 901 shown in FIG. 23B.

FIG. 32 is a block diagram of the stacked chip 902 shown in FIG. 23B.

As shown in FIG. 31, the circuit chip 700-1 of the stacked chip 901 includes an SSD controller 402-1, control circuits 401-1, 401-2, 401-3, 401-4, and an array chip 100-1.

The SSD controller 402-1 is connected to the host system 900A.

The control circuit 401-1 is connected to the array chip 100-1. The control circuit 401-2 is connected to the array chip 100-2. The control circuit 401-3 is connected to the array chip 100-3. The control circuit 401-4 is connected to the array chip 100-4.

As shown in FIG. 32, the circuit chip 700-2 of the stacked chip 902 includes an SSD controller 402-2, control circuits 401-5, 401-6, 401-7, 401-8, and an array chip 100-5.

The SSD controller 402-2 is connected to the host system 900B.

The control circuit 401-5 is connected to the array chip 100-5. The control circuit 401-6 is connected to the array chip 100-6. The control circuit 401-7 is connected to the array chip 100-7. The control circuit 401-8 is connected to the array chip 100-8.

The array chips 100-2, 100-3, 100-4, 100-6, 100-7, and 100-8 are connected to the power supply 15 by wires.

The SSD controller 402-1 and the SSD controller 402-2 can be wired or connected to the same host system.

Fig. 33 is a schematic diagram of a modification of Fig. 21A and Fig. 21B.

A plurality of pads 705 for NAND I/F are arranged at the end portion of the circuit chip 700 in the X direction. The pad 705 for the NAND I/F is connected to the pad 101 of the array chip 100-2, 100-3, 100-4 by a wire 500.

A plurality of pads 706 for the host are arranged at the end portion of the circuit chip 700 in the Y direction. The pad 706 for the host is connected to the pad of the circuit board 600 by a wire 500.

According to the structure of FIG. 33, the end portion (side) of the circuit chip 700 in which the pad 705 for NAND I/F is placed is different from the end portion (side) of the circuit chip 700 in which the pad 706 for the host is placed. This structure can reduce the arrangement pitch and area of the pad 705 for the NAND I/F and the pad 706 for the host.

Since the array chips 100-2, 100-3, and 100-4 are stacked in a step configuration, the end portions (sides) of the pads 101 on which the array chips 100-2, 100-3, and 100-4 are placed are affected by the size of the package. Strict restrictions. This may limit the layout rules of the pads on the circuit board 600. In the structure of FIG. 33, the end portion (side) of the pad 101 on which the array chips 100-2, 100-3, and 100-4 are placed is different from the end portion (side) of the connection circuit board 600. This structure can be easily restricted according to the above-mentioned rules.

Although certain embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present invention. In fact, the novel embodiments described herein can be embodied in many other forms; in addition, various omissions, substitutions and changes can be made to the forms of the embodiments described herein without departing from the spirit of the present invention. The scope of the attached patent application and its equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present invention.

Cross reference of related applications This application is based on the U.S. Partial Continuation Patent Application No. 16/121,123 filed on September 4, 2018 and the U.S. Partial Continuation Patent Application No. 16/409,637 filed on May 10, 2019, and claims the aforementioned U.S. Part The priority of the continuation patent application; the entire content of the aforementioned US partial continuation patent application is incorporated herein by reference.

1: Memory cell array 2: Memory cell array 5: Substrate 10: substrate 15: power supply 20: Channel body 30: memory film 31: Tunnel insulation film 32: charge storage film 33: barrier film 34: Cover film 35: barrier insulating film 40: Insulation layer 43: Interlayer insulation layer 44: Insulation layer 45: silicon nitride film 46: Insulation separation film 47: Insulation separation film 48: Silicon oxide film 49: protective film 50: Core insulation film 51: Insulating film 52: Insulating film 61: contact plug 62: word interconnection layer 63: contact plug 64: back gate interconnect layer 65: contact plug 66: Select gate interconnection layer 67: plug 69: Interlayer insulation 70: pad 71: External connection electrode 72: External connection pad 73: Surface layer interconnection layer 74: Metal 74a: Bonding metal 74b: Bonding metal 75: insulating film 76: circuit side interconnection layer 77: Transistor 78: gate electrode 79: plug 80: Interlayer insulation layer 81: Memory cell array area 91: The first bonding metal 92: first insulating film 93: The second bonding metal 94: second insulating film 95: Through hole 96: Stepped structure section 100: Array chip 100-2: Array chip 100-3: Array chip 100-4: Array chip 100-5: Array chip 100-6: Array chip 100-7: Array chip 100-8: Array chip 101: pad 102: Conductive ball/bump 110: layer 111: pad 112: External connection electrode 120: Through hole 121: External connection electrode 122: pad 123: Conductive body 200: circuit chip 210: I/O control circuit 211: Logic Control Circuit 212: Status register 213: Address register 214: Command register 215: control circuit 216: Ready/Busy Circuit 217: Voltage Generator 219: column decoder 220: sense amplifier 221: data register 222: Line decoder 300: Semiconductor memory device 301: Encapsulation 302: Conductive ball 400: Combination control circuit chip 401: control circuit 401-1: Control circuit 401-2: Control circuit 401-3: Control circuit 401-4: Control circuit 401-5: Control circuit 401-6: Control circuit 401-7: control circuit 401-8: control circuit 402: Solid State Drive (SSD) Controller 402-1: Solid State Drive (SSD) Controller 402-2: Solid State Drive (SSD) Controller 402-3: Solid State Drive (SSD) Controller 402-4: Solid State Drive (SSD) Controller 500: Wire 500a: bump 600: Wiring board 601: Electrode 602: conductive ball or pad 603: Passive Device 700: circuit chip 700-1: circuit chip 700-2: circuit chip 700-3: circuit chip 700-4: circuit chip 700-5: circuit chip 700-6: circuit chip 700-8: circuit chip 701: pad 702: pad / conductive ball 705: pad 706: Pad 711: Host IF 712: host IF controller 713: Host Command Controller 714: Loss Level Controller 715: NAND block manager 716: Memory Location Manager 717: data buffer 718: Data Buffer Controller 719: Password Module 720: Error Correcting Code (ECC) processor 721: Power Controller 722: Address Register 723: Command Register 724: Status Register 725: Memory Controller 726: column decoder 727: Line Decoder 728: Data Cache 729: Sense Amplifier 800: Semiconductor memory system 801: Package 802: Conductive ball 900: External host system 900A: host system 900B: host system 901: Stacking device/stacking chip 902: Stacked Chips 910: data bus 920: control bus ALE-0: Address latch enable signal BCE-0: Chip enable signal BG: back gate BGT: back gate transistor BL: bit line BRE-0: Read enable signal RE-0 BWE-0: Write enable signal CL: columnar section CLE-0: Command latch enable signal DQ0-0: data line DQ7-0: data line I/O＜O＞: 8-bit input/output signal I/O<7>: 8-bit input/output signal JP: Connection section MC: Memory unit MS: memory string RE-0: Read enable signal SL: source layer SG: Select gate SGD: Drain side selector gate SGS: Source side select gate layer STD: Select the transistor on the drain side STS: Source-side select transistor W1: Array wafer W2: circuit wafer WL: Multiple electrode layers

FIG. 1 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment; 2 is a schematic plan view showing an example of the layout of the bonding metal of the semiconductor memory device of the first embodiment; 3 is a schematic perspective view of the memory cell array of the first embodiment; 4 is a schematic cross-sectional view of the memory string of the first embodiment; 5 is a schematic cross-sectional view of the memory unit of the first embodiment; 6 and 7 are schematic cross-sectional views showing the method for manufacturing the semiconductor memory device of the first embodiment; 8 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment; 9 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment; 10 is a schematic perspective view of the memory cell array of the first embodiment; 11 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment; 12 is a schematic enlarged cross-sectional view of the wire bonding part of the semiconductor memory device of the first embodiment; 13A and 13B are schematic enlarged cross-sectional views of the wire bonding portion of the semiconductor memory device of the first embodiment; 14 is a scanning electron microscope (SEM) image of the semiconductor memory device of the first embodiment; 15 is a block diagram of the semiconductor memory device of the first embodiment; 16 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment; 17 is a schematic plan view showing the BGA (or LGA) pin assignment of the semiconductor memory device of the first embodiment; 18 is a schematic cross-sectional view of the semiconductor memory system of the second embodiment; 19 is a schematic plan view of the integrated control circuit chip of the semiconductor memory system of the second embodiment; 20 is a schematic diagram of the semiconductor memory device of the third embodiment; 21A and 21B are schematic plan views of the semiconductor memory device shown in FIG. 20; 22A to 24B are schematic diagrams of another example of the semiconductor memory device of the third embodiment; FIG. 25 is a schematic cross-sectional view of the circuit chip 700; FIG. 26 is a block diagram of the circuit chip 700; 27 and 28 are block diagrams of the stacked chip 901 shown in FIG. 20; 29 and 30 are block diagrams of the stacked chips shown in FIG. 23A; FIG. 31 is a block diagram of the stacked chip 901 shown in FIG. 23B; FIG. 32 is a block diagram of the stacked chip 902 shown in FIG. 23B; and Fig. 33 is a schematic diagram of a modification of Figs. 21A and 21B.

1: Memory cell array

5: Substrate

45: silicon nitride film

48: Silicon oxide film

61: contact plug

62: word interconnection layer

63: contact plug

64: back gate interconnect layer

65: contact plug

66: Select gate interconnection layer

67: plug

69: Interlayer insulation

70: pad

71: External connection electrode

72: External connection pad

73: Surface layer interconnection layer

74a: Bonding metal

74b: Bonding metal

75: insulating film

76: circuit side interconnection layer

77: Transistor

78: gate electrode

79: plug

80: Interlayer insulation layer

81: Memory cell array area

96: Stepped structure section

100: Array chip

200: circuit chip

BG: back gate

BL: bit line

CL: columnar section

SG: Select gate

WL: Multiple electrode layers

Claims (20)

A semiconductor memory device, which includes: An array chip including a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells, and the array chip does not include a substrate; A circuit chip including a substrate, a control circuit disposed on the substrate, and a circuit-side interconnect layer disposed on the control circuit and connected to the control circuit, the circuit chip being pasted To the array chip, wherein the circuit-side interconnection layer faces the memory-side interconnection layer; A bonding metal, the bonding metal is disposed between the memory-side interconnection layer and the circuit-side interconnection layer, and is bonded to the memory-side interconnection layer and the circuit-side interconnection layer; A pad, the pad is arranged in the array chip; and An external connection electrode, which reaches the pad from a surface side of the array chip. Such as the semiconductor memory device of claim 1, wherein The array chip includes: A stacked body including a plurality of electrode layers stacked via an insulating layer; A semiconductor body extending in one of the stacking directions of the stacking body in the stacking body; A charge storage film, the charge storage film is disposed between the semiconductor body and the electrode layers; A plurality of bit lines, the plurality of bit lines are connected to an end portion of the semiconductor body; and A source line connected to the other end portion of the semiconductor body. Such as the semiconductor memory device of claim 2, wherein The electrode layers are formed in a stepped shape at an end of a memory cell array area where the memory cells are arranged, and The memory-side interconnection layer includes a word interconnection layer connected to the electrode layers formed in the step shape. Such as the semiconductor memory device of claim 3, wherein The bonding metal includes a plurality of bit line lead-out sections electrically connected to the bit lines, and The bit line lead-out sections are arranged in an area overlapping the memory cell array area along the stacking direction. Such as the semiconductor memory device of claim 3, wherein The bonding metal includes a plurality of word line lead-out sections electrically connected to the word interconnect layers, and The pad is arranged in an area that overlaps the word line lead-out sections along the stacking direction. The semiconductor memory device of claim 2, wherein the pad is provided in the same layer as the source line, and is formed of the same material as the source line. The semiconductor memory device of claim 3, wherein the pad is arranged in the same layer as the word interconnection layer, and is formed of the same material as the word interconnection layer. Such as the semiconductor memory device of claim 2, wherein A gate layer is disposed in a layer of the stacked body on an opposite side of the memory-side interconnection layer, and The pad is formed in the same layer as the gate layer, and is formed of the same material as the gate layer. The semiconductor memory device of claim 1, further comprising an insulating film disposed around the bonding metal. A semiconductor memory device, which includes: An array chip including a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells, and the array chip does not include a substrate; A circuit chip including a substrate, a control circuit disposed on the substrate, and a circuit-side interconnect layer disposed on the control circuit and connected to the control circuit, the circuit chip being pasted To the array chip, wherein the circuit-side interconnection layer faces the memory-side interconnection layer; A bonding metal, the bonding metal is disposed between the memory-side interconnection layer and the circuit-side interconnection layer, and is bonded to the memory-side interconnection layer and the circuit-side interconnection layer; A pad, the pad is arranged in the circuit chip; and An external connection electrode, which reaches the pad from a surface side of the array chip. Such as the semiconductor memory device of claim 10, wherein The array chip includes: A stacked body including a plurality of electrode layers stacked via an insulating layer; A semiconductor body extending in one of the stacking directions of the stacking body in the stacking body; A charge storage film, the charge storage film is disposed between the semiconductor body and the electrode layers; A plurality of bit lines, the plurality of bit lines are connected to an end portion of the semiconductor body; and A source line connected to the other end portion of the semiconductor body. Such as the semiconductor memory device of claim 11, wherein The electrode layers are formed in a stepped shape at an end of a memory cell array area where the memory cells are arranged, and The memory-side interconnection layer includes a zigzag interconnection layer connected to the electrode layers formed in the step shape. Such as the semiconductor memory device of claim 12, wherein The bonding metal includes a plurality of bit line lead-out sections electrically connected to the bit lines, and The bit line lead-out sections are arranged in an area overlapping the memory cell array area along the stacking direction. The semiconductor memory device of claim 10, wherein the pad is provided in the same layer as the circuit-side interconnection layer, and is formed of the same material as the circuit-side interconnection layer. The semiconductor memory device of claim 10, further comprising an insulating film disposed around the bonding metal. A semiconductor memory device, which includes: An array chip including a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells, and the array chip does not include a substrate; A circuit chip including a substrate, a control circuit arranged on the substrate, and a circuit-side interconnect layer arranged on the control circuit and connected to the control circuit, the circuit chip being pasted To the array chip, wherein the circuit-side interconnection layer faces the memory-side interconnection layer; A bonding metal, the bonding metal is disposed between the memory-side interconnection layer and the circuit-side interconnection layer, and is bonded to the memory-side interconnection layer and the circuit-side interconnection layer; The circuit chip includes a pad, and The array chip includes a through hole that penetrates the array chip and reaches the pad. Such as the semiconductor memory device of claim 16, wherein The stacks each include the array chip, the circuit chip, and a plurality of semiconductor memory chips of bonding metal, Each of the semiconductor memory chips includes an end portion along one side of the semiconductor memory chip, and A plurality of the pads and a plurality of the through holes are arranged in the end portion along the one side. The semiconductor memory device of claim 16, wherein the circuit chip is a combined control circuit chip, which includes the control circuit and a solid-state drive controller. A semiconductor memory device, which includes: An array chip including a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells, and the array chip does not include a substrate; A circuit chip including a substrate, a control circuit disposed on the substrate, a solid-state drive controller disposed on the substrate, and a circuit-side interconnection layer, the circuit chip being bonded to the An array chip, wherein the circuit-side interconnection layer faces the memory-side interconnection layer; and A bonding metal, the bonding metal is disposed between the memory-side interconnection layer and the circuit-side interconnection layer, and is bonded to the memory-side interconnection layer and the circuit-side interconnection layer; The control circuit is connected to the memory-side interconnection layer through the circuit-side interconnection layer and the bonding metal, The control circuit is connected to the solid-state drive controller through the circuit-side interconnection layer. Such as the semiconductor memory device of claim 19, wherein The array chip includes a plurality of semiconductor bodies, a plurality of electrode layers facing the semiconductor bodies, and a plurality of bit lines connected to the semiconductor bodies, The control circuit includes a column decoder that controls the potentials of the electrode layers, and a sense amplifier that senses and amplifies the potentials of the bit lines.

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