TWI723248B - Synchronization sequence sending method, synchronization detection method and device - Google Patents

Abstract

The present invention provides a synchronization sequence transmission method, synchronization detection method and device. The transmission method includes: setting a target synchronization sequence with good autocorrelation characteristics; wherein the target synchronization sequence is intercepted in the time domain or the frequency domain At least one segment of the sequence is a sub-synchronization sequence, the sub-synchronization sequence has good autocorrelation characteristics and the sub-synchronization sequences have good cross-correlation characteristics; the target synchronization sequence is sent to the terminal.

Description

Synchronization sequence sending method, synchronization detection method and device

The present invention belongs to the field of communication technology, and particularly refers to a method for sending a synchronization sequence, a method and device for synchronization detection.

In the 5G system, due to the need to support the multi-beam system, the synchronization sequence has a longer period. In order to reduce the delay of synchronization detection, it is necessary to improve the accuracy of one detection as much as possible; for this reason, the synchronization sequence should be as long as possible, and the frequency should be as long as possible. In terms of domain, the bandwidth of the synchronization sequence should be as wide as possible. In 5G communication, the user's system bandwidth will range from 180k to 80M. In the same frequency band, different users will have different working bandwidths. In order to ensure the performance of one detection and support users of different bandwidths, the synchronization sequence needs to be able to work under different bandwidths, that is, in the frequency domain, the synchronization sequence is intercepted, and the synchronization sequence can still have good autocorrelation and mutual correlation. Related features.

In addition, when the user is moving at a high speed, in order to ensure synchronization detection accuracy, the synchronization signal should have a higher carrier interval, but when the total bandwidth remains the same, the higher carrier interval reduces the length of the synchronization sequence. Therefore, it is necessary to design a synchronization sequence to support different carrier spacing.

However, the synchronization sequence in the existing Long Term Evolution (LTE) system does not support the use of a synchronization sequence after bandwidth interception, nor does it support synchronization sequences with different carrier intervals.

The purpose of the present invention is to provide a synchronization sequence sending method, synchronization detection method and device, which solves the problem that the sequence length and the bandwidth width of the synchronization sequence in the related art are mutually restricted, resulting in low detection accuracy.

In order to achieve the above objective, an embodiment of the present invention provides a method for sending a synchronization sequence, including: setting a target synchronization sequence; wherein at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a synchronization sequence; The target synchronization sequence is sent to the terminal.

Optionally, the step of setting the target synchronization sequence includes: obtaining a reference synchronization sequence; and rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence.

Optionally, if the reference synchronization sequence is a generalized chirp-like sequence, and the sequence length of the ZC sequence is an even number, the multiple sequence points of the reference synchronization sequence are rearranged according to a preset rule to obtain the target synchronization sequence The steps include: extracting the sequence points of the reference synchronization sequence at equal intervals, and placing the extracted sequence points consecutively to obtain the target synchronization sequence.

Optionally, the step of extracting the sequence points of the reference synchronization sequence at equal intervals, and successively placing the extracted sequence points to obtain the target synchronization sequence includes: extracting the even-numbered sequence points and the odd-numbered sequence points of the reference synchronization sequence respectively; The even-numbered sequence points are divided into a plurality of first short sequences, and the odd-numbered sequence points are divided into a plurality of second short sequences; wherein, the first short sequence contains a plurality of consecutive even-numbered sequence points, and the second short sequence The sequence includes a plurality of consecutive odd sequence points; the plurality of first short sequences and the plurality of second short sequences are arranged in a preset order to obtain a target synchronization sequence.

Optionally, the step of arranging the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain the target synchronization sequence includes: alternately placing the first short sequence and the second short sequence , Get the target synchronization sequence.

Optionally, if the result obtained by dividing the sequence length of the reference synchronization sequence by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the sequence length of the reference synchronization sequence is divided by 4, the result obtained is an odd number When, the plurality of second short sequences are ZC sequences.

Optionally, if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number, and the sequence length is equal to the square of N; the multiple sequence points of the reference synchronization sequence are rearranged according to a preset rule, The step of obtaining the target synchronization sequence includes: starting from the 0th sequence point of the reference synchronization sequence, extracting a target sequence point from every N consecutive sequence points; and placing the extracted target sequence points consecutively in the reference synchronization sequence The preset position of the sequence to obtain the target synchronization sequence; where N is an integer greater than or equal to 3.

Optionally, the preset position is a position starting from an integer multiple of N.

Optionally, if the sequence length of the ZC sequence is an integer multiple of X, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a section X of the target synchronization sequence And the sub-synchronization sequence is a ZC sequence; where X is an integer greater than or equal to 2.

Optionally, if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the step of rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence, Including: intercepting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence respectively; placing the even-numbered sequence points of the reference synchronization sequence before the odd-numbered sequence points of the reference synchronization sequence to obtain a rearrangement sequence; or The odd-numbered sequence points are placed before the even-numbered sequence points of the reference synchronization sequence to obtain the rearrangement sequence; the rearrangement sequence is respectively mapped to each subcarrier in the frequency domain, and the target synchronization sequence is obtained after inverse Fourier transform.

Optionally, the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, and the second quarter segment of the target synchronization sequence , The sequence of the third quarter segment of the target synchronization sequence, and/or the sequence of the fourth quarter segment of the target sequence, and the sub-synchronization sequence is a ZC sequence.

An embodiment of the present invention also provides a synchronization detection method, which includes: receiving a target synchronization sequence sent by a base station; and performing synchronization detection according to the target synchronization sequence.

Optionally, the step of performing synchronization detection based on the target synchronization sequence includes: intercepting a sequence in the time domain or frequency domain of the target synchronization sequence as a synchronization sequence; performing synchronization detection based on the intercepted synchronization sequence.

Optionally, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the synchronization sequence intercepted in the time domain or frequency domain of the target synchronization sequence is one or the other contained in the target synchronization sequence. A plurality of first short sequences and/or one or more second short sequences; wherein, the first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.

Optionally, the step of performing synchronization detection according to the target synchronization sequence includes: using a preset synchronization sequence to perform correlation processing on the target synchronization sequence; and determining the base station to send the target synchronization sequence according to the number of correlation peaks obtained by the correlation processing The interval of subcarriers; Perform synchronization detection according to the interval of subcarriers and the intercepted synchronization sequence.

Optionally, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, the synchronization sequence intercepted in the time domain of the target synchronization sequence is the target synchronization sequence A sequence of one segment of X, and the intercepted synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence is an integer multiple of X, and X is an integer greater than or equal to 2.

Optionally, the step of performing synchronization detection based on the intercepted synchronization sequence includes: raising the intercepted synchronization sequence to the power of p to obtain the sequence to be detected; where p is an integer greater than or equal to 2; The detection sequence performs synchronous detection.

The embodiment of the present invention also provides a synchronization sequence sending device, including: The sequence setting module is used to set the target synchronization sequence; wherein at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a synchronization sequence; the sequence sending module is used to send the target synchronization sequence to terminal.

Optionally, the sequence setting module includes: a reference acquisition module for acquiring a reference synchronization sequence; a rearrangement module for rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain Target synchronization sequence.

Optionally, the rearrangement module includes: a first rearrangement sub-module, configured to extract the reference synchronization sequence at equal intervals if the reference synchronization sequence is a ZC sequence and the sequence length of the ZC sequence is an even number Place the extracted sequence points consecutively to obtain the target synchronization sequence.

Optionally, the first rearrangement submodule includes: a first extraction unit, configured to extract even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence, respectively; a first division unit, configured to divide the even-numbered sequence points into Multiple first short sequences, and divide the odd sequence points into multiple second short sequences; wherein, the first short sequence contains multiple consecutive even sequence points, and the second short sequence contains multiple consecutive Odd sequence points; a rearrangement unit for arranging the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain a target synchronization sequence.

Optionally, the rearrangement unit includes: a rearrangement subunit, configured to alternately place the first short sequence and the second short sequence to obtain the target synchronization sequence.

Optionally, if the result obtained by dividing the sequence length of the reference synchronization sequence by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the sequence length of the reference synchronization sequence is divided by 4, the result obtained is an odd number When, the plurality of second short sequences are ZC sequences.

Optionally, the rearrangement module includes: an extraction sub-module for synchronizing from the reference if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number, and the sequence length is equal to the square of N Starting from the 0th sequence point of the sequence, a target sequence point is extracted from every N consecutive sequence points; the second rearrangement sub-module is used to continuously place the extracted target sequence point in the preset reference synchronization sequence. Set the position to obtain the target synchronization sequence; where N is an integer greater than or equal to 3.

Optionally, the preset position is a position starting from an integer multiple of N.

Optionally, if the sequence length of the ZC sequence is an integer multiple of X, the synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of a segment X of the target synchronization sequence, and the intercepted synchronization sequence The synchronization sequence is a ZC sequence; where X is an integer greater than or equal to 2.

Optionally, the rearrangement module includes: a second intercepting sub-module, configured to intercept the even-numbered sequence points of the reference synchronization sequence if the reference synchronization sequence is a ZC sequence and the sequence length of the ZC sequence is an even number And odd sequence points; the third rearrangement submodule is used to place the even sequence points of the reference synchronization sequence before the odd sequence points of the reference synchronization sequence to obtain the rearrangement sequence; or the odd sequence of the reference synchronization sequence The point is placed before the even-numbered sequence point of the reference synchronization sequence to obtain the rearrangement sequence; the frequency domain mapping sub-module is used to map the rearrangement sequence to each subcarrier in the frequency domain, And after inverse Fourier transform, the target synchronization sequence is obtained.

Optionally, the synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, and the sequence of the second quarter segment of the target synchronization sequence. Sequence, the sequence of the third quarter segment of the target synchronization sequence and/or the sequence of the fourth quarter segment of the target sequence, and the intercepted synchronization sequence is a ZC sequence.

An embodiment of the present invention also provides a synchronization detection device, which includes: a sequence receiving module for receiving a target synchronization sequence sent by a base station; and a detection module for performing synchronization detection according to the target synchronization sequence.

Optionally, the detection module includes: an interception sub-module for intercepting a sequence in the time domain or frequency domain of the target synchronization sequence as a synchronization sequence; and the detection sub-module for performing processing according to the intercepted synchronization sequence Synchronous detection.

Optionally, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the synchronization sequence intercepted in the time domain or frequency domain of the target synchronization sequence is one or the other contained in the target synchronization sequence. A plurality of first short sequences and/or one or more second short sequences; wherein, the first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.

Optionally, the detection module includes: a correlation processing sub-module for performing correlation processing on the target synchronization sequence using a preset synchronization sequence; an interval determination sub-module for performing correlation processing based on the number of correlation peaks obtained by the correlation processing , Determine the base The sub-carrier interval of the target synchronization sequence sent by the station; the synchronization detection sub-module is used to perform synchronization detection according to the sub-carrier interval and the intercepted synchronization sequence.

Optionally, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, the synchronization sequence intercepted in the time domain of the target synchronization sequence is the target synchronization sequence A sequence of one segment of X, and the intercepted synchronization sequence is a ZC sequence; wherein, the sequence length of the ZC sequence is an integer multiple of X, and X is an integer greater than or equal to 2.

Optionally, the detection sub-module includes: a preprocessing module, which is used to power the intercepted synchronization sequence to the power of p to obtain the sequence to be detected; where p is an integer greater than or equal to 2; and the detection unit is used to Perform synchronization detection according to the sequence to be detected.

The embodiment of the present invention also provides a synchronization sequence sending device, including: a processor, a memory, and a transceiver, where: the processor is used to read a program in the memory and execute the following process: setting a target synchronization sequence; At least one segment of the target synchronization sequence intercepted in the time domain or frequency domain is a synchronization sequence; the target synchronization sequence is sent to the terminal through the transceiver, the transceiver is used to receive and send data, and the memory can store and process The data used by the device when performing operations.

The embodiment of the present invention also provides a synchronization detection device, including: a processor, a memory, and a transceiver, wherein: The processor is used to read the program in the memory and perform the following process: receive the target synchronization sequence sent by the base station through the transceiver; perform synchronization detection according to the target synchronization sequence, the transceiver is used to receive and send data, the memory The body can store the data used by the processor when performing operations.

The above technical solution of the present invention has at least the following advantages: in the synchronization sequence sending method, synchronization detection method and device of the embodiment of the present invention, the base station side presets a target synchronization sequence with good autocorrelation characteristics, and the target synchronization sequence The sequence acquired in the time domain or frequency domain can still be used as a synchronization sequence, and the acquired sub-synchronization sequence has good autocorrelation characteristics and good cross-correlation characteristics; it is aimed at terminals with different bandwidths or different carrier intervals After the terminal and the base station side send the same target synchronization sequence, the terminal can intercept the corresponding sub-synchronization sequence to perform synchronization detection according to its own needs, which not only ensures the synchronization detection accuracy, but also improves the application range of the target synchronization sequence.

11~12、21~22‧‧‧Step

100‧‧‧Processor

110‧‧‧Transceiver

120‧‧‧Memory

31‧‧‧Sequence Setting Module

32‧‧‧Sequence sending module

51‧‧‧Serial Receiver Module

52‧‧‧Detection Module

In order to explain the technical solutions of the embodiments of the present invention more clearly, the following will briefly introduce the drawings used in the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without making progressive labor.

Figure 1 shows a flow chart of the steps of a method for sending a synchronization sequence provided in some embodiments of the present invention; Figure 2 shows a flowchart of the steps of a synchronization detection method provided in some embodiments of the present invention; Figure 3 shows a schematic structural diagram of a synchronization sequence sending device provided in some embodiments of the present invention; Figure 4 shows some of the present invention A schematic structural diagram of another synchronization sequence sending device and a synchronization detection device provided in the embodiments; and FIG. 5 shows a schematic structural diagram of another synchronization detection device provided in some embodiments of the present invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making progressive work fall within the protection scope of the present invention.

As shown in Figure 1, some embodiments of the present invention provide a synchronization sequence sending method, including: Step 11, setting a target synchronization sequence with good autocorrelation characteristics; wherein, in the time domain or frequency domain of the target synchronization sequence At least a segment of the sequence intercepted on the domain is a sub-synchronization sequence, the sub-synchronization sequence has good autocorrelation characteristics and the sub-synchronization sequences have good cross-correlation characteristics; step 12, the target synchronization sequence is sent to the terminal.

The above-mentioned embodiment of the present invention described with reference to FIG. 1 is applied to the base station side, and the base station side sets a target synchronization sequence, and the target synchronization sequence has good sub-correlation characteristics and cross-correlation characteristics. And if a sequence or multiple sequences intercepted according to preset rules in the time domain or frequency domain of the target synchronization sequence can also be used as a synchronization sequence, called a sub-synchronization sequence, this sub-synchronization sequence also has good autocorrelation characteristics and Cross-correlation characteristics.

Specifically, for terminals with different bandwidths or terminals with different carrier intervals, after the base station side sends the same target synchronization sequence, the terminal can intercept the corresponding sub-synchronization sequence according to its own needs to perform synchronization detection.

Further, step 11 in the above-mentioned embodiment described with reference to FIG. 1 of the present invention includes: step 111, obtaining a reference synchronization sequence with good autocorrelation characteristics; step 112, the number of the reference synchronization sequence according to a preset rule The sequence points are rearranged to obtain the target synchronization sequence with good autocorrelation characteristics.

Specifically, the preset rule can be specifically set according to the characteristics of the reference synchronization sequence; specifically, if the target synchronization sequence is a synchronization sequence that is not sensitive to carrier spacing, then at least one sequence is intercepted in the time domain of the target synchronization sequence It is a sub-synchronization sequence; and if the target synchronization sequence is a synchronization sequence that is not sensitive to the bandwidth, at least a segment of the sequence intercepted in the frequency domain of the target synchronization sequence is a sub-synchronization sequence.

The following separately describes the sub-synchronization sequence in the time domain and the sub-synchronization sequence in the frequency domain: First, the case that the sequence intercepted in the time domain of the target synchronization sequence is a sub-synchronization sequence is described: Two cases: the first type, the reference synchronization sequence is a ZC sequence, and the ZC sequence The sequence length of is an even number. The second type of reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is odd and the sequence length is equal to the square of N; among them, the Chinese name of the ZC (Zadoff-Chu) sequence is: Generalized 啁Chirp sequence.

In the first case, if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, step 112 includes: Step 1123: extract the sequence points of the reference synchronization sequence at equal intervals, and extract the sequence points of the reference synchronization sequence. The sequence points are placed continuously to obtain a target synchronization sequence with good autocorrelation characteristics.

Further step 1123 includes: step 11231, respectively extracting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence; step 11232, dividing the even-numbered sequence points into a plurality of first short sequences, and dividing the odd-numbered sequence points into multiple A second short sequence; wherein the first short sequence includes a plurality of consecutive even-numbered sequence points, and the second short sequence includes a plurality of consecutive odd-numbered sequence points; step 11233, the multiple first short sequences and The multiple second short sequences are arranged in a preset order to obtain a target synchronization sequence with good autocorrelation characteristics.

And step 11233 includes: alternately placing the first short sequence and the second short sequence to obtain a target synchronization sequence with good autocorrelation characteristics.

For example, when the sequence length of the reference synchronization sequence is an integer multiple of 4, step 11232 specifically includes: dividing the even sequence point into two first short sequences, which are short sequence 1 and short sequence 2, respectively; and the odd sequence point Divided into 2 second short sequences, short sequence 3 and short sequence 4 respectively. Among them, short sequence 1 is the first half of the even-numbered sequence point of the reference synchronization sequence, short sequence 2 is the latter half of the even-numbered sequence point of the reference synchronization sequence; short sequence 3 is the odd-numbered sequence point of the reference synchronization sequence In the first half, short sequence 4 is the second half of the odd sequence point of the reference synchronization sequence.

The alternate placement of the first short sequence and the second short sequence specifically means that in the rearranged target sequence, between short sequence 1 and 2 is short sequence 3 or 4, and between short sequence 3 and 4 is short Sequence 1 or 2; For example: the target synchronization sequence is [short sequence 1, short sequence 3, short sequence 2, short sequence 4], or [short sequence 1, short sequence 4, short sequence 2, short sequence 3], or [ Short sequence 2, short sequence 3, short sequence 1, short sequence 4], [short sequence 2, short sequence 4, short sequence 1, short sequence 3], in the same way, the short sequence composed of odd dots can also be placed in the first The short sequence positions are not listed here.

It should be noted that the method of alternately placing the first short sequence and the second short sequence is only a preferred embodiment of the present invention, and other placing orders are also applicable to the present invention. For example, multiple first short sequences are placed consecutively, and then multiple second short sequences are consecutively placed; or multiple second short sequences are placed consecutively, and then multiple first short sequences are placed consecutively. In short, the even-numbered sequence points of the reference synchronization sequence are placed before the odd-numbered sequence points of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics; or the odd-numbered sequence points of the reference synchronization sequence are placed on the reference synchronization sequence. Before the even-numbered sequence point of the reference synchronization sequence, a target synchronization sequence with good autocorrelation characteristics is obtained.

Further, in the foregoing embodiment of the present invention, if the sequence length of the reference synchronization sequence divided by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the sequence length of the reference synchronization sequence is divided by 4 When the result obtained is an odd number, the multiple second short sequences are ZC sequences.

Specifically, that is, when the length of the reference synchronization sequence is an even number, if a quarter of the length of the reference synchronization sequence is an even number, short sequence 1 and short sequence 2 are ZC sequences; if the reference synchronization sequence is an even number, short sequence 1 and short sequence 2 are ZC sequences; The quarter length of the step sequence is odd, then the short sequence 3 and the short sequence 4 are ZC sequences.

If the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, step 112 further includes: step 1121, respectively intercepting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence; step 1122, synchronize the reference The even-numbered sequence points of the sequence are placed before the odd-numbered sequence points of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics; or the odd-numbered sequence points of the reference synchronization sequence are placed before the even-numbered sequence points of the reference synchronization sequence , Get the target synchronization sequence with good autocorrelation characteristics.

For example, the reference synchronization sequence includes {sequence point 1, sequence point 2, sequence point 3, sequence point 4, sequence point 5, sequence point 6, sequence point 7, and sequence point 8}, then the target synchronization sequence is {sequence point 2, Sequence point 4, sequence point 6, sequence point 8, sequence point 1, sequence point 3, sequence point 5, sequence point 7}; or the target synchronization sequence is {sequence point 1, sequence point 3, sequence point 5, sequence point 7 , Sequence point 2, sequence point 4, sequence point 6, sequence point 8}.

Further, when the first half of the target synchronization sequence is an even sequence point of the reference synchronization sequence, and the second half of the target synchronization sequence is an odd sequence point of the reference synchronization sequence, that is, the target synchronization sequence is {sequence point 2, sequence point 4 , Sequence point 6, sequence point 8, sequence point 1, sequence point 3, sequence point 5, sequence point 7}; if the sequence length of the ZC sequence divided by 4 is an even number, the target synchronization sequence The sub-synchronization sequence intercepted in the time domain is the sequence of the first quarter segment of the target synchronization sequence and/or the sequence of the second quarter segment of the target synchronization sequence, and the sub-synchronization sequence is ZC sequence; that is, the sub-synchronization sequence is {sequence point 2, sequence point 4} or the sub-synchronization sequence is {sequence point 6, sequence point 8}.

If the sequence length of the ZC sequence divided by 4 is an odd number, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the sequence of the third quarter segment of the target synchronization sequence and/ Or the sequence of the fourth quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; no examples are given.

Or, when the first half of the target synchronization sequence is an odd sequence point of the reference synchronization sequence, and the second half of the target synchronization sequence is an even sequence point of the reference synchronization sequence, that is, the target synchronization sequence is {sequence point 1, sequence point 3, Sequence point 5, sequence point 7, sequence point 2, sequence point 4, sequence point 6, sequence point 8}; if the sequence length of the ZC sequence divided by 4 is an odd number, when the target synchronization sequence is The sub-synchronization sequence intercepted on the domain is the sequence of the first quarter segment of the target synchronization sequence and/or the sequence of the second quarter segment of the target synchronization sequence, and the sub-synchronization sequence is ZC Sequence; do not give examples one by one.

If the sequence length of the ZC sequence divided by 4 is an even number, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the sequence of the third quarter segment of the target synchronization sequence and/ Or the sequence of the fourth quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; that is, the sub-synchronization sequence is {sequence point 2, sequence point 4} or the sub-synchronization sequence is {sequence point 6 , Sequence point 8}.

The specific proof is as follows: Suppose the even ZC sequence is:

The sequence has the following characteristics: When Nzc/4 is still an even number, the even-numbered point in the first half of z(n) is still a ZC sequence.

則當Nzc/4仍是偶數時，z ₁(m)是一個ZC序列。 Proof: Let n=2m, m=0,1,...,Nzc/4, there is the following formula:

Then when Nzc/4 is still an even number, z ₁ ( m ) is a ZC sequence.

When Nzc/4 is still an even number, the even-numbered point in the second half of z(n) is still a ZC sequence.

當Nzc/4仍是偶數時，z ₂(m)是一個ZC序列。 Proof: Let n=2m, m=0,1,...,Nzc/4, there is the following formula:

When Nzc/4 is still an even number, z ₂ ( m ) is a ZC sequence.

When Nzc/4 is an odd number, the odd-numbered point in the first half of z(n) is still a ZC sequence.

當Nzc/4是奇數時，z ₃(m)是一個ZC序列，其中。 Proof: Let n=2m, m=0,1,...,Nzc/4, there is the following formula:

When Nzc/4 is an odd number, z ₃ ( m ) is a ZC sequence in which.

When Nzc/4 is an odd number, the odd-numbered point in the second half of z(n) is still a ZC sequence.

當Nzc/4是奇數時，z ₄(m)是一個ZC序列，其中

Proof: Let n=2m, m=0,1,...,Nzc/4, there is the following formula:

When Nzc/4 is an odd number, z ₄ ( m ) is a ZC sequence, where

The second case: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, step 112 includes: step 1123, starting from the 0th sequence point of the reference synchronization sequence Initially, one target sequence point is extracted from every N consecutive sequence points; step 1124, the extracted target sequence point is successively placed in the preset position of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics ; Wherein, N is an integer greater than or equal to 3.

And the preset position is a position starting from an integer multiple of N.

For example, the reference synchronization sequence includes {sequence point 1, sequence point 2, sequence point 3, sequence point 4, sequence point 5, sequence point 6, sequence point 7, sequence point 8, sequence point 9}, and N is equal to 3; then The target synchronization sequence is {sequence point 1, sequence point 4, sequence point 7, sequence point 2, sequence point 5, sequence point 8, sequence point 3, sequence point 6, sequence point 9}.

Further, if the sequence length of the ZC sequence is an integer multiple of X, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of the X sub-segment of the target synchronization sequence, and the sub-synchronization sequence It is a ZC sequence; where X is an integer greater than or equal to 2.

For example, if X is equal to 3, the target synchronization sequence is {sequence point 1, sequence point 3, Sequence point 4, sequence point 6, sequence point 2, sequence point 7, sequence point 8, sequence point 9, sequence point 5}, then the sequence length of the target synchronization sequence is 9, then 9 is an integer multiple of 3, so sub-synchronization The sequence is a one-third segment of the target synchronization sequence, namely {sequence point 1, sequence point 3, sequence point 4}, or {sequence point 6, sequence point 2, sequence point 7}, or {sequence point 8, sequence Point 9, sequence point 5}.

Further, the description will be made for the case where the sequence intercepted in the frequency domain of the target synchronization sequence is a sub-synchronization sequence. In this case, the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number. 112 includes: step 1125, respectively intercepting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence; step 1126, placing the even-numbered sequence points of the reference synchronization sequence before the odd-numbered sequence points of the reference synchronization sequence to obtain a rearrangement sequence; Or place the odd-numbered sequence point of the reference synchronization sequence before the even-numbered sequence point of the reference synchronization sequence to obtain the rearrangement sequence; step 1127, map the rearrangement sequence to each subcarrier in the frequency domain, and pass the inverse Fourier After the inner leaf transform, the target synchronization sequence with good autocorrelation characteristics is obtained.

Specifically, the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, and the sequence of the second quarter segment of the target synchronization sequence. Sequence, the sequence of the third quarter segment of the target synchronization sequence and/or the sequence of the fourth quarter segment of the target sequence, and the sub-synchronization sequence is a ZC sequence.

Similarly, it can be proved by the formula of even ZC sequence that the sub-ZC sequence on each carrier can also be used as a synchronization sequence, that is, it has good autocorrelation and cross-correlation characteristics. It will not be described in detail here.

In summary, in the above-mentioned embodiment described with reference to FIG. 1 of the present invention, a target synchronization sequence with good autocorrelation characteristics is preset on the base station side. The interval and the system bandwidth are not sensitive, and can meet the needs of users of different system bandwidth and carrier interval; specifically, the sequence intercepted in the time domain or frequency domain of the target synchronization sequence can still be used as the synchronization sequence, and the interception The obtained sub-synchronization sequence has good autocorrelation characteristics and good cross-correlation characteristics; for terminals with different bandwidths or terminals with different carrier intervals, after the base station side sends the same target synchronization sequence, the terminal can intercept the corresponding according to its own needs The synchronization detection is performed by the sub-synchronization sequence of, which not only ensures the synchronization detection accuracy, but also improves the application range of the target synchronization sequence.

As shown in Figure 2, some embodiments of the present invention provide a synchronization detection method, including: step 21, receiving a target synchronization sequence with good autocorrelation characteristics sent by a base station; step 22, performing synchronization according to the target synchronization sequence Detection.

The foregoing embodiment of the present invention described with reference to FIG. 2 is applied to the terminal side, that is, the terminal side receives the target synchronization sequence sent by the base station, and performs synchronization detection according to its own needs and the received target synchronization sequence to achieve synchronization timing.

Specifically, step 22 in the above-mentioned embodiment described with reference to FIG. 2 of the present invention includes: step 221, intercepting a sequence in the time domain or frequency domain of the target synchronization sequence as a sub-synchronization sequence, and the sub-synchronization sequence has good performance. Auto-correlation characteristics; the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the needs of users of different system bandwidth and carrier spacing; in short, the terminal intercepts the target synchronization sequence in the frequency domain or time domain The subsequence obtained later can still be used as a synchronization sequence.

Step 222: Perform synchronization detection according to the sub-synchronization sequence.

If the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the sub-synchronization sequence intercepted in the time domain or frequency domain of the target synchronization sequence is one or more of the first synchronization sequences contained in the target synchronization sequence. A short sequence and/or one or more second short sequences; wherein the first short sequence includes multiple sequence points, and the second short sequence includes multiple sequence points.

It should be noted that the specific first short sequence includes several sequence points and the second short sequence includes several sequence points, which need to be determined according to the integer multiple of the sequence length of the reference synchronization sequence, which is not specifically limited here.

Specifically, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, and the sequence length of the ZC sequence is an integer multiple of 4, the time domain or frequency domain of the target synchronization sequence is intercepted The sub-synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, the sequence of the second quarter segment of the target synchronization sequence, and the sequence of the third quarter segment of the target synchronization sequence. Sequence or the sequence of the fourth quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence.

It should be noted that the specific sequence of the quarter segment that can be used as the sub-synchronization sequence also needs to be determined according to whether the sequence length of the target synchronization sequence is divided by 4, whether the result is odd or even, and the characteristics of the target synchronization sequence. Specifically, the characteristics of the target synchronization sequence can be indicated by the base station side, which is not specifically limited here.

Correspondingly, step 22 includes: step 223, using the preset synchronization sequence to perform correlation processing on the target synchronization sequence; step 224, determining the subcarrier interval for the base station to send the target synchronization sequence according to the number of correlation peaks obtained by the correlation processing; Step 225: Perform synchronization detection according to the sub-carrier interval and the sub-synchronization sequence.

Specifically, when the receiving end does not know the subcarrier spacing used by the base station (ie, the transmitting end), the subcarrier spacing can be determined according to the number of correlation peaks obtained by correlating the synchronization sequence.

Take the target synchronization sequence as [short sequence 1, short sequence 3, short sequence 2, short sequence 4] as an example. When the subcarrier spacing is 15kHz, the target synchronization sequence sent is [short sequence 1, short sequence 3, short sequence 2, short sequence 4], when the subcarrier spacing is 30 kHz, the target synchronization sequence sent is [short sequence 1, Short sequence 3], when the subcarrier spacing is 60kHz, the target synchronization sequence sent is [short sequence 1].

When the user at the receiving end performs detection, the carrier interval of the transmitting terminal can be judged according to the number of correlation peaks. For example, if the carrier interval of the transmitting terminal is 15kHz, and the user uses the 60kHz preset synchronization sequence [Short Sequence 1] as the local sequence for correlation, two peaks will be detected; if the carrier interval of the transmitting terminal is 60kHz, the user uses the preset synchronization sequence of 60kHz [Short Sequence 1] for correlation, 1 peak will be detected; if the carrier interval of the transmitting terminal is 30kHz, the user uses the 60kHz preset synchronization sequence [Short Sequence 1] for correlation, the user will only detect 1 peak, but if The user uses [short sequence 3] for correlation, and the user will also detect a peak value. However, for the case where the carrier interval of the transmitting terminal is 30kHz, the short sequence 3 is adopted, and there will be no peak. From this, the carrier interval of the transmitting terminal can be judged, and further Perform synchronization detection.

Or, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, The sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of a segment X of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; wherein, the sequence of the ZC sequence The length is an integer multiple of X, and X is an integer greater than or equal to 2. For example, if the sequence length is 15 and X is 3, the sub-synchronization sequence is any one-third sequence of the target synchronization sequence.

Specifically, in the above-mentioned embodiment of the present invention, the step of the terminal performing synchronization detection according to the sub-synchronization sequence includes: raising the sub-synchronization sequence to the power of p to obtain the sequence to be detected; that is, preprocessing the sub-synchronization sequence; wherein , P is an integer greater than or equal to 2; perform synchronization detection according to the sequence to be detected; that is, perform synchronization detection on the preprocessed signal.

；其中，r(m)是用來進行同步相關檢測 的。 Optionally, the receiving process includes two parts: preprocessing and synchronization detection. The synchronization detection is an existing algorithm, which is not described here. The following preprocessing algorithm is used when detecting the target synchronization sequence: Set the received signal as y(n)n=0,1,2,3……, let: y ₁ (2 m ) = y (4 m ) y ₁ (2 m +1)=0, y ₂ (2 m +1)= y (4 m +3), y ₂ (2 m )=0,

; Among them, r ( m ) is used for synchronization related detection.

In summary, in the above-mentioned embodiment of the present invention described with reference to FIG. 2, after receiving the target synchronization sequence, the terminal side intercepts the corresponding sub-synchronization sequence according to its own needs to perform synchronization detection, which not only ensures the synchronization detection accuracy, but also improves the target synchronization. The application range of the sequence; specifically, the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the needs of users of different system bandwidth and carrier spacing.

As shown in FIG. 3, some embodiments of the present invention provide a synchronization sequence sending device, including: The sequence setting module 31 is used to set a target synchronization sequence with good autocorrelation characteristics; wherein, at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a sub-synchronization sequence, and the sub-synchronization sequence has Good autocorrelation characteristics and good cross-correlation characteristics between the sub-synchronization sequences; the sequence sending module 32 is used to send the target synchronization sequence to the terminal.

Specifically, the sequence setting module in the above-mentioned embodiment described with reference to FIG. 3 of the present invention includes: a reference acquisition module for acquiring a reference synchronization sequence with good autocorrelation characteristics; a rearrangement module for following The preset rule rearranges multiple sequence points of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the rearrangement module includes: a first rearrangement sub-module, used if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number At the same time, the sequence points of the reference synchronization sequence are extracted at equal intervals, and the extracted sequence points are successively placed to obtain the target synchronization sequence with good autocorrelation characteristics.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the first rearrangement submodule includes: a first extraction unit for extracting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence respectively; first division The unit is used to divide the even-numbered sequence points into a plurality of first short sequences, and divide the odd-numbered sequence points into a plurality of second short sequences; wherein, the first short sequence includes a plurality of consecutive even-numbered sequence points, The second short sequence contains a plurality of consecutive odd sequence points; The rearrangement unit is configured to arrange the multiple first short sequences and the multiple second short sequences in a preset order to obtain a target synchronization sequence with good autocorrelation characteristics.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the rearrangement unit includes: a rearrangement subunit for alternately placing the first short sequence and the second short sequence to obtain a good autocorrelation The target synchronization sequence of the characteristic.

Specifically, in the foregoing embodiment of the present invention described with reference to FIG. 3, if the result of dividing the sequence length of the reference synchronization sequence by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the reference synchronization sequence is When the sequence length of the sequence divided by 4 is an odd number, the plurality of second short sequences are ZC sequences.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the rearrangement module includes: a first interception sub-module, which is used if the reference synchronization sequence is a ZC sequence and the sequence length of the ZC sequence is an even number , Respectively intercept the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence; the first rearrangement submodule is used to place the even-numbered sequence points of the reference synchronization sequence before the odd-numbered sequence points of the reference synchronization sequence to obtain a good The target synchronization sequence with the autocorrelation characteristics of the reference synchronization sequence; or the odd sequence point of the reference synchronization sequence is placed before the even sequence point of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics.

Specifically, in the foregoing embodiment of the present invention described with reference to FIG. 3, when the first half of the target synchronization sequence is an even sequence point of the reference synchronization sequence, and the second half of the target synchronization sequence is an odd sequence point of the reference synchronization sequence, If the sequence length of the ZC sequence divided by 4 is an even number, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence and/ Or the sequence of the second quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; if the sequence length of the ZC sequence divided by 4 is an odd number, when the target synchronization sequence is The sub-synchronization sequence intercepted on the domain is the sequence of the third quarter segment of the target synchronization sequence and/or the sequence of the fourth quarter segment of the target synchronization sequence, and the sub-synchronization sequence is ZC sequence.

Specifically, in the foregoing embodiment of the present invention described with reference to FIG. 3, when the first half of the target synchronization sequence is an odd sequence point of the reference synchronization sequence, and the second half of the target synchronization sequence is an even sequence point of the reference synchronization sequence, if When the sequence length of the ZC sequence divided by 4 is an odd number, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the sequence and/or the first quarter segment of the target synchronization sequence The sequence of the second quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; if the sequence length of the ZC sequence divided by 4 is an even number, in the time domain of the target synchronization sequence The sub-synchronization sequence intercepted above is the sequence of the third quarter segment of the target synchronization sequence and/or the sequence of the fourth quarter segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence .

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the rearrangement module includes: an extraction sub-module, which is used if the reference synchronization sequence is a ZC sequence, and the sequence of the ZC sequence When the length is an odd number and the sequence length is equal to the square of N, start from the 0th sequence point of the reference synchronization sequence, and extract a target sequence point from every N consecutive sequence points; the second rearrangement submodule is used for The extracted target sequence points are continuously placed at the preset position of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics; where N is an integer greater than or equal to 3.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the preset position is a position starting from an integer multiple of N.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, if the sequence length of the ZC sequence is an integer multiple of X, the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the target synchronization sequence A sequence of one segment of X, and the sub-synchronization sequence is a ZC sequence; where X is an integer greater than or equal to 2.

Wherein, the rearrangement module includes: a second intercepting sub-module, which is used to intercept the even sequence points and odd numbers of the reference synchronization sequence if the reference synchronization sequence is a ZC sequence and the sequence length of the ZC sequence is an even number Sequence points; the third rearrangement submodule is used to place the even-numbered sequence points of the reference synchronization sequence before the odd-numbered sequence points of the reference synchronization sequence to obtain the rearrangement sequence; or place the odd-numbered sequence points of the reference synchronization sequence Before the even-numbered sequence point of the reference synchronization sequence, the rearrangement sequence is obtained; the frequency domain mapping sub-module is used to map the rearrangement sequence to each sub-carrier in the frequency domain, and the rearrangement sequence is obtained after the inverse Fourier transform Target synchronization sequence with good autocorrelation characteristics.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the first quarter of the target synchronization sequence. The sequence of one segment, the sequence of the second quarter segment of the target synchronization sequence, the sequence of the third quarter segment of the target synchronization sequence, and/or the fourth quarter of the target sequence The sequence of segments, and the sub-synchronization sequence is a ZC sequence.

In summary, in the above-mentioned embodiment of the present invention described with reference to FIG. 3, the base station side presets a target synchronization sequence with good autocorrelation characteristics. The target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the requirements of different systems. The needs of users of bandwidth and carrier spacing; specifically, the sequence intercepted in the time domain or frequency domain of the target synchronization sequence can still be used as the synchronization sequence, and the intercepted sub-synchronization sequence has good autocorrelation characteristics and Good cross-correlation characteristics; For terminals with different bandwidths or terminals with different carrier intervals, after the base station side sends the same target synchronization sequence, the terminal can intercept the corresponding sub-synchronization sequence for synchronization detection according to its own needs, which not only guarantees Synchronization detection accuracy, and improve the application range of the target synchronization sequence.

It should be noted that the sending device of the synchronization sequence provided by the embodiment described with reference to FIG. 3 of the present invention is a sending device capable of executing the method of sending the synchronization sequence provided by the embodiment described with reference to FIG. All the embodiments of the sending method are applicable to the sending device, and all can achieve the same or similar beneficial effects.

As shown in FIG. 4, some embodiments of the present invention also provide another synchronization sequence sending device. The synchronization sequence sending device includes: a processor 100; a memory 120 connected to the processor 100 through a bus interface , And a transceiver 110 connected to the processor 100 through a bus interface; the memory is used to store programs and data used by the processor when performing operations; control commands, etc. are sent through the transceiver 110; when the processor When calling and executing the programs and data stored in the memory, the following functional modules are realized: The sequence setting module is used to set a target synchronization sequence with good autocorrelation characteristics; wherein, at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a sub-synchronization sequence, and the sub-synchronization sequence has a good And the sub-synchronization sequence has good cross-correlation characteristics; the sequence sending module is used to send the target synchronization sequence to the terminal.

Wherein, in FIG. 4, the bus structure may include any number of interconnected bus bars and bridges, specifically one or more processors represented by the processor 100 and various circuits of the memory represented by the memory 120 are connected together. The bus bar architecture can also connect various other circuits such as peripherals, voltage regulators, and power management circuits. The bus interface provides an interface. The transceiver 110 may be a plurality of elements, that is, including a transmitter and a transceiver, and provide a unit for communicating with various other devices on a transmission medium. The processor 100 is responsible for managing the bus architecture and general processing, and the memory 120 can store data used by the processor 100 when performing operations.

The processor 100 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 100 when performing operations.

It should be noted that the sending device of the synchronization sequence provided by the embodiment described with reference to FIG. 4 of the present invention is a sending device capable of executing the method of sending the synchronization sequence provided by the embodiment described with reference to FIG. All the embodiments of the sending method are applicable to the sending device, and all can achieve the same or similar beneficial effects.

As shown in FIG. 5, some embodiments of the present invention also provide a synchronization detection device, including: a sequence receiving module 51 for receiving a target synchronization sequence with good autocorrelation characteristics sent by a base station; The detection module 52 is used to perform synchronization detection according to the target synchronization sequence.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 5, the detection module includes: an interception sub-module for intercepting a sequence in the time domain or the frequency domain of the target synchronization sequence as a sub-synchronization sequence. The synchronization sequence has good autocorrelation characteristics; the detection sub-module is used to perform synchronization detection according to the sub-synchronization sequence.

Specifically, in the foregoing embodiment of the present invention described with reference to FIG. 5, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the target synchronization sequence is intercepted in the time domain or the frequency domain. The sub-synchronization sequence of is one or more first short sequences and/or one or more second short sequences contained in the target synchronization sequence; wherein, the first short sequence contains multiple sequence points, and the second short sequence Contains multiple sequence points.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 5, the detection module includes: a correlation processing sub-module for performing correlation processing on the target synchronization sequence using a preset synchronization sequence; and an interval determination sub-module, It is used to determine the sub-carrier interval for the base station to send the target synchronization sequence according to the number of correlation peaks obtained by the correlation processing; the synchronization detection sub-module is used to perform synchronization detection according to the sub-carrier interval and the sub-synchronization sequence.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 5, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the target synchronization sequence is intercepted in the time domain or the frequency domain. The sub-synchronization sequence is the same as the target The sequence of the first quarter segment of the step sequence, the sequence of the second quarter segment of the target synchronization sequence, the sequence of the third quarter segment of the target synchronization sequence, or the target synchronization sequence The fourth quarter segment of the sequence, and the sub-synchronization sequence is a ZC sequence.

Specifically, in the foregoing embodiment of the present invention described with reference to FIG. 5, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, in the time domain of the target synchronization sequence The sub-synchronization sequence intercepted above is a sequence of a part of X of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; wherein, the sequence length of the ZC sequence is an integer multiple of X, and X is greater than or equal to 2 Integer.

Specifically, in the above-mentioned embodiment of the present invention described with reference to FIG. 5, the detection sub-module includes: a pre-processing module, which is used to power the sub-synchronization sequence to the power of p to obtain the sequence to be detected; p is greater than or equal to 2. An integer; the detection unit is used to perform synchronization detection according to the sequence to be detected.

In summary, in the above embodiment of the present invention described with reference to FIG. 5, after receiving the target synchronization sequence, the terminal side intercepts the corresponding sub-synchronization sequence according to its own needs to perform synchronization detection, which not only ensures synchronization detection accuracy, but also improves target synchronization. The application range of the sequence; specifically, the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the needs of users of different system bandwidth and carrier spacing.

It should be noted that the synchronization detection device provided by the embodiment described with reference to FIG. 5 of the present invention can execute the synchronization detection method provided by the embodiment described with reference to FIG. 2, then all implementations of the synchronization detection method Examples are applicable to the synchronization detection Device, and can achieve the same or similar beneficial effects.

As shown in FIG. 4, some embodiments of the present invention also provide another synchronization detection device. The synchronization detection device includes: a processor 100; a memory 120 connected to the processor 100 through a bus interface; The transceiver 110 connected to the processor 100 is arranged on the interface; the memory is used to store the programs and data used by the processor when performing operations; control commands, etc. are sent through the transceiver 110; when the processor calls and executes the When the programs and data stored in the memory, the following functional modules are realized: the sequence receiving module is used to receive the target synchronization sequence with good autocorrelation characteristics sent by the base station; the detection module is used to follow the target The synchronization sequence performs synchronization detection.

Wherein, in FIG. 4, the bus structure may include any number of interconnected bus bars and bridges, specifically one or more processors represented by the processor 100 and various circuits of the memory represented by the memory 120 are connected together. The bus bar architecture can also connect various other circuits such as peripherals, voltage regulators, and power management circuits. The bus interface provides an interface. The transceiver 110 may be a plurality of elements, that is, including a transmitter and a transceiver, and provide a unit for communicating with various other devices on a transmission medium. The processor 100 is responsible for managing the bus architecture and general processing, and the memory 120 can store data used by the processor 100 when performing operations.

The processor 100 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 100 when performing operations.

It should be noted that the synchronization detection device provided by the embodiment described with reference to FIG. 4 of the present invention can execute the synchronization detection method provided by the embodiment described with reference to FIG. 2, then all implementations of the synchronization detection method Examples are applicable to the synchronization detection Device, and can achieve the same or similar beneficial effects.

The above are the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made. These improvements and modifications It should also be regarded as the protection scope of the present invention.

11-12‧‧‧Step

Claims (12)

A method for sending a synchronization sequence includes: setting a target synchronization sequence; wherein at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a synchronization sequence; sending the target synchronization sequence to a terminal; wherein, the The step of setting the target synchronization sequence includes: obtaining a reference synchronization sequence; rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence, wherein, if the reference synchronization sequence is a generalized chirp (Zadoff-Chu, ZC) sequence, and the sequence length of the ZC sequence is an even number, the step of rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence includes: equal intervals respectively Extract the sequence points of the reference synchronization sequence, place the extracted sequence points consecutively to obtain the target synchronization sequence, where the sequence points of the reference synchronization sequence are extracted at equal intervals, and the extracted sequence points are consecutively placed to obtain the target synchronization sequence. The sequence step includes: extracting the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence respectively; dividing the even-numbered sequence points into a plurality of first short sequences, and dividing the odd-numbered sequence points into a plurality of second short sequences; Wherein, the first short sequence includes a plurality of consecutive even-numbered sequence points, the second short sequence includes a plurality of consecutive odd-numbered sequence points; the plurality of first short sequences and the plurality of second short sequences are in accordance with the predetermined Suppose the sequence is arranged to obtain the target synchronization sequence. The step of arranging the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain the target synchronization sequence includes: The second short sequence is alternately placed to obtain the target synchronization sequence. The method for sending a synchronization sequence according to claim 1, wherein if the result of dividing the sequence length of the reference synchronization sequence by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the reference synchronization sequence is When the result of dividing the sequence length by 4 is an odd number, then the plurality of second short sequences are ZC sequences. A method for sending a synchronization sequence includes: setting a target synchronization sequence; wherein at least a segment of the sequence intercepted in the time domain or frequency domain of the target synchronization sequence is a synchronization sequence; sending the target synchronization sequence to a terminal; wherein, the The step of setting the target synchronization sequence includes: obtaining a reference synchronization sequence; rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence, wherein, if the reference synchronization sequence is a ZC sequence, and The sequence length of the ZC sequence is an odd number, and the sequence length is equal to the square of N; the step of rearranging a plurality of sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence includes: obtaining the target synchronization sequence from the reference synchronization sequence Starting from the 0th sequence point of, extract a target sequence point from every N consecutive sequence points; place the extracted target sequence point consecutively at the preset position of the reference synchronization sequence to obtain the target synchronization sequence; where N Is an integer greater than or equal to 3, where the preset position is a position starting from an integer multiple of N, where, if the sequence length of the ZC sequence is an integer multiple of X, it will be intercepted in the time domain of the target synchronization sequence The obtained sub-synchronization sequence is a sequence of a segment of X of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; where X is an integer greater than or equal to 2. A method for sending a synchronization sequence includes: setting a target synchronization sequence; wherein at least a segment of the sequence intercepted in the time domain or the frequency domain of the target synchronization sequence is a synchronization sequence; Sending the target synchronization sequence to the terminal; wherein the step of setting the target synchronization sequence includes: obtaining a reference synchronization sequence; rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence, Wherein, if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, the steps of rearranging multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence include: Separately intercept the even sequence points and odd sequence points of the reference synchronization sequence; place the even sequence points of the reference synchronization sequence before the odd sequence points of the reference synchronization sequence to obtain the rearrangement sequence; or the odd sequence of the reference synchronization sequence The point is placed before the even-numbered sequence point of the reference synchronization sequence to obtain the rearrangement sequence; the rearrangement sequence is respectively mapped to each subcarrier in the frequency domain, and the target synchronization sequence is obtained after the inverse Fourier transform. The sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, the sequence of the second quarter segment of the target synchronization sequence, and the target synchronization sequence. The sequence of the third quarter segment of the synchronization sequence and/or the sequence of the fourth quarter segment of the target sequence, and the sub-synchronization sequence is a ZC sequence. A synchronization detection method includes: receiving a target synchronization sequence sent by a base station; performing synchronization detection according to the target synchronization sequence; wherein the step of performing synchronization detection according to the target synchronization sequence includes: in the time domain of the target synchronization sequence or A segment of the sequence is intercepted in the frequency domain as a synchronization sequence; synchronization detection is performed according to the intercepted synchronization sequence, where, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, in the time domain of the target synchronization sequence Or the synchronization sequence intercepted in the frequency domain is one or more first short sequences and/or one or more second short sequences contained in the target synchronization sequence; wherein, the The first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points, wherein the step of performing synchronization detection according to the target synchronization sequence includes: performing synchronization detection on the target synchronization sequence using a preset synchronization sequence Correlation processing; according to the number of correlation peaks obtained by the correlation processing, determine the subcarrier interval for the base station to send the target synchronization sequence; perform synchronization detection according to the subcarrier interval and the intercepted synchronization sequence. A synchronization detection method includes: receiving a target synchronization sequence sent by a base station; performing synchronization detection according to the target synchronization sequence; wherein the step of performing synchronization detection according to the target synchronization sequence includes: in the time domain of the target synchronization sequence or A segment of the sequence is intercepted in the frequency domain as a synchronization sequence; synchronization detection is performed according to the intercepted synchronization sequence, where if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, The synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of a part of X of the target synchronization sequence, and the intercepted synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence is an integer multiple of X , X is an integer greater than or equal to 2, wherein the step of performing synchronization detection according to the intercepted synchronization sequence includes: deriving the intercepted synchronization sequence to the power of p to obtain the sequence to be detected; where p is greater than or An integer equal to 2; perform synchronization detection according to the sequence to be detected. A synchronization sequence sending device includes: a processor, a memory, and a transceiver. The processor is used to read the program in the memory and execute the following process: setting a target synchronization sequence; wherein, when the target synchronization sequence is At least a segment of the sequence intercepted in the frequency domain or the frequency domain is a synchronization sequence; the target synchronization sequence is sent to the terminal through the transceiver, the transceiver is used to receive and send data, and the memory can store the processor when performing operations The data used; where the processor reads the program in the memory to further perform the following process: obtain a reference synchronization sequence; rearrange multiple sequence points of the reference synchronization sequence according to a preset rule to obtain target synchronization Sequence, where the processor reads the program in the memory to further perform the following process: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, extract the reference synchronization sequence at equal intervals. Sequence points: sequentially place the extracted sequence points to obtain the target synchronization sequence, where the processor reads the program in the memory to further perform the following process: extract the even-numbered sequence points and odd-numbered sequence points of the reference synchronization sequence respectively; The even-numbered sequence points are divided into a plurality of first short sequences, and the odd-numbered sequence points are divided into a plurality of second short sequences; wherein, the first short sequence includes a plurality of consecutive even-numbered sequence points, and the second short sequence Contains a plurality of consecutive odd sequence points; the plurality of first short sequences and the plurality of second short sequences are arranged in a preset order to obtain the target synchronization sequence, wherein the processor reads the program in the memory to The following process is further performed: the first short sequence and the second short sequence are alternately placed to obtain the target synchronization sequence. The device for sending a synchronization sequence according to claim 7, wherein, if the result of dividing the sequence length of the reference synchronization sequence by 4 is an even number, then the plurality of first short sequences are ZC sequences; if the reference synchronization sequence is When the result of dividing the sequence length by 4 is an odd number, then the plurality of second short sequences are ZC sequences. A synchronization sequence sending device includes: a processor, a memory, and a transceiver. The processor is used to read the program in the memory and execute the following process: setting a target synchronization sequence; wherein, when the target synchronization sequence is At least one segment of the sequence intercepted in the frequency domain or the frequency domain is a synchronization sequence; the target synchronization sequence is sent to the terminal through the transceiver, The transceiver is used to receive and send data, and the memory can store data used by the processor when performing operations; wherein, the processor reads the program in the memory to further perform the following process: obtain a reference synchronization sequence; The multiple sequence points of the reference synchronization sequence are rearranged according to the preset rule to obtain the target synchronization sequence, wherein the processor reads the program in the memory to further perform the following process: if the reference synchronization sequence is a ZC sequence, And when the sequence length of the ZC sequence is an odd number, and the sequence length is equal to the square of N, start from the 0th sequence point of the reference synchronization sequence, and extract a target sequence point from every N consecutive sequence points; The target sequence points are continuously placed at the preset positions of the reference synchronization sequence to obtain the target synchronization sequence; where N is an integer greater than or equal to 3, where the preset position is a position starting from an integer multiple of N, where, If the sequence length of the ZC sequence is an integer multiple of X, the synchronization sequence intercepted in the time domain of the target synchronization sequence is the sequence of the X sub-segment of the target synchronization sequence, and the intercepted synchronization sequence is ZC Sequence; where X is an integer greater than or equal to 2. A synchronization sequence sending device includes: a processor, a memory, and a transceiver. The processor is used to read the program in the memory and execute the following process: setting a target synchronization sequence; wherein, when the target synchronization sequence is At least one segment of the sequence intercepted in the frequency domain or frequency domain is a synchronization sequence; the target synchronization sequence is sent to the terminal through the transceiver, the transceiver is used to receive and send data, and the memory can store the processor's operation The data used; where the processor reads the program in the memory to further perform the following process: obtain a reference synchronization sequence; rearrange multiple sequence points of the reference synchronization sequence according to a preset rule to obtain the target synchronization sequence , Wherein, the processor reads the program in the memory to further perform the following process: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, respectively intercept the even sequence points and odd numbers of the reference synchronization sequence Sequence point; the even sequence point of the reference synchronization sequence is placed before the odd sequence point of the reference synchronization sequence to obtain the rearrangement sequence; or the odd sequence point of the reference synchronization sequence is placed before the even sequence point of the reference synchronization sequence , Get the rearrangement sequence; map the rearrangement sequence to each subcarrier in the frequency domain, and obtain the target synchronization sequence after inverse Fourier transform, where the target synchronization sequence is intercepted in the frequency domain of the target synchronization sequence The synchronization sequence is the sequence of the first quarter segment of the target synchronization sequence, the sequence of the second quarter segment of the target synchronization sequence, and the sequence of the third quarter segment of the target synchronization sequence And/or the sequence of the fourth quarter segment of the target sequence, and the intercepted synchronization sequence is a ZC sequence. A synchronization detection device includes: a processor, a memory, and a transceiver. The processor is used to read the program in the memory and execute the following process: receive the target synchronization sequence sent by the base station through the transceiver; Synchronization sequence for synchronization detection, the transceiver is used to receive and send data, the memory can store the data used by the processor when performing operations; wherein, the processor reads the program in the memory to further perform the following processes : Intercept a sequence in the time domain or frequency domain of the target synchronization sequence as a synchronization sequence; perform synchronization detection according to the intercepted synchronization sequence, where, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number When, the synchronization sequence intercepted in the time domain or frequency domain of the target synchronization sequence is one or more first short sequences and/or one or more second short sequences contained in the target synchronization sequence; wherein, the first short sequence A short sequence includes a plurality of sequence points, the second short sequence includes a plurality of sequence points, wherein the processor reads the program in the memory to further perform the following process: use a preset synchronization sequence to synchronize the target sequence Carry out related processing; According to the number of correlation peaks obtained by correlation processing, determine the subcarrier interval for the base station to send the target synchronization sequence; perform synchronization detection according to the subcarrier interval and the intercepted synchronization sequence. A synchronization detection device includes: a processor, a memory, and a transceiver. The processor is used to read the program in the memory and execute the following process: receive the target synchronization sequence sent by the base station through the transceiver; Synchronization sequence for synchronization detection, the transceiver is used to receive and send data, the memory can store the data used by the processor when performing operations; wherein, the processor reads the program in the memory to further perform the following processes : Intercept a sequence in the time domain or frequency domain of the target synchronization sequence as a synchronization sequence; perform synchronization detection according to the intercepted synchronization sequence, where, if the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number And when the sequence length is equal to the square of N, the synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one segment X of the target synchronization sequence, and the intercepted synchronization sequence is a ZC sequence; where the ZC The sequence length of the sequence is an integer multiple of X, and X is an integer greater than or equal to 2. Among them, the processor reads the program in the memory to further perform the following process: the intercepted synchronization sequence is raised to the power of p to obtain the Detection sequence; where p is an integer greater than or equal to 2; perform synchronization detection according to the sequence to be detected.

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