有鑑於此，本發明提供一種橫向擴散金屬氧化物半導體裝置及其製造方法以使得橫向擴散金屬氧化物半導體裝置既具有較高的耐崩潰電壓，又具有較低的導通電阻。
一種橫向擴散金屬氧化物半導體裝置，其中包括：
基層，
位於所述基層中且具有第一摻雜類型的減小表面場效應層，
位於所述基層中且位於所述減小表面場效應層之上的漂移區，所述漂移區為第二摻雜類型，
位於所述漂移區中的汲極區，所述汲極區為第二摻雜類型，
其中，所述減小表面場效應層與所述漂移區之間的第一間距大於零。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括：
位於所述基層中且位於所述減小表面場效應層之上的體區，所述體區為第一摻雜類型，
位於所述體區中的源極區，所述源極區為第二摻雜類型，
所述減小表面場效應層與所述體區之間的第二間距小於或等於所述第一間距。
較佳地，位於所述體區下方的所述減小表面場效應層與所述基層的第一表面之間的第三間距小於位於所述漂移區下方的所述減小表面場效應層與所述基層的第一表面之間的第四間距。
較佳地，所述減小表面場效應層包括埋層在所述基層中且彼此相接觸的第一埋層和第二埋層，所述第一埋層的至少部分位於所述體區下方，所述第二埋層的至少部分位於所述漂移區下方，
所述第一埋層與所述基層的第一表面之間的間距為所述第三間距，所述第二埋層與所述基層的第一表面之間的間距為所述第四間距。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括位於所述基層中，且位於所述減小表面場效層下方的隔離層，所述隔離層將所述減小表面場效應層與所述基層隔離。
較佳地，所述隔離層為第二摻雜類型的第三埋層。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括：
位於所述基層的第一表面且與所述源極區相鄰的第一介電質層，
位於所述第一介電質層上的第一導體。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括位於所述第一介電質層和汲極區之間的耐壓層。
較佳地，所述第一導體位於所述第一介電質層和部分耐壓層上。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括第二導體，所述第二導體的至少部分位於所述耐壓層上，且所述第一導體和第二導體空間隔離。
較佳地，所述第二導體和第一導體中的一個導體層的一部分覆蓋在所述第一介電質層和耐壓層的交界處上方。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括至少一個第三導體，各個所述第三導體均位於所述耐壓層上，且彼此空間隔離，且與所述第二導體相鄰的一個所述第三導體與所述第二導體空間隔離。
較佳地，所述耐壓層為第二介電質層，所述第二介電質層的厚度大於所述第一介電質層的厚度。
較佳地，所述基層包括第一摻雜類型的矽基板和位於所述矽基板中的高壓井區，所述高壓井區為第二摻雜類型，
所述體區和漂移區均位於所述高壓井區中。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括位於體區中且為第一摻雜類型的體接觸區。
較佳地，所述漂移區的摻雜濃度越大，所述第一間距的大小越小。
較佳地，所述的橫向擴散金屬氧化物半導體裝置還包括與所述源極區電連接的源電極，
所述源電極延伸至至少部分所述第二導體的上方。
一種橫向擴散金屬氧化物半導體裝置的製造方法，其中包括：
在基層中形成具有第一摻雜類型的減小表面場效應層，
以及在所述基層中形成具有第二摻雜類型的漂移區，並在所述漂移區中形成第二摻雜類型的汲極區，
所述漂移區位於所述減小表面場效應層的上方，且使得所述漂移區與所述減小表面場效應層之間的第一間距大於零。
較佳地，所述的製造方法還包括：
在所述基層中形成第一摻雜類型的體區，所述體區位於所述減小表面場效應層的上方，並在所述體區中形成具有第二摻雜類型的源極區，
使所述減小表面場效應層與所述體區之間的第二間距小於或等於所述第一間距。
較佳地，使位於所述體區下方的所述減小表面場效應層與所述基層的第一表面之間的第三間距小於位於所述漂移區下方的所述減小表面場效應層與所述基層的第一表面之間的第四間距。
較佳地，所述的製造方法還包括在所述基層中形成隔離層，所述隔離層位於所述減小表面場效應層下方，以將所述減小表面場效應層和所述基層隔離。
較佳地，所述的製造方法還包括，在所述基層的第一表面的閘極區域形成第一介電質層，
在所述第一介電質層上形成第一導體，所述第一介電質層與所述源極區相鄰，
其中，所述體區的至少部分位於所述第一介電質層的第一側，所述漂移區的至少部分位於所述第一介電質層的第二側。
較佳地，所述的製造方法還包括在所述第一介電質層和汲極區之間形成耐壓層。
較佳地，在形成所述第一導體時，形成第二導體，所述第二導體的至少部分位於所述耐壓層上，且所述第一導體和第二導體空間隔離。
較佳地，在形成所述第二導體時，在所述耐壓層上形成至少一個第三導體，各個所述第三導體之間彼此空間隔離。
較佳地，所述的製造方法還包括形成與所述源極區電連接的源電極，且使得所述源電極延伸至至少部分所述第二導體的上方。
較佳地，根據所述漂移區的摻雜濃度來調節所述第一間距的大小，所述漂移區的摻雜濃度越高，所述第一間距的大小越小。
由上可見，依據本發明提供的橫向擴散金屬氧化物半導體裝置及其製造方法中，透過在漂移區下方形成設置與漂移區摻雜類型相反的減小表面場效應層來輔助耗盡漂移區，以提高半導體裝置的耐壓性能，且還使得所述減小表面場效應層與所述漂移區之間的第一間距設置得大於零，從而可以確保所述減小表面場效應層和漂移區之間具有一定的電子流經路徑，以降低半導體器的導通電阻。因此，依據本發明提供的橫向擴散金屬氧化物半導體裝置的耐壓性能和導通電阻性能均能得到最優化。In view of this, the present invention provides a laterally diffused metal oxide semiconductor device and a manufacturing method thereof so that the laterally diffused metal oxide semiconductor device has a higher breakdown voltage and a lower on-resistance.
A laterally diffused metal oxide semiconductor device, which includes:
Grassroots,
A surface field effect reduction layer located in the base layer and having the first doping type,
A drift region located in the base layer and above the surface field effect reduction layer, where the drift region is of the second doping type,
A drain region located in the drift region, the drain region is of the second doping type,
Wherein, the first distance between the surface field effect reduction layer and the drift region is greater than zero.
Preferably, the laterally diffused metal oxide semiconductor device further includes:
A body region located in the base layer and above the surface field effect reduction layer, the body region being of the first doping type,
A source region located in the body region, the source region is of the second doping type,
The second distance between the reduced surface field effect layer and the body region is less than or equal to the first distance.
Preferably, the third distance between the reduced surface field effect layer located below the body region and the first surface of the base layer is smaller than that between the reduced surface field effect layer located below the drift region and the first surface of the base layer. The fourth distance between the first surfaces of the base layer.
Preferably, the surface field effect reduction layer includes a first buried layer and a second buried layer with a buried layer in the base layer and in contact with each other, and at least part of the first buried layer is located below the body region , At least part of the second buried layer is located below the drift region,
The distance between the first buried layer and the first surface of the base layer is the third distance, and the distance between the second buried layer and the first surface of the base layer is the fourth distance.
Preferably, the laterally diffused metal oxide semiconductor device further includes an isolation layer located in the base layer and below the surface field effect reduction layer, and the isolation layer connects the surface field effect reduction layer Isolated from the base layer.
Preferably, the isolation layer is a third buried layer of the second doping type.
Preferably, the laterally diffused metal oxide semiconductor device further includes:
A first dielectric layer located on the first surface of the base layer and adjacent to the source region,
A first conductor located on the first dielectric layer.
Preferably, the laterally diffused metal oxide semiconductor device further includes a voltage withstand layer located between the first dielectric layer and the drain region.
Preferably, the first conductor is located on the first dielectric layer and part of the withstand voltage layer.
Preferably, the laterally diffused metal oxide semiconductor device further includes a second conductor, at least part of the second conductor is located on the withstand voltage layer, and the first conductor and the second conductor are spaced apart.
Preferably, a part of one conductor layer of the second conductor and the first conductor covers above the junction of the first dielectric layer and the withstand voltage layer.
Preferably, the laterally diffused metal oxide semiconductor device further includes at least one third conductor, and each of the third conductors is located on the withstand voltage layer and is spaced apart from each other and is connected to the second conductor. The adjacent third conductor is spaced apart from the second conductor.
Preferably, the voltage withstand layer is a second dielectric layer, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
Preferably, the base layer includes a silicon substrate of a first doping type and a high-voltage well region located in the silicon substrate, and the high-voltage well region is of a second doping type,
Both the body region and the drift region are located in the high-pressure well region.
Preferably, the laterally diffused metal oxide semiconductor device further includes a body contact region located in the body region and of the first doping type.
Preferably, the greater the doping concentration of the drift region, the smaller the size of the first gap.
Preferably, the laterally diffused metal oxide semiconductor device further includes a source electrode electrically connected to the source region,
The source electrode extends to at least part of the second conductor.
A method for manufacturing a laterally diffused metal oxide semiconductor device, which includes:
Forming a reduced surface field effect layer with the first doping type in the base layer,
And forming a drift region with a second doping type in the base layer, and forming a drain region with the second doping type in the drift region,
The drift region is located above the reduced surface field effect layer, and the first distance between the drift region and the reduced surface field effect layer is greater than zero.
Preferably, the manufacturing method further includes:
Forming a body region of the first doping type in the base layer, the body region being located above the surface field effect reduction layer, and forming a source region of the second doping type in the body region,
The second distance between the reduced surface field effect layer and the body region is made smaller than or equal to the first distance.
Preferably, the third distance between the reduced surface field effect layer located below the body region and the first surface of the base layer is smaller than the reduced surface field effect layer located below the drift region The fourth distance from the first surface of the base layer.
Preferably, the manufacturing method further includes forming an isolation layer in the base layer, the isolation layer is located below the surface field effect reduction layer to isolate the surface field effect reduction layer from the base layer .
Preferably, the manufacturing method further includes forming a first dielectric layer on the gate region of the first surface of the base layer,
Forming a first conductor on the first dielectric layer, and the first dielectric layer is adjacent to the source region,
Wherein, at least part of the body region is located on the first side of the first dielectric layer, and at least part of the drift region is located on the second side of the first dielectric layer.
Preferably, the manufacturing method further includes forming a voltage withstand layer between the first dielectric layer and the drain region.
Preferably, when forming the first conductor, a second conductor is formed, at least a part of the second conductor is located on the withstand voltage layer, and the first conductor and the second conductor are spaced apart.
Preferably, when forming the second conductor, at least one third conductor is formed on the withstand voltage layer, and the third conductors are spaced apart from each other.
Preferably, the manufacturing method further includes forming a source electrode electrically connected to the source region, and making the source electrode extend above at least part of the second conductor.
Preferably, the size of the first spacing is adjusted according to the doping concentration of the drift region, and the higher the doping concentration of the drift region, the smaller the size of the first spacing.
It can be seen from the above that in the laterally diffused metal oxide semiconductor device and its manufacturing method provided by the present invention, the drift region is assisted to deplete the drift region by forming and disposing a surface field effect reduction layer opposite to the doping type of the drift region under the drift region. In order to improve the withstand voltage performance of the semiconductor device, and also make the first distance between the reduced surface field effect layer and the drift region set to be greater than zero, so as to ensure the reduced surface field effect layer and the drift region There is a certain electron flow path between them to reduce the on-resistance of the semiconductor device. Therefore, both the withstand voltage performance and the on-resistance performance of the laterally diffused metal oxide semiconductor device provided according to the present invention can be optimized.
以下將參照圖式更詳細地描述本發明。在各個圖式中，相同的組成部分採用類似的圖式標記來表示。為了清楚起見，圖式中的各個部分沒有按比例繪製。此外，可能未示出某些公知的部分。為了簡明起見，可以在一幅圖中描述經過數個步驟後獲得的結構。在下文中描述了本發明的許多特定的細節，例如每個組成部分的結構、材料、尺寸、處理技術和技術，以便更清楚地理解本發明。但正如所屬技術領域中具有通常知識者能夠理解的那樣，可以不按照這些特定的細節來實現本發明。
圖2為依據本發明實施例一提供的一種橫向擴散金屬氧化物半導體裝置200的結構示意圖。依據本發明實施例一提供的半導體裝置主要包括：基層，位於所述基層中且具有第一摻雜類型的減小表面場效應層，位於所述基層中且位於所述減小表面場效應層之上的漂移區，所述漂移區為第二摻雜類型，位於所述漂移區中的汲極區，所述汲極區為第二摻雜類型，其中，所述減小表面場效應層與所述漂移區之間的第一間距大於零。
在半導體裝置200中，第一摻雜類型為P型，第二摻雜類型為n型，當然在其它類型中，所述第一摻雜類型可以為n型，而第二摻雜類型為p型。所述基層由P型摻雜的基板PSUB和位於P型基板PSUB中的N型高壓井區HVNW構成，在其它實施例中，所述基層也可以僅由半導體基板構成。N型漂移區N-drift位於N型高壓井區HVNW中，透過調節N型漂移區N-drift的摻雜濃度來調節半導體裝置200的崩潰電壓Bv。N+汲極區相對於N型漂移區N-drift重摻雜，其用於與汲電極Drain(圖2中僅用連接端子示意，並未畫出具體的汲電極Drain)電連接。
所述減小表面場效應層用於輔助耗盡所述漂移區，以使得所述漂移區具有較高的摻雜濃度時，仍然能夠被快速耗盡，以減小了半導體裝置200的表面電場，使得半導體裝置200既具有較低的導通電阻Rdson，又具有較高的崩潰電壓Bv。為了更大空間的降低半導體裝置200的導通電阻Rdson，所述減小表面場效應層與所述漂移區之間的第一間距需要確保大於零，即保證所述減小表面場效應層與所述漂移區之間有一定空間以供電子流經。此外，為了更好的調節半導體裝置200的耐壓特性，需要根據所述漂移區的摻雜濃度來調節所述第一間距的大小，其中，所述漂移區的摻雜濃度越大，就更加需要所述減小表面場效應層的輔助耗盡，則所述第一間距越小，反之亦然。在半導體裝置200中，所述減小表面場效應層可以為形成於N型高壓井區HVNW中的P型埋層PBL。
如圖2所示，半導體裝置200還包括第一摻雜類型的體區以及位於所述體區中且具有第二摻雜類型的源極區，所述體區位於所述基層中並位於所述減小表面場效應層之上。為了在更接近半導體裝置200表面的位置提供足夠的第一類型的摻雜劑(與第一摻雜類型對應，如第一摻雜類型為P型，則第一類型的雜質為P型摻雜劑)，以更好的輔助耗盡靠近汲極區域附近的區域，以降低該區域的表面電場，所述減小表面場效應層與所述體區之間的第二間距需要設置得小於或等於所述第一間距，即所述減小表面場效應層更靠近所述體區。在半導體裝置200中，所述體區為P型摻雜的體區Pbody，N+型源極區位於所述體區Pbody中，以用於源電極Source(圖2中僅用連接端子示意，並未畫出具體的源電極Source)電連接。在半導體裝置200中，由於所述減小表面場效應層為一個P型埋層PBL，則為了確保所述第一間距大於或等於所述第二間距，在第一方向上，所述漂移區的厚度小於所述體區的厚度，其中，所述第一方向是指所述減小表面場效應層與所述漂移區的堆疊方向。
繼續參考圖2所示，半導體裝置200還包括位於所述基層的第一表面且與所述源極區相鄰的第一介電質層，以及位於所述第一介電質層上的第一導體，此外還包括位於所述第一介電質層和汲極區之間的耐壓層，且所述第一導體的一部分還位於部分所述耐壓層上。在半導體裝置200中，所述第一介電質層(圖中未標記出來)作為閘極介電質層，所述第一導體為閘極導體，以用於與閘電極Gate(圖2中僅用連接端子示意，並未畫出具體的閘電極Gate)電連接。所述第一介電質層可以為氧化物層，如SiO2層，而所述第一導體可以為多晶矽層Ploy1，其覆蓋在所述第一介電質層上並延伸至部分所述耐壓層上。所述耐壓層可以為第二介電質層，如厚氧層Oxide，厚氧層Oxide可以為鳥嘴型，其中所述第二介電質層的厚度大於所述第一介電質層的厚度。所述第二間距需要設置得小於所述第一間距，就是為了更好的輔助耗盡鳥嘴區域，降低鳥嘴區域的電場，提高裝置的熱載流子特性。
此外，如圖2所示，在所述體區中，還設置有與所述體區摻雜類型相同的體接觸區，如體接觸區P+，該體接觸區與源極區相接觸，並與所述源極區接相同的電位，例如均與源電極Source電連接。
圖3為依據本發明實施例二提供的一種橫向擴散金屬氧化物半導體裝置300的結構示意圖。半導體裝置300與半導體裝置200的不同之處僅在於，在半導體裝置300中，所述減小表面場效應層的第一表面(靠近所述漂移區的一面)與所述基層的第一表面之間的間距並非均是相等的，而是位於所述體區下方的所述減小表面場效應層的第一表面與所述基層的第一表面之間的第三間距小於位於所述漂移區下方的所述減小表面場效應層的第一表面與所述基層的第一表面之間的第四間距，即使得所述體區下方的所述減小表面場效應層儘量靠近體區，以盡可能的降低表面電場，提高半導體裝置300的崩潰電壓，而使靠近所述漂移區下方的減小表面場效應層與漂移區之間留有一定空間，以最大幅度的降低半導體裝置300的導通電阻。
在半導體裝置300中，所述表面場效應層可以由埋層在所述基層中且彼此相接觸的第一埋層和第二埋層構成，所述第一埋層的至少部分位於所述體區下方，所述第二埋層的至少部分位於所述漂移區下方，所述第一埋層與所述基層的第一表面之間的間距為所述第三間距，所述第二埋層與所述基層的第一表面之間的間距為所述第四間距。如所述第一埋層為P型埋層PBL1，所述第二埋層為P型埋層PBL2，其中使得第一埋層PBL1儘量靠近P型體區Pbody，如二者可以直接接觸，那麼施加在Pbody上的源電極電壓(通常為參考零地的電壓)會透過Pbody施加在PBL1上，以避免動態的Rdson發生，而第二埋層PBL與漂移區N-drift不接觸，即所述第一間距大於零，以給電子提供更寬的電流路徑，更大空間的降低半導體裝置300的Rdson。
圖4為依據本發明實施例三提供的一種橫向擴散金屬氧化物半導體裝置400的結構示意圖。半導體裝置400與半導體裝置200的不同之處僅在於，在半導體裝置400還包括位於所述基層中，且位於所述減小表面場效應層下方的隔離層，所述隔離層將所述減小表面場效應層與所述基層隔離，以利於半導體裝置400的高壓應用在本實施例中，所述隔離層可以為n型摻雜的第三埋層NBL，其位於高壓井HVNW中，且位於埋層PBL下方，第三埋層NBL的摻雜濃度相對於高壓井HVNW而言，為重摻雜。同樣，在半導體裝置300中的減小表面場效應層下方也可以設置半導體裝置400中所述的隔離層。
圖5為依據本發明實施例四提供的一種橫向擴散金屬氧化物半導體裝置500的結構示意圖。半導體裝置500與半導體裝置200的不同之處僅在於，還包括第二導體，全部位於所述耐壓層上，而所述第一導體全部位於所述第一介電質層上，且所述第一導體和第二導體空間隔離，所述空間隔離是所述第一導體和第二導體在空間位置上是不接觸的，是相互隔開的。
如圖5所示，所述第一導體同樣可以為多晶矽poly1，而所述第二導體為多晶矽Ploy2。其中，多晶矽Poly1與閘電極Gate(圖5中僅用連接端子示意，並未畫出具體的閘電極Gate)電連接，而多晶矽Poly2與第一場板電極Plate1(圖5中僅用連接端子示意，並未畫出具體的場板電極Plate1)電連接。第一場板電極Plate1可以與源電極Source接相同的電位，即第一場板電極Plate1與源電極Source電連接，第一場板電極Plate1也可以單獨接其它電位，且第一場板電極Plate1與閘電極Gate接不同的電位。由於第一場板電極Plate1與閘電極Gate接不同的電位，在閘電極Gate所接的電位使得半導體裝置500處於關斷狀態時，第一場板電極Plate1透過接收一定的電位，仍然可以輔助耗盡所述漂移區，以保持半導體裝置500處於關斷狀態下時的耐高壓性。此外，由於所述第一導體全部位於所述第一介電質層上，使得其與汲極區域(汲極區所在的區域)的交疊部分變小，可以大幅度降低閘極電荷Qgd，使得半導體裝置500可以應用於高頻領域。半導體裝置500中的第一導體和第二導體的結構也同樣可以應用到半導體裝置300與半導體裝置400中。
圖6為依據本發明實施例五提供的一種橫向擴散金屬氧化物半導體裝置600的結構示意圖。 半導體裝置600與半導體裝置500基本相同，不同之處僅在於，所述第二導體，即多晶矽Poly2的一部分還位於所述第一介電質層上，多晶矽Ploy2從所述第一介電質層的部分上延伸至厚氧層Oxide上，以使得多晶矽Poly2的部分覆蓋在所述第一介電質層和厚氧層Oxide的交界處上方，有效的降低了半導體裝置600的閘極電荷Qgd。同樣，圖6中的第一導體和第二導體結構也可以用於到半導體裝置300與半導體裝置400中。
圖7為依據本發明實施例六提供的一種橫向擴散金屬氧化物半導體裝置700的結構示意圖。半導體裝置700與半導體裝置500基本相同，不同之處僅在於，所述第一導體，即多晶矽Poly1的一部分還位於耐壓層，即厚氧層Oxide上，多晶矽Ploy1覆蓋所述第一介電質層，並從所述第一介電質層上延伸至部分厚氧層Oxide上，以使得多晶矽Poly1的部分覆蓋在所述第一介電質層和厚氧層Oxide的交界處上方，有效的降低了半導體裝置700的閘極電荷Qgd。同樣，圖7中的第一導體和第二導體結構也可以用於到半導體裝置300與半導體裝置400中。
圖8為依據本發明實施例七提供的一種橫向擴散金屬氧化物半導體裝置800的結構示意圖。半導體裝置800與半導體裝置700基本相同，不同之處僅在於，半導體裝置800還包括至少一個第三導體，各個所述第三導體均位於所述耐壓層上，且彼此空間隔離，且與所述第二導體相鄰的一個所述第三導體與所述第二導體空間隔離。在半導體裝置800中，所述第三半導體層可以為多晶矽Poly3，各個多晶矽Ploy3與各個對應的第二場板電極(圖8中未畫出)電連接，各個所述第二場板電極與所述第一場板電極Plate1所接的電位不同，且在各個所述第二場板電極中，與越靠近汲極區N+的多晶矽Ploy3電連接的第二場板所接的電位越高，這樣可以進一步提高裝置的耐壓性能。此外，與所述第一場板電極Plate1相鄰的一個所述第二場板電極之間，以及各個相鄰的所述第二場板電極之間均可以設置電阻。同樣，圖8中的第一導體、第二導體、第三導體的結構也可以用於到半導體裝置300與半導體裝置400中。
圖9為依據本發明實施例八提供的一種橫向擴散金屬氧化物半導體裝置900的結構示意圖。半導體裝置900與半導體裝置500基本相同，但是在本實施例中，提供了源電極Source的具體結構。如圖9所示，源電極Source與源極區電連接，並延伸至至少部分所述第二導體(多晶矽Ploy2)的上方，使得所述第一導體與第二導體斷開的位置處所裸露的所述第一介電質層和/或耐壓層的上方被所述源電極Source覆蓋(此處的覆蓋，並非指所述源電極Source直接與所裸露的所述第一介電質層和/或耐壓層接觸覆蓋，而是非接觸覆蓋，即所述源電極Source位於所裸露的所述第一介電質層和/或耐壓層的上方)。所述第一導體和第二導體的斷開處的電場可能會出現跌落，而在半導體裝置900中，該斷開位置處被所述源電極Source非接觸覆蓋，可以避免該斷開位置處的電場出現跌落的現象，從而改善了半導體裝置900的耐壓性能。同樣，半導體裝置900中的源電極結構可以應用於半導體裝置600、半導體裝置700及半導體裝置800中。
此外，本發明還提供了一種橫向擴散金屬氧化物半導體裝置的製造方法，其主要包括：在基層中形成具有第一摻雜類型的減小表面場效應層，以及在所述基層中形成具有第二摻雜類型的漂移區，並在所述漂移區中形成第二摻雜類型的汲極區，所述漂移區位於所述減小表面場效應層的上方，且使得所述漂移區與所述減小表面場效應層之間的第一間距大於零。
依據本發明提供的製造方法形成的半導體裝置之一可以如圖8所示，先在半導體基板PSUB中形成高壓井區HVNW，半導體基板PSUB以及位於半導體基板PSUB中的高壓井區HVNW作為所述基層。然後利用LOCOS技術形成場氧化層(圖8中未畫出)，接著用遮罩現代高壓汲極區域並利用LOCOS技術形成耐壓區層Oxide，再接著形成所述漂移區和減小表面場效應層。
此外，在形成所述減小表面場效應層後，所述製造方法還包括在所述基層中形成如圖3中所示的隔離層，如NBL層，所述隔離層位於所述減小表面場效應層下方，以將所述減小表面場效應層和所述基層隔離。
依據本發明提供的半導體裝置的製造方法還包括在形成所述隔離層之後，形成如圖2-9中所示的第一介電質層，即閘介電質層，然後在所述第一介電質層上和耐壓層Oxide上沉積導體層，如多晶矽層，接著蝕刻所沉積的導體層，並可以形成如圖2-9所示的第一導體、第二導體和第三導體。其中，所述第一介電質層與所述源極區相鄰。
在形成第一導體和第二導體之後，所述製造方法還包括形成圖2-9中各圖中的體區，如Pbody區，還可以進一步的在所述體區內注入形成LDD區(輕摻雜區)，如在Pbody體區中形成n型的輕摻雜區NLDD區。其中，形成的所述體區與所述減小表面場效應層之間的第二間距需要小於或等於所述第一間距。
在形成所述體區和輕摻雜區後，還需在圖2-9中所示的第一導體、第二導體和/或第三導體的側壁形成側牆。
最後，再在所述體區和漂移區內分別形成源極區和汲極區，以及形成源電極、汲電極、閘電極以及各個場板電極，其中，在形成所述源電極時，可以使得源電極延伸至至少部分所述第二導體的上方。
此外，在形成所述減小表面場效應層時，需要根據所述漂移區的摻雜濃度來調節所述第一間距的大小，所述漂移區的摻雜濃濃度越高，所述第一間距的大小越小。以及在形成所述減小表面場效應層時，還可以用兩塊遮罩形成如圖3中所示具有兩個P埋層的減小表面場效應層，從而使得所述減小表面場效應層與所述基層的第一表面之間的第三間距小於位於所述漂移區下方的所述減小表面場效應層與所述基層的第一表面之間的第四間距。
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域中具有通常知識者能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和均等物的限制。Hereinafter, the present invention will be described in more detail with reference to the drawings. In each figure, the same component parts are represented by similar figure symbols. For the sake of clarity, the various parts in the drawing are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present invention are described, such as the structure, material, size, processing technique and technology of each component, in order to understand the present invention more clearly. However, as those with ordinary knowledge in the technical field can understand, the present invention may not be implemented according to these specific details.
FIG. 2 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 200 according to the first embodiment of the present invention. The semiconductor device provided according to the first embodiment of the present invention mainly includes: a base layer, a surface field reduction layer with a first doping type located in the base layer, and a surface field effect reduction layer located in the base layer and located in the surface field effect reduction layer Above the drift region, the drift region is of the second doping type, is located in the drain region of the drift region, the drain region is of the second doping type, wherein the surface field effect reduction layer The first distance from the drift region is greater than zero.
In the semiconductor device 200, the first doping type is p-type, and the second doping type is n-type. Of course, in other types, the first doping type may be n-type and the second doping type is p-type. type. The base layer is composed of a P-type doped substrate PSUB and an N-type high-voltage well region HVNW located in the P-type substrate PSUB. In other embodiments, the base layer may also be composed of only a semiconductor substrate. The N-type drift region N-drift is located in the N-type high voltage well region HVNW, and the breakdown voltage Bv of the semiconductor device 200 is adjusted by adjusting the doping concentration of the N-type drift region N-drift. The N+ drain region is heavily doped with respect to the N-type drift region N-drift, and it is used for electrical connection with the drain electrode Drain (only the connection terminal is shown in FIG. 2 and the specific drain electrode Drain is not shown).
The surface field effect reduction layer is used to assist in depletion of the drift region, so that when the drift region has a higher doping concentration, it can still be quickly depleted, so as to reduce the surface electric field of the semiconductor device 200 , So that the semiconductor device 200 has a lower on-resistance Rdson and a higher breakdown voltage Bv. In order to reduce the on-resistance Rdson of the semiconductor device 200 in a larger space, the first distance between the reduced surface field effect layer and the drift region needs to be ensured to be greater than zero, that is, to ensure that the reduced surface field effect layer and the drift region There is a certain space between the drift regions for electrons to flow through. In addition, in order to better adjust the withstand voltage characteristics of the semiconductor device 200, the size of the first gap needs to be adjusted according to the doping concentration of the drift region. The greater the doping concentration of the drift region, the more If the auxiliary depletion of the surface field effect layer is reduced, the first distance is smaller, and vice versa. In the semiconductor device 200, the surface field effect reduction layer may be a P-type buried layer PBL formed in the N-type high voltage well region HVNW.
As shown in FIG. 2, the semiconductor device 200 further includes a body region of a first doping type and a source region located in the body region and having a second doping type. The body region is located in the base layer and is located in the base layer. Said to reduce the surface field effect layer. In order to provide sufficient dopants of the first type at a position closer to the surface of the semiconductor device 200 (corresponding to the first doping type, if the first doping type is P-type, the first type of doping is P-type doping) Agent) to better assist in depleting the area near the drain region to reduce the surface electric field of the area. The second distance between the reduced surface field effect layer and the body region needs to be set to be smaller than or It is equal to the first distance, that is, the surface field effect reduction layer is closer to the body region. In the semiconductor device 200, the body region is a P-type doped body region Pbody, and an N+-type source region is located in the body region Pbody for the source electrode Source (only the connection terminals are shown in FIG. 2, and The specific source electrode (Source) electrical connection is not shown. In the semiconductor device 200, since the surface field effect reduction layer is a P-type buried layer PBL, in order to ensure that the first pitch is greater than or equal to the second pitch, in the first direction, the drift region The thickness of is smaller than the thickness of the body region, wherein the first direction refers to the stacking direction of the surface field effect reduction layer and the drift region.
Continuing to refer to FIG. 2, the semiconductor device 200 further includes a first dielectric layer located on the first surface of the base layer and adjacent to the source region, and a second dielectric layer located on the first dielectric layer A conductor, in addition, includes a voltage withstand layer located between the first dielectric layer and the drain region, and a part of the first conductor is also located on a portion of the voltage layer. In the semiconductor device 200, the first dielectric layer (not marked in the figure) serves as a gate dielectric layer, and the first conductor is a gate conductor for connecting with the gate electrode Gate (in FIG. 2 Only the connection terminals are used to indicate the electrical connection of the specific gate electrode (Gate). The first dielectric layer may be an oxide layer, such as an SiO2 layer, and the first conductor may be a polysilicon layer Ploy1, which covers the first dielectric layer and extends to a part of the withstand voltage Layer up. The pressure-resistant layer may be a second dielectric layer, such as a thick oxygen layer Oxide, which may be a bird's beak type, wherein the thickness of the second dielectric layer is greater than that of the first dielectric layer thickness of. The second distance needs to be set smaller than the first distance, in order to better assist in depleting the bird's beak area, reduce the electric field in the bird's beak area, and improve the hot carrier characteristics of the device.
In addition, as shown in FIG. 2, in the body region, a body contact region with the same doping type as the body region is also provided, such as a body contact region P+, which is in contact with the source region, and It is connected to the same potential as the source region, for example, both are electrically connected to the source electrode Source.
FIG. 3 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 300 according to the second embodiment of the present invention. The only difference between the semiconductor device 300 and the semiconductor device 200 is that, in the semiconductor device 300, the first surface (the side close to the drift region) of the surface field effect layer is different from the first surface of the base layer. The distances between each other are not all equal, but the third distance between the first surface of the surface-reducing field effect layer located below the body region and the first surface of the base layer is smaller than that located in the drift region The fourth distance between the first surface of the lower surface field effect layer and the first surface of the base layer, that is, the lower surface field effect layer of the body region is made as close as possible to the body region, In order to reduce the surface electric field as much as possible, increase the breakdown voltage of the semiconductor device 300, and leave a certain space between the surface field reduction layer near the drift region and the drift region, so as to reduce the semiconductor device 300 to the greatest extent. On resistance.
In the semiconductor device 300, the surface field effect layer may be composed of a first buried layer and a second buried layer that are buried in the base layer and are in contact with each other, and at least part of the first buried layer is located in the body. Region, at least part of the second buried layer is located below the drift region, the distance between the first buried layer and the first surface of the base layer is the third distance, and the second buried layer The distance from the first surface of the base layer is the fourth distance. For example, the first buried layer is a P-type buried layer PBL1, and the second buried layer is a P-type buried layer PBL2, wherein the first buried layer PBL1 is made as close as possible to the P-type body region Pbody. If the two can be in direct contact, then The source electrode voltage applied to Pbody (usually a voltage referenced to zero ground) is applied to PBL1 through Pbody to avoid dynamic Rdson, and the second buried layer PBL does not contact the drift region N-drift, that is, the The first interval is greater than zero to provide a wider current path for the electrons and reduce the Rdson of the semiconductor device 300 in a larger space.
4 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 400 according to the third embodiment of the present invention. The only difference between the semiconductor device 400 and the semiconductor device 200 is that the semiconductor device 400 further includes an isolation layer located in the base layer and below the surface field effect reduction layer, and the isolation layer reduces the surface field effect layer. The surface field effect layer is isolated from the base layer to facilitate the high-voltage application of the semiconductor device 400. In this embodiment, the isolation layer may be an n-type doped third buried layer NBL, which is located in the high-voltage well HVNW and is located Below the buried layer PBL, the doping concentration of the third buried layer NBL is heavily doped relative to the high-pressure well HVNW. Similarly, the isolation layer described in the semiconductor device 400 may also be provided under the surface field effect reduction layer in the semiconductor device 300.
FIG. 5 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 500 according to the fourth embodiment of the present invention. The only difference between the semiconductor device 500 and the semiconductor device 200 is that it also includes a second conductor, all located on the withstand voltage layer, and all the first conductors are located on the first dielectric layer, and the The first conductor and the second conductor are spatially separated, and the spatial separation means that the first conductor and the second conductor are not in contact with each other in a spatial position and are separated from each other.
As shown in FIG. 5, the first conductor may also be polysilicon poly1, and the second conductor may be polysilicon Ploy2. Among them, the polysilicon Poly1 is electrically connected to the gate electrode Gate (only the connection terminal is shown in Figure 5, and the specific gate electrode Gate is not shown), and the polysilicon Poly2 is electrically connected to the first field plate electrode Plate1 (only the connection terminal is shown in Figure 5). , The specific electrical connection of the field plate electrode Plate1) is not shown. The first field plate electrode Plate1 can be connected to the same potential as the source electrode Source, that is, the first field plate electrode Plate1 is electrically connected to the source electrode Source, the first field plate electrode Plate1 can also be separately connected to other potentials, and the first field plate electrode Plate1 Connect the gate electrode to a different potential. Since the first field plate electrode Plate1 and the gate electrode Gate are connected to different potentials, when the potential connected to the gate electrode Gate makes the semiconductor device 500 in the off state, the first field plate electrode Plate1 can still assist in power consumption by receiving a certain potential. The drift region is exhausted to maintain the high voltage resistance of the semiconductor device 500 when it is in the off state. In addition, since the first conductor is all located on the first dielectric layer, the overlap between it and the drain region (the region where the drain region is located) becomes smaller, which can greatly reduce the gate charge Qgd. The semiconductor device 500 can be applied to the high-frequency field. The structures of the first conductor and the second conductor in the semiconductor device 500 can also be applied to the semiconductor device 300 and the semiconductor device 400.
FIG. 6 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 600 according to the fifth embodiment of the present invention. The semiconductor device 600 is basically the same as the semiconductor device 500. The only difference is that the second conductor, that is, a part of the polysilicon Poly2 is also located on the first dielectric layer, and the polysilicon Ploy2 is removed from the first dielectric layer. Extends to the thick oxide layer Oxide, so that the polysilicon Poly2 part covers the interface between the first dielectric layer and the thick oxide layer Oxide, effectively reducing the gate charge Qgd of the semiconductor device 600. Similarly, the first conductor and second conductor structure in FIG. 6 can also be used in the semiconductor device 300 and the semiconductor device 400.
FIG. 7 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 700 according to the sixth embodiment of the present invention. The semiconductor device 700 is basically the same as the semiconductor device 500. The only difference is that the first conductor, that is, part of the polysilicon Poly1 is also located on the withstand voltage layer, that is, the thick oxygen layer Oxide, and the polysilicon Ploy1 covers the first dielectric. Layer and extend from the first dielectric layer to a part of the thick oxygen layer Oxide, so that part of the polysilicon Poly1 covers the interface between the first dielectric layer and the thick oxygen layer Oxide, effectively The gate charge Qgd of the semiconductor device 700 is reduced. Similarly, the first conductor and second conductor structure in FIG. 7 can also be used in the semiconductor device 300 and the semiconductor device 400.
FIG. 8 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 800 according to a seventh embodiment of the present invention. The semiconductor device 800 is basically the same as the semiconductor device 700. The only difference is that the semiconductor device 800 further includes at least one third conductor. One of the third conductors adjacent to the second conductor is spaced apart from the second conductor. In the semiconductor device 800, the third semiconductor layer may be polysilicon Poly3, each polysilicon Ploy3 is electrically connected to each corresponding second field plate electrode (not shown in FIG. 8), and each second field plate electrode is The first field plate electrode Plate1 is connected to different potentials, and in each of the second field plate electrodes, the second field plate electrically connected to the polysilicon Ploy3 closer to the drain region N+ has a higher potential. The pressure resistance of the device can be further improved. In addition, a resistor may be provided between one of the second field plate electrodes adjacent to the first field plate electrode Plate1 and between each adjacent second field plate electrode. Similarly, the structures of the first conductor, the second conductor, and the third conductor in FIG. 8 can also be used in the semiconductor device 300 and the semiconductor device 400.
FIG. 9 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device 900 according to the eighth embodiment of the present invention. The semiconductor device 900 is basically the same as the semiconductor device 500, but in this embodiment, a specific structure of the source electrode Source is provided. As shown in FIG. 9, the source electrode Source is electrically connected to the source region and extends to at least part of the second conductor (polysilicon Ploy2), so that the position where the first conductor is disconnected from the second conductor is exposed The upper part of the first dielectric layer and/or the withstand voltage layer is covered by the source electrode Source (covering here does not mean that the source electrode Source is directly connected to the exposed first dielectric layer and /Or the voltage-resistant layer is in contact coverage, but is non-contact covering, that is, the source electrode Source is located above the exposed first dielectric layer and/or the voltage-resistant layer). The electric field at the disconnection of the first conductor and the second conductor may drop. However, in the semiconductor device 900, the disconnection position is covered by the source electrode Source in a non-contact manner, which can prevent the disconnection position. The electric field drops, thereby improving the withstand voltage performance of the semiconductor device 900. Similarly, the source electrode structure in the semiconductor device 900 can be applied to the semiconductor device 600, the semiconductor device 700, and the semiconductor device 800.
In addition, the present invention also provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which mainly includes: forming a reduced surface field effect layer having a first doping type in a base layer, and forming a first doped layer in the base layer. A drift region of two doping types, and a drain region of the second doping type is formed in the drift region. The drift region is located above the surface-reducing field effect layer and makes the drift region and the Said reducing the first distance between the surface field effect layers is greater than zero.
One of the semiconductor devices formed according to the manufacturing method provided by the present invention may be as shown in FIG. 8. First, a high-voltage well region HVNW is formed in the semiconductor substrate PSUB, and the semiconductor substrate PSUB and the high-voltage well region HVNW located in the semiconductor substrate PSUB are used as the base layer. . Then use LOCOS technology to form a field oxide layer (not shown in Figure 8), then mask the modern high-voltage drain region and use LOCOS technology to form a withstand voltage zone layer Oxide, and then form the drift zone and reduce the surface field effect Floor.
In addition, after forming the reduced surface field effect layer, the manufacturing method further includes forming an isolation layer as shown in FIG. 3 in the base layer, such as an NBL layer, where the isolation layer is located on the reduced surface Under the field effect layer to isolate the surface-reducing field effect layer and the base layer.
The manufacturing method of the semiconductor device provided according to the present invention further includes forming the first dielectric layer as shown in FIGS. 2-9, that is, the gate dielectric layer, after forming the isolation layer, and then forming the first dielectric layer in the first dielectric layer. A conductor layer, such as a polysilicon layer, is deposited on the dielectric layer and the withstand voltage layer Oxide, and then the deposited conductor layer is etched, and the first conductor, the second conductor and the third conductor as shown in FIGS. 2-9 can be formed. Wherein, the first dielectric layer is adjacent to the source region.
After forming the first conductor and the second conductor, the manufacturing method further includes forming the body region in each figure in FIGS. 2-9, such as the Pbody region, and can further implant the LDD region (lightweight) in the body region. Doped region), for example, an n-type lightly doped region NLDD region is formed in the Pbody body region. Wherein, the second distance between the formed body region and the surface field effect reduction layer needs to be less than or equal to the first distance.
After the body region and the lightly doped region are formed, sidewall spacers need to be formed on the sidewalls of the first conductor, the second conductor, and/or the third conductor shown in FIGS. 2-9.
Finally, in the body region and the drift region, a source region and a drain region are formed respectively, and a source electrode, a drain electrode, a gate electrode, and each field plate electrode are formed. When the source electrode is formed, The source electrode extends above at least part of the second conductor.
In addition, when forming the reduced surface field effect layer, the size of the first pitch needs to be adjusted according to the doping concentration of the drift region. The higher the doping concentration of the drift region, the higher the doping concentration of the drift region. The smaller the spacing. And when forming the reduced surface field effect layer, two masks can also be used to form the reduced surface field effect layer having two P buried layers as shown in FIG. 3, so that the reduced surface field effect The third distance between the layer and the first surface of the base layer is smaller than the fourth distance between the reduced surface field effect layer under the drift zone and the first surface of the base layer.
According to the embodiments of the present invention described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those with ordinary knowledge in the technical field can make good use of the present invention and make modifications based on the present invention. . The present invention is only limited by the scope of the patent application and its full scope and equivalents.