TWI717491B - Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit - Google Patents

Abstract

The invention relates to a method for manufacturing a structure comprising a first substrate (1) comprising at least one electronic component (10) likely to be damaged by a temperature higher than 400 °C and a semi-conductor layer extending on said first substrate, characterised in that it comprises the following steps of: (a) providing a first bonding metal layer (11) on the first substrate (1), (b) providing a second substrate (2) comprising successively: - a semi-conductor base substrate (20), - a stack (21) of a plurality of semi-conductor epitaxial layers, a layer (210) of Si_x Ge_1-x , with 0 ≤ x ≤ 1 being located at the surface of said stack (21) opposite to the base substrate (20), - a second bonding metal layer (22), (c) bonding the first substrate and the second substrate through the first and second bonding metal layers (11, 22), said bonding step being carried out at a temperature lower than or equal to 400 °C, (d) removing a part of the second substrate so as to transfer the layer (210) of Si_x Ge_1-x on the first substrate (1), said removing comprising at least selectively chemically etching a layer of the second substrate (2) relative to the Si_x Ge_1-x layer (210).

Description

Method for manufacturing structure for forming three-dimensional monolithic integrated circuit

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a structure for forming a monolithic integrated circuit, and a structure and a substrate intended to implement the method.

BACKGROUND OF THE INVENTION In view of increasing density and reducing the size of electronic components, three-dimensional (3D) monolithic integrated circuits are particularly promising because they particularly avoid the problem of misalignment of these components.

The manufacture of such circuits involves transferring the semiconductor layer to a substrate that already contains at least one electrical component, such as a transistor.

However, when the component may be damaged when subjected to temperatures above 400°C, this transfer is controversial.

In fact, there is no method so far that enables the transfer of semiconductor layers with good crystal quality and only involves steps that can be performed at temperatures below 400°C.

Therefore, the first option is to form the semiconductor layer by directly depositing the semiconductor layer on a substrate containing at least one electronic component. However, such deposition at a temperature lower than 400°C results in a polycrystalline or amorphous layer that does not have the crystal qualities required for subsequent formation of other electronic components.

Another option would be to use the Smart Cut ^™ method, which is well known for transferring the semiconductor layer from the donor substrate to the acceptor substrate. This method involves the formation of weakened areas in the donor substrate by implanting atomic species such as hydrogen and/or helium. However, this implantation creates defects in the transfer layer, which can only be dealt with by annealing at a temperature higher than 500°C so far.

The so-called BSOI (bonded silicon on insulator) and BESOI (bonded and etched back silicon on insulator) technologies are expected to transfer the silicon layer from the bonded bulk substrate to the substrate containing at least one electronic component. However, if the temperature used does not exceed 400°C, these techniques can neither allow the formation of extremely thin layers nor achieve satisfactory bonding energy.

SUMMARY OF THE INVENTION Therefore, one object of the present invention is to design a method for manufacturing a structure including a first substrate and a semiconductor layer. The first substrate includes at least one electronic component that may be damaged by temperatures above 400°C. The semiconductor layer is Extending on the first substrate, the method enables the semiconductor layer to have the properties required for the desired application, and the method provides a gap between the semiconductor layer and the first substrate to be obtained without using a temperature higher than 400°C Good adhesion.

According to the present invention, there is provided a method for manufacturing a structure including a first substrate and a semiconductor layer, the first substrate including at least one electronic component that may be damaged by a temperature higher than 400°C, and the semiconductor layer extending on the first substrate The method is characterized by including the following steps: (a) providing a first bonding metal layer on a first substrate called an acceptor substrate, (b) providing a second substrate called a donor substrate, which in turn includes: -A semiconductor base substrate,-a stack of multiple semiconductor epitaxial layers, a Si _x Ge _1-x layer, where 0≤x≤1, the Si _x Ge _1-x layer is located on the surface of the stack opposite to the base substrate,- The second bonding metal layer, (c) bonding the first substrate and the second substrate via the first and second bonding metal layers, the bonding step is performed at a temperature lower than or equal to 400°C, (d) removing the second A portion of the substrate thereby transfers the Si _x Ge _1-x layer on the first substrate, and the removal includes at least selectively chemically etching the layer of the second substrate relative to the Si _x Ge _1-x layer.

Therefore, the Si _x Ge _1-x layer has excellent crystal quality and higher charge carrier mobility than a relaxed single crystal silicon layer. Therefore, the formed structure is the best for manufacturing three-dimensional monolithic integrated circuits for high-performance and/or low-power applications.

On the other hand, metal-metal bonding provides strong bonding energy even at a temperature not exceeding 400°C, which is substantially higher than the energy provided by dielectric-dielectric bonding performed at this temperature. In addition, unlike the dielectric-dielectric interface, the metal-metal interface has the advantage of not being corroded by the hydrofluoric acid solution that may be used to selectively etch at least one layer of the second substrate.

In this context, the phrase "layer A on layer B" or "layer B underlies layer A" does not necessarily imply that layer A and layer B have a common interface; they can actually be separated by one or more intermediate layers. On the other hand, the phrase "layer A is directly on layer B" means that layer A and layer B are in contact with each other.

According to an embodiment, the second substrate includes a dielectric layer between the Si _x Ge _1-x layer and the second bonding metal layer.

The thickness of the dielectric layer is advantageously between 10 nm and 20 nm.

According to an embodiment, the base substrate is a silicon substrate.

According to a preferred embodiment, the stack from the base substrate sequentially includes:-a silicon-germanium layer with a gradually changing composition in its thickness,-a silicon-germanium layer with a constant composition in its thickness,-a Si _y Ge _1-y layer , Where 0≤y≤1 and y is different from x, the Si _y Ge _1-y layer has a composition different from that of the silicon-germanium layer (212) having a constant composition in its thickness, so as to form the Si _x Ge _1- etching the barrier layer _x layer, -Si _x Ge _1-x layer.

Particularly advantageous:-at the surface of the layer opposite to the base substrate, the composition of the silicon-germanium layer with a gradually changing composition in its thickness is Si _0.8 Ge _0.2 ,-the silicon-germanium with a constant composition in its thickness The composition of the layer is Si _0.8 Ge _0.2 , the thickness of the layer is between 0.5 μm and 2 μm,-the composition of the etching barrier layer is selected from Si and Si _0.6 Ge _0.4 , and the thickness of the layer is between 10 nm and 50 nm In the meantime, the composition of the -Si _x Ge _1-x layer is selected from Si _0.8 Ge _0.2 , Si and Ge, and the thickness of the layer is between 5 nm and 50 nm.

The first and second bonding metal layers may include titanium, nickel, copper, and/or tungsten.

According to one embodiment, step (b) comprises the following successive steps:-epitaxially grow a silicon-germanium layer with a graded composition in its thickness,-epitaxially grow a silicon-germanium layer with a constant composition in its thickness,-polish a silicon-germanium layer with a constant composition the composition of silicon - germanium layer, - polishing silicon - epitaxial growth of Si _y Ge _1-y layer on the germanium layer, wherein 0≤y≤1 and y is different from x, the Si _y Ge _1-y layer has a thickness in A silicon-germanium layer with a constant composition has a different composition,-epitaxially grow a Si _x Ge _1-x layer on the Si _y Ge _1-y layer,-deposit a second bonding metal layer.

According to one embodiment, between the step of epitaxially growing the Si _x Ge _1-x layer and the step of depositing the second bonding metal layer, step (b) includes a step of depositing a dielectric layer.

After the step of depositing the dielectric layer, step (b) may include densification annealing of the layer.

Particularly advantageously, step (b) further comprises forming a binary or ternary metal alloy layer between the dielectric layer and the second bonding metal layer.

According to one embodiment, step (d) includes withdrawing a part of the thickness of the base substrate by polishing, followed by selectively etching the remaining part of the base substrate.

Particularly advantageously, the etching of the base substrate is performed using TMAH, KOH and/or HF:HNO ₃ solutions.

On the other hand, removing the base substrate can be followed by selective etching of the silicon-germanium layer with a constant composition and a graded composition by means of SC1 solution and/or HF:H ₂ O ₂ :CH ₃ COOH solution.

Another object relates to a method for manufacturing a three-dimensional monolithic integrated circuit, which method includes implementing the above-mentioned method.

More precisely, this method for manufacturing a three-dimensional monolithic integrated circuit includes:-manufacturing a structure including a first substrate and a Si _x Ge _1-x layer by means of the above-mentioned method, and the first substrate includes At least one electronic component damaged by a temperature of 400°C, the Si _x Ge _1-x layer extends on the first substrate,-at least one other is manufactured in the Si _x Ge _1-x layer or on the Si _x Ge _1-x layer Electronic components.

The remarkable feature of this method is that all the steps carried out on the structure are carried out at a temperature lower than or equal to 400°C.

Another objective concerns the structure that may be obtained by the above method.

The structure includes a first substrate and a semiconductor layer, the first substrate includes at least one electronic component that may be damaged by a temperature higher than 400° C., the semiconductor layer extends on the first substrate, and the structure is characterized by the semiconductor layer It is a Si _x Ge _1-x layer, where 0≤x≤1, and the structure includes a metal layer between the first substrate and the semiconductor layer.

According to an embodiment, the structure further includes a dielectric layer between the metal layer and the semiconductor layer.

Advantageously, the structure comprises a binary or ternary metal alloy layer between the metal layer and the dielectric layer.

The at least one electronic component may include a transistor, a memory, a photodetector, a diode, a laser, a switch, an amplifier, and/or a filter.

Another object relates to the donor substrate intended to be used in the above method.

The donor substrate in turn includes:-a semiconductor base substrate,-a stack of multiple semiconductor epitaxial layers, a Si _x Ge _1-x layer, where 0≤x≤1, the Si _x Ge _1-x layer is located between the stack and the base At the opposite surface of the substrate, a metal layer is bonded.

According to an embodiment, the donor substrate further includes a dielectric layer between the Si _x Ge _1-x layer and the metal layer.

The dielectric layer may have a thickness between 10 nm and 20 nm.

According to an embodiment, the base substrate is a silicon substrate.

According to a preferred embodiment, the stacking from the base substrate sequentially includes:-a silicon-germanium layer with a gradually changing composition in its thickness,-a silicon-germanium layer with a constant composition in its thickness,-Si _y Ge _1-y Layer, where 0≤y≤1 and y is different from x, the Si _y Ge _1-y layer has a different composition from the silicon-germanium layer having a constant composition in its thickness, thereby forming a Si _x Ge _1-x layer The etching barrier layer, -Si _x Ge _1-x layer.

Detailed Description of the Preferred Embodiment Figures 1A to 1C illustrate various alternatives to the donor substrate.

Generally speaking, the donor substrate sequentially includes:-a base substrate 20,-a stack 21 of multiple semiconductor epitaxial layers, a Si _x Ge _1-x layer 210 in the stack 21, where 0≤x≤1, the Si _x Ge _{1 The x} layer is located at the surface of the stack opposite to the base substrate 20, intended to transfer the layer to another substrate to form the final structure, and the metal layer 22 is bonded.

The base substrate 20 has a semiconductor material or a stack of different semiconductor materials. According to a specific embodiment, the base substrate has bulk single crystal silicon.

In FIGS. 1A to 1C, the stack 21 is represented as four layers 213, 212, 211, and 210. However, those skilled in the art can change the number and composition of the layers without departing from the scope of the present invention, as long as the layer underlying the layer 210 constitutes an etching barrier layer. In other words, it is possible to perform selective etching on at least one of the stacked layers with respect to the layer 210.

Advantageously, the stacked layer is a silicon, germanium and/or silicon-germanium layer. GaP may be used because this material has a lattice parameter close to that of silicon. Those skilled in the art can select the composition of each layer according to the desired properties of the layer 210 (the composition may be constant or gradual in thickness depending on the situation).

According to a preferred embodiment, the layer 213 formed by epitaxy on the base substrate 20 is a SiGe layer having a gradually changing composition in its thickness, so that the layer (that is, at the surface opposite to the base substrate 20) The final composition is, for example, Si _0.8 Ge _0.2 .

The silicon-germanium layer 212 having the same composition as the final composition of the layer 213 (in this example, Si _0.8 Ge _0.2 ) is formed by epitaxy on the layer 213. The composition of layer 212 is constant in its thickness. The layer 212 is thick, that is, generally has a thickness between 0.5 μm and 2 μm. It is particularly advantageous to perform polishing of the surface of the layer 212 before continuing the epitaxy.

The layer 211 having a material different from that of the layer 212 (for example, if the layer 212 has Si _0.8 Ge _0.2 , the layer 211 has silicon or Si _0.6 Ge _0.4 ) is formed by epitaxy on the layer 212. The thickness of the layer 211 is about 10 nm to 50 nm. The layer 211 is an etching barrier layer facing the underlying layers 212 and 213. Those skilled in the art can select the composition of the layer 211 to provide sufficient etching selectivity, so that etching the base substrate and/or the layers 212 and 213 does not erode the overlying layer 210.

The layer 210 is formed by epitaxy on the layer 211. It is intended to transfer the layer 210 onto another substrate to form the final structure, as will be explained below. The layer 210 has a material different from the material constituting the etching barrier layer 211. For example, the layer 210 has the composition Si _x Ge _1-x , where 0 _≦x≦ 1, and the material of the layer may be limited depending on the difference of the lattice parameters toward the underlying layer 211. For example, the layer 210 may have Si _0.8 Ge _0.2 , silicon or germanium. The thickness of the layer 210 is usually between 5 nm and 50 nm.

The metal layer 22 may be formed of one of the following materials: nickel, copper, tungsten, titanium. This layer is generally deposited by one of the following techniques: physical vapor deposition (PVD), electrodeposition, chemical vapor deposition (CVD). The thickness of the metal layer 22 is usually between 10 nm and 1000 nm.

In the embodiment of FIG. 1A, the metal layer 22 is deposited directly onto the layer 210.

In the embodiment of FIG. 1B, the dielectric layer 23 is deposited on the layer 210 before the metal layer 22 is deposited. This type of dielectric layer is particularly interesting for back gate type applications that require buried oxide. The dielectric layer advantageously has an extremely low thickness (usually between 10 nm and 20 nm). This thin layer is therefore not changed by possible HF etching, because the edge erosion surface is low for this thickness range. The dielectric layer 23 is generally deposited by one of the following techniques: plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), PVD. The deposition of the dielectric layer can be followed by densification annealing.

In the embodiment of FIG. 1C, the binary or ternary metal alloy layer 24 is deposited on the dielectric layer 23 before the metal layer 22 is deposited. The layer 24 has the advantage of promoting the adhesion of the metal layer 22 to the dielectric layer 23.

The donor substrate thus formed can be bonded to another substrate called an acceptor substrate, which contains at least one electronic component that may be damaged by a temperature higher than 400°C.

Such electronic components can be, for example, transistors, memory, light detectors, diodes, lasers, switches, amplifiers, filters, or a combination of these components.

FIG. 2 illustrates an embodiment of the receptor substrate 1.

The substrate 1 includes, for example, a base substrate 20 having bulk silicon, and the base substrate supports a dielectric layer 13 containing a plurality of transistors 10. These transistors belong to the FinFET (Fin Field Effect Transistor) type, which has a non-planar structure.

In order to bond the acceptor substrate to the donor substrate, the bonding metal layer 11 is advantageously formed on the surface of the acceptor substrate 1 that is intended to form a bonding interface. The bonding metal layer 11 can be made of one of the following materials: nickel, titanium, tungsten, and copper.

Then, as illustrated in FIG. 3, the donor substrate and the acceptor substrate are bonded via bonding layers 22 and 11. In this illustration, the donor substrate is the substrate of FIG. 1A, but it can naturally be the substrate of FIG. 1B or FIG. 1C.

Such metal-metal bonding can be performed at low temperatures, that is, at temperatures below 400°C, and provides high bonding energy. Therefore, the bonding step does not damage the electronic component 10.

On the other hand, if the back gate function is necessary in the final structure, the metal layers 11 and 22 can fulfill this function.

Referring to FIG. 4, the layer 210 is transferred from the donor substrate to the acceptor substrate by performing at least one etching step, thereby detaching the layer 210 from the underlying layer of the substrate 2. The etching direction layer 210 must be selective so as not to damage the layer 210.

First, mechanical polishing (also called "grinding") of the base substrate 20 can be performed. This polishing may include a first rough polishing step followed by a fine polishing step. Therefore, most of the base substrate 20 can be removed until the thickness of a few microns remains.

Secondly, the remaining part of the base substrate 20 can be removed by dry polishing or chemical etching. In the case of a silicon substrate, the etching composition is advantageously TMAH, KOH or HF:HNO ₃ .

Third, the layers 213 and 212 can be removed by dry etching or chemical etching. In the case of the silicon-germanium layer, the etching composition may be the composition SC1 (NH ₄ OH:H ₂ O ₂ :H ₂ O) or HF:H ₂ O ₂ :CH ₃ COOH.

Possibly, if the etching selectivity is allowed, the layer 211 can also be removed by etching. In addition, the layer 211 can be removed by dry polishing.

Optionally, different above-mentioned etching steps can be performed by combining different etching compositions. Those who are familiar with this technology can define a suitable composition depending on the material to be etched.

Since in FIG. 4 represents the structure, can be manufactured or at least one other electronic components (not illustrated) on a Si _x Ge _1-x layer 210 Si _x Ge _1-x layer 210.

Finally, the examples just described are undoubtedly only specific and in no way limit the description of the application field of the present invention.

1‧‧‧First substrate 10‧‧‧Electronic component 11‧‧‧First bonding metal layer 12, 20‧‧‧ Base substrate 13, 23‧‧‧Dielectric layer 2.‧‧Second substrate 21‧‧‧Stacked 210‧‧‧Si _x Ge _1-x layer 211‧‧‧Si _y Ge _1-y layer 212, 213‧‧‧Si-germanium layer 22‧‧‧Second bonding metal layer 24‧‧‧Metal alloy layer

Other characteristics and advantages of the present invention will appear from the following detailed description with reference to the accompanying drawings in which:-Figures 1A to 1C are cross-sectional views of donor substrates according to various embodiments of the present invention ,-Figure 2 is a cross-sectional view of a receiver substrate containing at least one electronic component,-Figures 3 and 4 illustrate successive steps of a method for manufacturing a structure according to an embodiment of the present invention.

It should be clarified that, for the sake of legibility of the drawings, the different elements illustrated are not necessarily shown to scale. The same reference symbols in one drawing to another designate the same elements or elements that provide the same functions.

10‧‧‧Electronic components

11‧‧‧First bonding metal layer

12, 20‧‧‧Base substrate

13‧‧‧Dielectric layer

21‧‧‧Stack

210‧‧‧Si _x Ge _1-x layer

211‧‧‧Si _y Ge _1-y layer

212, 213‧‧‧Si-Ge layer

22‧‧‧Second bonding metal layer

Claims (22)

A method for manufacturing a structure including a first substrate and a semiconductor layer, the first substrate including at least one electronic component that may be damaged by a temperature higher than 400°C, the semiconductor layer extending on the first substrate, The method is characterized in that it includes the following steps: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate, which in turn includes:-a semiconductor base substrate,-a plurality of semiconductors One of the epitaxial layers is stacked, one Si _x Ge _1-x layer, of which 0

x

1. The Si _x Ge _1-x layer is located on the surface of the stack opposite to the base substrate,-a second bonding metal layer, (c) bonding through the first bonding metal layer and the second bonding metal layer For the first substrate and the second substrate, the bonding step is performed at a temperature lower than or equal to 400°C, (d) removing a part of the second substrate to transfer the Si _x Ge _1- on the first substrate _{The x} layer, the removing includes at least selectively chemically etching a layer of the second substrate with respect to the Si _x Ge _1-x layer. The method of claim 1, wherein the second substrate includes a dielectric layer between the Si _x Ge _1-x layer and the second bonding metal layer. The method of claim 2, wherein the thickness of the dielectric layer is between 10 nm and 20 nm. Such as the method of claim 1, wherein the base substrate is a Silicon substrate. The method of claim 1 or 2, wherein the stacking from the base substrate sequentially comprises:-a silicon-germanium layer with a gradually changing composition in its thickness,-a silicon-germanium layer with a constant composition in its thickness, -One Si _y Ge _1-y layer, of which 0

y

1 and y is different from x, the Si _y Ge _1-y layer has a different composition from the silicon-germanium layer having a constant composition in its thickness, thereby forming an etching barrier layer toward the Si _x Ge _1-x layer ,-The Si _x Ge _1-x layer. The method of claim 5, wherein:-at the surface of the silicon-germanium layer having a gradually changing composition in its thickness relative to the surface of the base substrate, the composition of the layer is Si _0.8 Ge _0.2 ,-in its thickness The composition of the silicon-germanium layer with a constant composition is Si _0.8 Ge _0.2 , the thickness of the layer is between 0.5 μm and 2 μm, the composition of the etching barrier layer is selected from Si and Si _0.6 Ge _0.4 , the thickness of the layer is between Between 10nm and 50nm, the composition of the Si _x Ge _1-x layer is selected from Si _0.8 Ge _0.2 , Si and Ge, and the thickness of the layer is between 5 nm and 50 nm. The method of claim 1 or 2, wherein the first bonding metal layer and the second bonding metal layer include titanium, nickel, copper, and/or tungsten. Such as the method of claim 1 or 2, wherein step (b) includes the following sequential steps:-epitaxially grow a silicon-germanium layer with a graded composition,-epitaxially grow a silicon-germanium layer with a constant composition,-polish the silicon-germanium layer with a constant composition Constitute a silicon-germanium layer,-epitaxially grow a Si _y Ge _1-y layer on the polished silicon-germanium layer, where 0

y

1 and y is different from x, the Si _y Ge _1-y layer has a different composition from the silicon-germanium layer having a constant composition in its thickness,-the Si _x is epitaxially grown on the Si _y Ge _1-y layer Ge _1-x layer,-deposit the second bonding metal layer. The method of claim 8, wherein between the step of epitaxially growing the Si _x Ge _1-x layer and the step of depositing the second bonding metal layer, step (b) includes a step of depositing a dielectric layer. The method of claim 9, wherein after the step of depositing the dielectric layer, step (b) includes uniform densification annealing of the layer. The method of claim 9, wherein step (b) further comprises forming a binary or ternary metal alloy layer between the dielectric layer and the second bonding metal layer. The method of claim 1 or 2, wherein step (d) includes withdrawing a part of the thickness of the base substrate by polishing, followed by selectively etching the remaining part of the base substrate. The method of claim 12, wherein the etching of the base substrate is performed using a TMAH, KOH, and/or HF:HNO ₃ solution. Such as the method of claim 12, wherein removing the base substrate is followed by selectively etching the ones with constant composition and gradual composition by means of an SC1 solution and/or a HF: H ₂ O ₂ : CH ₃ COOH solution Silicon-germanium layer. A method for manufacturing a three-dimensional monolithic integrated circuit, characterized in that it comprises:-manufacturing a first substrate and a Si _x Ge _1-x layer by means of the method as claimed in any one of claims 1 to 14 A structure, the first substrate includes at least one electronic component that may be damaged by a temperature higher than 400°C, the Si _x Ge _1-x layer extends on the first substrate, and the Si _x Ge _1-x layer At least one other electronic component is fabricated on the Si _x Ge _1-x layer, wherein all the steps performed on the structure are performed at a temperature lower than or equal to 400° C. A structure including a first substrate and a semiconductor layer:-the first substrate includes at least one electronic component that may be damaged by a temperature higher than 400°C, and-the semiconductor layer extends on the first substrate, and the structure It is characterized in that the semiconductor layer is a Si _x Ge _1-x layer, where 0

x

1. The structure includes in sequence between at least one electronic component of the first substrate and the semiconductor layer:-a metal layer,-a binary or ternary metal alloy layer, and-a dielectric layer. Such as the structure of claim 16, wherein the at least one electronic component includes a transistor, a memory, a photodetector, a diode, a laser, a switch, an amplifier and/or a filter. A substrate for implementing the method according to any one of claims 1 to 14, the substrate is characterized in that it comprises in sequence: a semiconductor base substrate, a stack of one of a plurality of semiconductor epitaxial layers, a Si _x Ge _{1- x} layer, of which 0

x

1. The Si _x Ge _1-x layer is located at the surface of the stack opposite to the base substrate, a bonding metal layer. Such as the substrate of claim 18, which further includes a dielectric layer between the Si _x Ge _1-x layer and the metal layer. The substrate of claim 19, wherein the dielectric layer has a thickness between 10 nm and 20 nm. The substrate according to any one of claims 18 to 20, wherein the base substrate is a silicon substrate. The substrate of any one of claims 18 to 20, wherein the stack successively from the base substrate comprises:-a silicon-germanium layer with a gradually changing composition in its thickness,-a silicon with a constant composition in its thickness -Germanium layer,-Si _y Ge _1-y layer, of which 0

y

1 and y is different from x, the Si _y Ge _1-y layer has a different composition from the silicon-germanium layer having a constant composition in its thickness, thereby forming an etching barrier layer toward the Si _x Ge _1-x layer ,-The Si _x Ge _1-x layer.

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