TWI714281B - Display panel - Google Patents

Abstract

A display panel includes a first substrate, a pixel array, a first output line, a second output line, a first touch device, and a second touch device. The pixel array is disposed on the first substrate. The pixel array is driven in a manner of column inversion and includes scan lines, data lines, and pixels. Each of the pixels includes sub-pixels, and each of the sub-pixels is electrically connected with a corresponding one scan line and a corresponding one data line. The first output line and the second output line are substantially parallel with the data lines. One of the data lines closest to the first output line and another one of the data lines closest to the second output line have a same polarity. The first touch device and the second touch device are electrically connected with the first output line and the second output line respectively.

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel including a sensing device.

At present, in order to increase the convenience of use of products, many manufacturers install sensing devices in their products. For example, existing mobile phones often carry fingerprint recognition sensing devices. In the existing fingerprint recognition technology, the sensor device detects the light reflected by the fingerprint of the finger. The height of the fingerprint will have different intensities of reflected light, so different fingerprint appearances will be distinguished by the sensor device.

However, when the light is insufficient or the fingerprint dent is not obvious, the sensing device is easy to detect errors. As a result, the user needs to repeat the induction to successfully recognize the fingerprint. Therefore, there is an urgent need for a method that can solve the aforementioned problems.

At least one embodiment of the present invention provides a display panel that can reduce the influence of the polarity of the data line on the sensing device, thereby improving the ability of the sensing device to recognize fingerprints.

At least one embodiment of the present invention provides a display panel. The display panel includes a first substrate, a pixel array, a first output line, a second output line, a first sensing device, and a second sensing device. The pixel array is located on the first substrate. The pixel array is driven in a row-reversal manner, and includes multiple scan lines, multiple data lines, and multiple pixels. The data lines are interleaved with the scan lines. Each pixel includes a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. The first output line and the second output line are substantially parallel to the data line. One of the data lines closest to the first output line and the other one of the data lines closest to the second output line have the same polarity. The first sensing device and the second sensing device are electrically connected to the first output line and the second output line, respectively.

At least one embodiment of the present invention provides a display panel. The display panel includes a first substrate, a pixel array, a first output line, a second output line, a first sensing device, a second sensing device, a system voltage line, a first reference voltage line, and a second reference voltage line. The pixel array is located on the first substrate and includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The data lines are interleaved with the scan lines. Each pixel includes a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. The first output line and the second output line are substantially parallel to the data line. The first sensing device and the second sensing device are electrically connected to the first output line and the second output line, respectively, and the first sensing device and the second sensing device respectively include a first photosensitive element and a second photosensitive element. The system voltage line is located between the first sensing device and the second sensing device and between the first output line and the second output line, and is electrically connected to the first sensing device and the second sensing device. The first reference voltage line and the second reference voltage line are respectively located on both sides of the first photosensitive element and the second photosensitive element. The first reference voltage line and the second reference voltage line are electrically connected to the first sensing device and the second sensing device, respectively.

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. For the convenience of description, FIG. 1 omits some components of the sensing element substrate and the pixel array substrate.

Please refer to FIG. 1, the display panel 1 includes a sensing element substrate 20, a pixel array substrate 10 and a display medium layer LC. The sensing element substrate 20 faces the pixel array substrate 10. The display medium layer LC is located between the pixel array substrate 10 and the sensing element substrate 20. In this embodiment, the display panel 1 further includes a backlight module BL, which is disposed under the pixel array substrate 10. In other words, the pixel array substrate 10 is located on the backlight module BL and the sensing element substrate 20 between.

In this embodiment, the pixel array substrate 10 includes a first substrate 100 and a pixel array 110. The pixel array 110 is located on the first substrate 100.

In this embodiment, the sensing element substrate 20 includes a second substrate 200 and a plurality of sensing devices (in FIG. 1, the photosensitive element LS in the sensing device is shown). The sensing device is located on the second substrate 200. In some embodiments, the sensing element substrate 20 further includes a system voltage line, a reference voltage line, and an output line. The arrangement of the system voltage line, the reference voltage line, and the output line can be seen in the embodiment of FIG. 2A.

In this embodiment, the photosensitive element LS includes a conductive layer C1, a light sensing layer R, and an electrode layer C2. The light sensing layer R is located between the conductive layer C1 and the electrode layer C2.

In this embodiment, when the finger F approaches the sensing element substrate 20, the light LR emitted by the backlight module BL will be reflected by the finger F to the light sensing layer R.

2A is a schematic top view of a pixel array substrate according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line aa' of Fig. 2A. 3A is a schematic bottom view of a sensing device substrate according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along the section line bb' of Fig. 3A. It should be noted that, in order to make the drawings clear, Figures 2A, 2B, 3A, and 3B are not drawn to scale

It must be noted here that the embodiment of FIGS. 2A to 3B follows the element numbers and part of the content of the embodiment of FIG. 1, wherein the same or similar numbers are used to represent the same or similar elements, and the same technical content is omitted. Description. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

In this embodiment, the display panel has a light transmission area OR and a light shielding area CR. In some embodiments, the light shielding region CR overlaps the black matrix (illustration omitted in FIGS. 2B and 3B). In some embodiments, the black matrix is located in the sensing element substrate 20. In other embodiments, the black matrix is located in the pixel array substrate 10.

2A and 2B, the pixel array 110 is located on the first substrate 100, and includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixels PX. The data line DL may be zigzag, straight or other shapes.

The data line DL is interlaced with the scan line SL. Each pixel PX includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line SL and a corresponding data line DL.

In this embodiment, each sub-pixel SP includes a switching element T and a pixel electrode PE electrically connected to the switching element T. In this embodiment, the switching element T, the scan line SL and the data line DL are located in the light-shielding area CR, and at least part of the pixel electrode PE is located in the light-transmitting area OR.

The switching element T is located on the insulating layer I1, for example. In some embodiments, a light shielding layer M is sandwiched between the switching element T and the first substrate 100. The switching element T includes a gate G, a source S, a drain D, and a semiconductor channel layer CH. The semiconductor channel layer CH is located on the insulating layer I1. The gate electrode G overlaps with the semiconductor channel layer CH, and an insulating layer I2 is sandwiched between the gate electrode G and the semiconductor channel layer CH. The gate G is electrically connected to the scan line SL. In this embodiment, the gate electrode G and the scan line SL belong to the same conductive film layer, but the invention is not limited to this. The insulating layer I3 is located on the insulating layer I2 and covers the gate electrode G and the scan line SL. The source S and the drain D are located above the insulating layer I3, and the source S is electrically connected to the data line DL. In this embodiment, the source electrode S and the data line DL belong to the same conductive film layer, but the invention is not limited to this. The source S and the drain D are electrically connected to the semiconductor channel layer CH through the openings H1 and H2. The openings H1 and H2 are located in the insulating layer I3 and the insulating layer I2, for example. The insulating layer B1 is located above the source S and the drain D.

The above-mentioned switching element T is illustrated with a top gate type thin film transistor as an example, but the invention is not limited to this. According to other embodiments, the above-mentioned switching element T may also be a bottom gate type thin film transistor.

In this embodiment, the pixel array substrate 10 optionally includes a common electrode line CL.

In this embodiment, the common electrode line CL and the data line DL extend in the same direction, and the common electrode line CL and the data line DL belong to the same film layer, but the invention is not limited to this. In other embodiments, the common electrode line CL and the data line DL belong to different layers, and the common electrode line CL overlaps the data line DL in a direction perpendicular to the first substrate 100, thereby increasing the aperture ratio of the display panel.

The common electrode CE is located on the insulating layer B1 and is electrically connected to the common electrode line CL through the opening in the insulating layer B1. In some embodiments, the common electrode CE includes a touch electrode.

The insulating layer I4 is located on the common electrode CE. The pixel electrode PE is located on the insulating layer I4, the pixel electrode PE overlaps the common electrode CE, and the pixel electrode PE is separated from the common electrode CE. The pixel electrode PE is electrically connected to the drain D of the switching element T through the opening OP. In this embodiment, the opening OP passes through the insulating layer B1, the insulating layer 14 and the common electrode CE, but the invention is not limited to this. In some embodiments, the pixel array substrate 10 may use fringe field switching (FFS) technology or lateral electric field (In-Plane-Switching, IPS) technology to drive liquid crystals.

In this embodiment, the pixel array 110 is driven in a column inversion manner. For example, adjacent data lines DL have different polarities. In this embodiment, the polarity of the data line DL will be continuously reversed with the operation time.

3A and 3B, the first output line 212, the second output line 214, the first sensing device 222, the second sensing device 224, the first system voltage line 232, the first reference voltage line 242, the second The reference voltage line 244, the first control signal line 252 and the second control signal line 254 are located on the second substrate 200. In this embodiment, the first output line 212, the second output line 214, the first sensing device 222, the second sensing device 224, the first system voltage line 232, the first reference voltage line 242, the second reference voltage The line 244, the first control signal line 252, and the second control signal line 254 are located in the shading area CR.

In this embodiment, the first output line 212, the second output line 214, the first system voltage line 232, the first reference voltage line 242, and the second reference voltage line 244 overlap and are substantially parallel to those on the first substrate 100. The data line DL can thereby prevent the aperture ratio of the display panel from decreasing. In some embodiments, the first output line 212, the second output line 214, the first system voltage line 232, the first reference voltage line 242, and the second reference voltage line 244 may be zigzag, linear or other shapes. shape.

In this embodiment, the first sensing device 222 is electrically connected to the first output line 212, the first reference voltage line 242, the first control signal line 252, and the first system voltage line 232. The first sensing device 222 includes a first switching element T1, a second switching element T2, and a first photosensitive element LS1.

In this embodiment, the first switching element T1 includes a gate G1, a source S1, a drain D1, and a semiconductor channel layer CH1. In this embodiment, the light shielding layer M1 is further included between the first switching element T1 and the second substrate 200, but the invention is not limited to this.

The semiconductor channel layer CH1 is located on the insulating layer I1'. The gate electrode G1 overlaps the semiconductor channel layer CH1, and an insulating layer I2' is sandwiched between the gate electrode G1 and the semiconductor channel layer CH1. The gate G1 is electrically connected to the first control signal line 252. The insulating layer I3' is located on the insulating layer I2' and covers the gate G1, the first control signal line 252, and the second control signal line 254. The source S1 and the drain D1 are located above the insulating layer I3', and the source S1 is electrically connected to the first reference voltage line 242, where the first reference voltage line 242 is, for example, electrically connected to the voltage VSS. The source S1 and the drain D1 are electrically connected to the semiconductor channel layer CH1 through the openings H1a and H2a, respectively. The openings H1a and H2a are located in the insulating layer I3' and the insulating layer I2', for example.

The second switching element T2 includes a gate electrode G2, a source electrode S2, a drain electrode D2, and a semiconductor channel layer CH2. In this embodiment, the light shielding layer M2 is further included between the second switching element T2 and the second substrate 200, but the invention is not limited to this.

The semiconductor channel layer CH2 is located on the insulating layer I1'. The gate electrode G2 overlaps the semiconductor channel layer CH2, and an insulating layer I2' is sandwiched between the gate electrode G2 and the semiconductor channel layer CH2. The insulating layer I3' covers the gate G2. The gate G2 is electrically connected to the first switching element T1. For example, the drain D1 of the first switching element T1 is electrically connected to the gate G2 through the opening H3a, and the opening H3a is located in the insulating layer I3', for example. The source S2 and the drain D2 are located above the insulating layer I3', and the source S2 is electrically connected to the first system voltage line 232, where the first system voltage line 232 is, for example, electrically connected to the voltage VDD. The drain D2 is electrically connected to the first output line 212. The source S2 and the drain D2 are electrically connected to the semiconductor channel layer CH2 through the openings H2b and H1b. The openings H1b and H2b are located in the insulating layer I3' and the insulating layer I2', for example. This design makes the signal better.

The first photosensitive element LS1 includes a conductive layer C1, a light sensing layer R1, and an electrode layer C2. The light sensing layer R1 is located between the conductive layer C1 and the electrode layer C2.

The conductive layer C1 is located on the insulating layer B1'. The conductive layer C1 of the first photosensitive element LS1 is electrically connected to the second control signal line 254.

The electrode layer C2 is located on the insulating layer B1'. The electrode layer C2 of the first photosensitive element LS1 is electrically connected to the drain D1 of the first switching element T1 and the gate G2 of the second switching element T2. For example, the electrode layer C2 is electrically connected to the drain D1 of the first switching element T1 through the opening TH1, and the opening TH1 is located in the insulating layer B1', for example. In some embodiments, a transfer electrode layer (not shown) is selectively sandwiched between the electrode layer C2 and the drain electrode D1, and the transfer electrode layer, for example, belongs to the same film layer as the conductive layer C1.

In this embodiment, the second sensing device 224 is electrically connected to the second output line 214, the second reference voltage line 244, the first control signal line 252, and the first system voltage line 232. In this embodiment, the first sensing device 222 and the second sensing device 224 share the same first system voltage line 232. The second sensing device 224 includes a third switching element T3, a fourth switching element T4, and a second photosensitive element LS2.

In this embodiment, the third switching element T3 includes a gate electrode G3, a source electrode S3, a drain electrode D3, and a semiconductor channel layer CH3. In this embodiment, the light shielding layer M3 is further included between the third switching element T3 and the second substrate 200, but the invention is not limited to this.

The semiconductor channel layer CH3 is located on the insulating layer I1'. The gate electrode G3 overlaps with the semiconductor channel layer CH3, and an insulating layer I2' is sandwiched between the gate electrode G3 and the semiconductor channel layer CH3. The gate G3 is electrically connected to the first control signal line 252. The insulating layer I3' covers the gate G3. The source S3 and the drain D3 are located above the insulating layer I3', and the source S3 is electrically connected to the second reference voltage line 244, and the second reference voltage line 244 is, for example, electrically connected to the voltage VSS. The source S3 and the drain D3 are electrically connected to the semiconductor channel layer CH3 through openings H1c and H2c, respectively. The openings H1c and H2c are located in the insulating layer I3' and the insulating layer I2', for example.

The fourth switching element T4 includes a gate electrode G4, a source electrode S4, a drain electrode D4, and a semiconductor channel layer CH4. In this embodiment, the light shielding layer M4 is further included between the fourth switching element T4 and the second substrate 200, but the invention is not limited to this.

The semiconductor channel layer CH4 is located on the insulating layer I1'. The gate electrode G4 overlaps the semiconductor channel layer CH4, and an insulating layer I2' is sandwiched between the gate electrode G4 and the semiconductor channel layer CH4. The insulating layer I3' covers the gate G4. The gate G4 is electrically connected to the third switching element T3. For example, the drain D3 of the third switching element T3 is electrically connected to the gate G4 through the opening H3b, and the opening H3b is located in the insulating layer I3', for example. The source S4 and the drain D4 are located above the insulating layer I3', and the source S4 is electrically connected to the first system voltage line 232. The drain D4 is electrically connected to the second output line 214. The source S4 and the drain D4 are electrically connected to the semiconductor channel layer CH4 through the openings H2b and H1d, and the opening H1d is located in the insulating layer I3' and the insulating layer I2', for example. This design makes the signal better.

In this embodiment, the semiconductor channel layer CH4 and the semiconductor channel layer CH2 are connected as one body, and the source electrode S4 and the source electrode S2 are connected as one body, thereby reducing the size of the sensing device.

In some embodiments, the shapes of the gate electrode G2 and the gate electrode G4 are mirror symmetry with each other, and the shapes of the drain electrode D1 and the drain electrode D3 are mirror symmetry with each other.

In this embodiment, the gate G1, the gate G2, the gate G3, the gate G4, the first control signal line 252 and the second control signal line 254 belong to the same conductive film layer, but the invention is not limited to this. In this embodiment, source S1, drain D1, source S2, drain D2, source S3, drain D3, source S4, drain D4, first reference voltage line 242, and second reference voltage line 244, the first output line 212, the second output line 214, and the first system voltage line 232 belong to the same conductive film layer, but the invention is not limited to this.

In this embodiment, the first switching element T1, the second switching element T2, the third switching element T3, and the fourth switching element T4 are illustrated by taking the top gate type thin film transistor as an example, but the invention is not limited to this. In other embodiments, the first switching element T1, the second switching element T2, the third switching element T3, and the fourth switching element T4 may also be bottom gate type thin film transistors or other suitable thin film transistors.

The second photosensitive element LS2 includes a conductive layer C3, a light sensing layer R2, and an electrode layer C4. The light sensing layer R2 is located between the conductive layer C3 and the electrode layer C4.

The conductive layer C3 is located on the insulating layer B1'. The conductive layer C3 is electrically connected to the second control signal line 254. In this embodiment, the conductive layer C1 and the conductive layer C3 are connected as a whole, and the conductive layer C1 and the conductive layer C3 are electrically connected to the transition electrode TE through the opening O1, and the transition electrode TE is electrically connected to the transition electrode TE through the opening O2. The second control signal line 254. The opening O1 is located in the insulating layer B1', for example. The opening O2 is located in the insulating layer I3', for example. In some embodiments, the transfer electrode TE and the first system voltage line 232 belong to the same conductive film layer, but the invention is not limited to this.

The electrode layer C4 is located on the insulating layer B1'. The electrode layer C4 is electrically connected to the drain D3 of the third switching element T3 and the gate G4 of the fourth switching element T4. For example, the electrode layer C4 is electrically connected to the drain D3 of the third switching element T3 through the opening TH2, and the opening TH2 is located in the insulating layer B1', for example. In some embodiments, a transfer electrode layer (not shown) is selectively sandwiched between the electrode layer C4 and the drain electrode D3, and the transfer electrode layer, for example, belongs to the same film layer as the conductive layer C3.

In this embodiment, the materials of the conductive layer C1 and the conductive layer C3 are preferably transparent conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or Other suitable oxides or stacked layers of at least two of the above.

In this embodiment, the material of the electrode layer C2 and the electrode layer C4 is, for example, molybdenum, aluminum, titanium, copper, gold, silver or other conductive materials or a stack of two or more of the foregoing materials. In some embodiments, the electrode layer C2 and the electrode layer C4 can be used as reflective layers, thereby increasing the light that the light sensing layer R1 and the light sensing layer R2 can receive.

In this embodiment, the materials of the light sensing layer R1 and the light sensing layer R2 are, for example, silicon-rich oxide (SRO) or other suitable materials.

In this embodiment, the sensing element substrate 20 further includes a shielding layer SM.

The shielding layer SM is located between the first output line 212 and the pixel array substrate 10, between the second output line 214 and the pixel array substrate 10, between the first system voltage line 232 and the pixel array substrate 10, and the first reference Between the voltage line 242 and the pixel array substrate 10, between the second reference voltage line 244 and the pixel array substrate 10, between the first control signal line 252 and the pixel array substrate 10, and between the second control signal line 254 and the picture Between the element array substrate 10.

In some embodiments, the shielding layer SM, the conductive layer C1 and the conductive layer C3 are the same conductive film layer. The shielding layer SM and the conductive layer C1 (or the conductive layer C3) are electrically connected to different signal sources. The shielding layer SM can improve the problem that the electric field generated by the sensing element substrate 20 affects the liquid crystal molecules in the display medium layer, and can improve the display quality of the display device.

In some embodiments, the common electrode CE and the shielding layer SM are electrically connected to the same signal source. It can also be said that the same signal is applied to the common electrode CE and the shielding layer SM, thereby further improving the problem that the electric field generated by the sensing element substrate 20 affects the display quality.

In this embodiment, the sensing element substrate 20 further includes a passivation layer B2. The passivation layer B2 covers the conductive layer C1, the electrode layer C2, the shielding layer SM, and the insulating layer B1'.

In this embodiment, the first system voltage line 232 is located between the first sensing device 222 and the second sensing device 224 and between the first output line 212 and the second output line 214, and the first reference voltage line 242 And the second reference voltage line 244 are respectively located on both sides of the first photosensitive element 222 and the second photosensitive element 224, therefore, a data line DL closest to the first output line 212 and a data line DL closest to the second output line 214 The other data line DL has the same polarity (for example, the same positive electrode or the same negative electrode at the same time). For example, one data line DL overlapping the first output line 212 and another data line DL overlapping the second output line 214 have the same polarity, thereby reducing the polarity of the data line DL to the first sensing device. 222 and the second sensing device 224, and improve the ability of the first sensing device 222 and the second sensing device 224 to recognize fingerprints.

4A is a schematic top view of a pixel array substrate according to an embodiment of the invention. 4B is a schematic bottom view of a sensing device substrate according to an embodiment of the invention. 4C is a three-dimensional schematic diagram of a display panel according to an embodiment of the invention.

It must be noted here that the embodiment of FIGS. 4A to 4C follows the element numbers and part of the content of the embodiment of FIGS. 2A to 3B, wherein the same or similar numbers are used to denote the same or similar elements, and the same is omitted. Description of technical content. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

Referring to FIGS. 4A, 4B, and 4C, the display device 2 includes a sensing element substrate 20 and a pixel array substrate 10.

The pixel array substrate 10 includes a first substrate 100 and a pixel array 110. The pixel array 110 is located on the first substrate 100. The pixel array 110 includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixels PX. Each pixel PX includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line SL and a corresponding data line DL. In this embodiment, each sub-pixel SP includes a switching element T and a pixel electrode PE electrically connected to the switching element T.

In this embodiment, the sensing element substrate 20 includes a second substrate 200, a first sensing device 222, a second sensing device 224, a third sensing device 222a, a fourth sensing device 224a, and a fifth sensing device. 222b, sixth sensing device 224b, seventh sensing device 222c, eighth sensing device 224c, first system voltage line 232, second system voltage line 234, first output line 212, second output line 214, first Three output line 216, fourth output line 218, first reference voltage line 242, second reference voltage line 244, third reference voltage line 246, first control signal line 252, second control signal line 254, third control signal Line 256 and the fourth control signal line 258.

The first sensing device 222 is electrically connected to the first system voltage line 232, the first output line 212, the first control signal line 252, the second control signal line 254, and the first reference voltage line 242. The second sensing device 224 is electrically connected to the first system voltage line 232, the second output line 214, the first control signal line 252, the second control signal line 254, and the second reference voltage line 244.

The structures of the third sensing device 222a and the fourth sensing device 224a are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiment. The third sensing device 222a is electrically connected to the second system voltage line 234, the third output line 216, the first control signal line 252, the second control signal line 254, and the second reference voltage line 244. The fourth sensing device 224a is electrically connected to the second system voltage line 234, the fourth output line 218, the first control signal line 252, the second control signal line 254, and the third reference voltage line 246.

The structures of the fifth sensing device 222b and the sixth sensing device 224b are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiment. The fifth sensing device 222b is electrically connected to the first system voltage line 232, the first output line 212, the third control signal line 256, the fourth control signal line 258, and the first reference voltage line 242. The sixth sensing device 224b is electrically connected to the first system voltage line 232, the second output line 214, the third control signal line 256, the fourth control signal line 258, and the second reference voltage line 244.

The structures of the seventh sensing device 222c and the eighth sensing device 224c are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiment. The seventh sensing device 222c is electrically connected to the second system voltage line 234, the third output line 216, the third control signal line 256, the fourth control signal line 258, and the second reference voltage line 244. The eighth sensing device 224c is electrically connected to the second system voltage line 234, the fourth output line 218, the third control signal line 256, the fourth control signal line 258, and the third reference voltage line 246.

In this embodiment, the data line DL nearest to the first output line 212, the data line DL nearest to the second output line 214, the data line DL nearest to the third output line 216, and the The most adjacent data lines DL of the four output lines 218 have the same polarity. Therefore, the influence of the polarity of the data line DL on the sensing device can be reduced, thereby improving the ability of the sensing device to recognize fingerprints.

In this embodiment, the first sensing device 222, the second sensing device 224, the third sensing device 222a, the fourth sensing device 224a, the fifth sensing device 222b, the sixth sensing device 224b, and the seventh sensing device The sensing device 222c and the eighth sensing device 224c respectively include a first photosensitive element LS1, a second photosensitive element LS2, a third photosensitive element LS1a, a fourth photosensitive element LS2a, a fifth photosensitive element LS1b, a sixth photosensitive element LS2b, and a Seven photosensitive elements LS1c and eighth photosensitive element LS2c.

In this embodiment, the pitch between photosensitive elements is equal to the pitch between pixels PX. For example, the pitch P1 between the first photosensitive element LS1 and the second photosensitive element LS2 is equal to the pitch P2 between the pixels PX, and the pitch P3 between the first photosensitive element LS1 and the fifth photosensitive element LS1b is about It is equal to the pitch P4 between pixels PX. In this embodiment, the pitch P1 is equal to the pitch P3, and the pitch P2 is equal to the pitch P4.

Although in this embodiment, the first sensing device 222, the second sensing device 224, the third sensing device 222a, the fourth sensing device 224a, the fifth sensing device 222b, the sixth sensing device 224b, and the Seven sensing device 222c, eighth sensing device 224c, first system voltage line 232, second system voltage line 234, first output line 212, second output line 214, third output line 216, fourth output line 218 , The first reference voltage line 242, the second reference voltage line 244, the third reference voltage line 246, the first control signal line 252, the second control signal line 254, the third control signal line 256 and the fourth control signal line 258 are located On the second substrate 200, the present invention is not limited to this. In other embodiments, the first sensing device 222, the second sensing device 224, the third sensing device 222a, the fourth sensing device 224a, the fifth sensing device 222b, the sixth sensing device 224b, and the seventh sensing device The sensing device 222c, the eighth sensing device 224c, the first system voltage line 232, the second system voltage line 234, the first output line 212, the second output line 214, the third output line 216, the fourth output line 218, The first reference voltage line 242, the second reference voltage line 244, the third reference voltage line 246, the first control signal line 252, the second control signal line 254, the third control signal line 256, and the fourth control signal line 258 are located at the On a substrate 100.

In summary, because the first system voltage line is located between the first sensing device and the second sensing device and between the first output line and the second output line, and the first reference voltage line and the second reference voltage line Located on both sides of the first photosensitive element and the second photosensitive element, the data line closest to the first output line and the other data line closest to the second output line have the same polarity (for example, at the same time Both are positive or both are negative). For example, one data line overlapping the first output line has the same polarity as another data line overlapping the second output line. Therefore, the polarity of the data line can be reduced for the first sensing device and the second sensing device. The influence caused by the device can improve the fingerprint recognition ability of the first sensing device and the second sensing device.

1, 2: Display panel 10: Pixel array substrate 100: first substrate 110: pixel array 20: Sensing component substrate 200: second substrate 212: The first output line 214: second output line 216: Third output line 218: Fourth output line 222: The first sensing device 224: second sensing device 222a: third sensing device 224a: Fourth sensing device 222b: Fifth sensing device 224b: The sixth sensing device 222c: seventh sensing device 224c: Eighth sensing device 232: The first system voltage line 234: Second system voltage line 242: The first reference voltage line 244: second reference voltage line 246: third reference voltage line 252: The first control signal line 254: second control signal line 256: Third control signal line 258: The fourth control signal line BL: Backlight module B1, B1’, I1, I1’, I2, I2’, I3, I3’, I4: insulating layer B2: Passivation layer CE: Common electrode CL: Common electrode line C1, C3: conductive layer C2, C4: electrode layer D, D1, D2: drain CH, CH1, CH2: semiconductor channel layer CR: shading zone DL: Data line F: Finger G, G1, G2: gate LC: display medium layer LR: light LS: photosensitive element LS1: The first photosensitive element LS2: The first photosensitive element LS1a: The third photosensitive element LS2a: Fourth photosensitive element LS1b: Fifth photosensitive element LS2b: The sixth photosensitive element LS1c: seventh photosensitive element LS2c: Eighth photosensitive element OR: light transmission area PE: pixel electrode PX: pixel P1, P2, P3, P4: pitch R1, R2: light sensing layer H1, H2, H1a, H2a, H1b, H2b, H1c, H2c, H1d, H3a, H3b, O1, O2, OP, TH1, TH2: opening S, S1, S2: source SL: scan line SM: Masking layer SP: Sub-pixel TE: transfer electrode T: switching element T1: the first switching element T2: second switching element T3: third switching element T4: Fourth switching element

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. 2A is a schematic top view of a pixel array substrate according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line aa' of Fig. 2A. 3A is a schematic bottom view of a sensing device substrate according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along the section line bb' of Fig. 3A. 4A is a schematic top view of a pixel array substrate according to an embodiment of the invention. 4B is a schematic bottom view of a sensing device substrate according to an embodiment of the invention. 4C is a three-dimensional schematic diagram of a display panel according to an embodiment of the invention.

20: Sensing component substrate

200: second substrate

212: The first output line

214: second output line

216: Third output line

218: Fourth output line

222: The first sensing device

224: second sensing device

222a: third sensing device

224a: Fourth sensing device

222b: Fifth sensing device

224b: The sixth sensing device

222c: seventh sensing device

224c: Eighth sensing device

232: The first system voltage line

234: Second system voltage line

242: The first reference voltage line

244: second reference voltage line

246: third reference voltage line

252: The first control signal line

254: second control signal line

256: Third control signal line

258: The fourth control signal line

LS1: The first photosensitive element

LS2: The first photosensitive element

LS1a: The third photosensitive element

LS2a: Fourth photosensitive element

LS1b: Fifth photosensitive element

LS2b: The sixth photosensitive element

LS1c: seventh photosensitive element

LS2c: Eighth photosensitive element

Claims (10)

A display panel includes: a pixel array located on a first substrate, wherein the pixel array is driven in a row inversion manner, and includes: a plurality of scanning lines; and a plurality of data lines interlaced with the scanning lines And a plurality of pixels, wherein each pixel includes a plurality of sub-pixels, and each of the sub-pixels is electrically connected to a corresponding scan line and a corresponding data line; a first output line and a second output Line is substantially parallel to the data lines, wherein the one of the data lines that is most adjacent to the first output line and the other of the data lines that are most adjacent to the second output line have the same A first sensing device and a second sensing device, respectively, electrically connected to the first output line and the second output line; and a system voltage line located at the first sensing device and the first Between the two sensing devices and electrically connected to the first sensing device and the second sensing device. For example, the display panel described in claim 1 further includes: a first reference voltage line and a second reference voltage line, which are electrically connected to the first sensing device and the second sensing device, respectively; The third sensing device is electrically connected to the second reference voltage line, wherein the second reference voltage line is located between the second sensing device and the third sensing device; and a third output line electrically Connected to the third sensing device, where the data The one of the lines that is most adjacent to the first output line and the other of the data lines that are most adjacent to the third output line have the same polarity. In the display panel described in item 1 of the scope of patent application, the adjacent data lines have different polarities. According to the display panel described in claim 1, wherein the first output line and the second output line overlap the data lines. The display panel described in claim 1 further includes: a second substrate, wherein the first output line, the second output line, the first sensing device, and the second sensing device are located on the On the two substrates; and a display medium layer located between the first substrate and the second substrate. A display panel includes: a pixel array located on a first substrate and including; a plurality of scan lines; a plurality of data lines interlaced with the scan lines; and a plurality of pixels, wherein each pixel includes A plurality of sub-pixels, and each of the sub-pixels is electrically connected to a corresponding scan line and a corresponding data line; a first output line and a second output line are substantially parallel to the data lines; A sensing device and a second sensing device are electrically connected to the first output line and the second output line, respectively, and the first sensing device and the second sensing device each include a first photosensitive element And a second photosensitive element; a system voltage line located between the first sensing device and the second sensing device And between the first output line and the second output line, and are electrically connected to the first sensing device and the second sensing device; a first reference voltage line and a second reference voltage line are located respectively Two sides of the first photosensitive element and the second photosensitive element are electrically connected to the first sensing device and the second sensing device, respectively. The display panel according to item 6 of the scope of patent application, wherein the first output line, the second output line, the system voltage line, the first reference voltage line, and the second reference voltage line overlap and are substantially parallel to These data lines. According to the display panel of claim 6, wherein the first sensing device further includes: a first switching element, wherein the gate of the first switching element, the source of the first switching element, and the first switching element The drain of the switching element is respectively electrically connected to a control signal line, the first reference voltage line and the first photosensitive element; and a second switching element, wherein the gate of the second switching element and the second switching element The source of and the drain of the second switch element are electrically connected to the first photosensitive element, the system voltage line, and the first output line, respectively; and the second sensing device includes: a third switch element, wherein The gate of the third switching element, the source of the third switching element, and the drain of the third switching element are electrically connected to the control signal line, the second reference voltage line, and the second photosensitive element, respectively; and A fourth switching element, wherein the gate of the fourth switching element, the first The source of the four switching elements and the drain of the fourth switching element are electrically connected to the second photosensitive element, the system voltage line and the second output line, respectively. The display panel described in item 6 of the scope of patent application further includes: a second substrate, wherein the first output line, the second output line, the first sensing device, the second sensing device, and the system The voltage line, the first reference voltage line, and the second reference voltage line are located on the second substrate; and a display medium layer is located between the first substrate and the second substrate. According to the display panel described in claim 6, wherein the pitch between the first photosensitive element and the second photosensitive element is approximately equal to the pitch between the pixels.

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