TWI714071B - Pixel circuit and display device - Google Patents

Abstract

A pixel circuit includes an emitting element, a current source, and a pulse width modulation circuit. The emitting element is configured to emit according to a driving current. The current source includes a driving transistor. A control terminal of the driving transistor is coupled with a first node configured to provide a first voltage. The current source is configured to receive a first data signal from a first data line, and to setup a level of the first voltage, so that the driving transistor provides the driving current having corresponding magnitude to the emitting element. The pulse width modulation circuit is coupled with a second data line and the first node, and is configured to receive a linearly-changed voltage from the second data line. The pulse width modulation circuit compares the linearly-changed voltage with a predetermined value, and determines, according to a comparison result, a conducted period of the driving transistor and a pulse width of the driving current. The first data line is different from the second data line.

Description

Pixel circuit and display device

This disclosure relates to a pixel circuit and a display device, especially a pixel circuit including a pulse width modulation circuit.

Compared with liquid crystal displays, micro LED displays have the advantages of low power consumption, high color saturation and high response speed, making micro LED displays regarded as one of the popular technologies for next-generation displays . The brightness of the micro light emitting diode can be controlled by the driving current flowing through the micro light emitting diode, but when the driving current is different, the micro light emitting diode will produce color shift. In addition, the maximum luminous efficiency points of the micro light-emitting diodes of different colors correspond to different driving currents. Therefore, how to provide a pixel circuit and related display device that can operate the micro light emitting diode at the point of maximum luminous efficiency and avoid the color shift problem is a problem to be solved in the industry.

This disclosure provides a pixel circuit including a light-emitting unit, a current source, and a pulse width modulation circuit. The light-emitting unit is used according to Drive current to emit light. The current source is coupled to the first data line and includes a driving transistor. The control terminal of the driving transistor is coupled to the first node for providing the first voltage. The current source is used for receiving the first data signal from the first data line, and is used for setting the level of the first voltage according to the first data signal, so that the driving transistor provides a driving current with a corresponding magnitude to the light-emitting unit. The pulse width modulation circuit is coupled to the second data line and the first node, and is used for receiving a linearly varying voltage from the second data line. The pulse width modulation circuit is used to compare the level of the linearly changing voltage with the first preset value, and determine the on-time of the driving transistor and the pulse width of the driving current according to the comparison result. The first data line is different from the second data line.

The present disclosure provides a display device including a source driver, a pixel matrix, and a gate driver. The source driver is used to provide a plurality of first data signals through a plurality of first data lines, and is used to provide a plurality of linearly varying voltages through a plurality of second data lines. The pixel matrix contains multiple pixel circuits. Each pixel circuit includes a light-emitting unit, a current source, and a pulse width modulation circuit. The light emitting unit is used for emitting light according to the driving current. The current source is coupled to the corresponding first data line among the plurality of first data lines, and includes a driving transistor. The control terminal of the driving transistor is coupled to the first node for providing the first voltage. The current source is used to receive the corresponding first data signal among the plurality of first data signals from the corresponding first data line, and is used to set the level of the first voltage according to the corresponding first data signal, so that the driving transistor provides Corresponding magnitude of driving current to the light-emitting unit The pulse width modulation circuit is coupled to the corresponding second data line and the first node among the plurality of second data lines, and is used for receiving the corresponding linear voltage from the corresponding second data line. Change the voltage. The pulse width modulation circuit is used to compare the level of the corresponding linearly varying voltage with the first preset value, and determine the on-time of the driving transistor and the pulse width of the driving current according to the comparison result. The first data line is different from the second data line. The gate driver is used to sequentially enable multiple columns of the pixel matrix. Each pixel circuit of the enabled column sets the first voltage level according to the corresponding first data signal. The source driver is also used to synchronously provide a plurality of linearly varying voltages to the pixel matrix, so that each pixel circuit of the pixel matrix synchronously compares the level of the corresponding linearly varying voltage with the first preset value.

The above-mentioned pixel circuit and display device can continuously operate the light-emitting unit at the point of maximum light-emitting efficiency and avoid color shift.

100, 200, 500, 712‧‧‧Pixel circuit

101, 201, 501, 740[1]~740[n]‧‧‧First data line

103, 203, 503, 750[1]~750[n]‧‧‧Second data line

110, 210, 510‧‧‧Pulse width modulation circuit

120, 220, 520‧‧‧current source

130, 230, 530‧‧‧Lighting unit

D1, D1[1]~D1[n]‧‧‧First data signal

D2, D2[1]~D2[n]‧‧‧Second data signal

Vsw, Vsw[1]~Vsw[n]‧‧‧Linear voltage

212、512‧‧‧Pulse width modulation transistor

214、514‧‧‧First switch

216、516‧‧‧Second switch

218、518‧‧‧First capacitor

222、522‧‧‧Drive transistor

224、524‧‧‧The third switch

226、526‧‧‧Second capacitor

700‧‧‧Display device

710‧‧‧Pixel Matrix

720‧‧‧Source Driver

730‧‧‧Gate Driver

N1‧‧‧First node

N2‧‧‧Second node

V1‧‧‧First voltage

V2‧‧‧Second voltage

S1, S1[1]~S1[n]‧‧‧First control signal

S2‧‧‧Second control signal

PVDD, PVSS‧‧‧Power input

Vp1‧‧‧First operating voltage

Vp2‧‧‧Second operating voltage

Vr‧‧‧Reset voltage

Vref‧‧‧Reference voltage

FIG. 1 is a simplified functional block diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 2 is a functional block diagram of a pixel circuit according to another embodiment of the present disclosure.

Figure 3 is a simplified waveform diagram of various data signals and control signals provided to the pixel circuit of Figure 2.

FIG. 4A is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 2 in the reset phase.

FIG. 4B is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 2 in the compensation and writing stage.

FIG. 4C is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 2 in the first sub-stage of the light-emitting stage.

FIG. 4D is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 2 in the second sub-stage of the light-emitting stage.

FIG. 5 is a simplified functional block diagram of a pixel circuit according to another embodiment of the present disclosure.

Figure 6 is a simplified waveform diagram of various data signals and control signals provided to the pixel circuit of Figure 5.

FIG. 7 is a simplified functional block diagram of the display device according to an embodiment of the present disclosure.

Fig. 8 is a simplified waveform diagram of various data signals and control signals provided to the display device of Fig. 7.

Fig. 9 is a simplified waveform diagram of various data signals and control signals provided to the display device of Fig. 7.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of the pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a pulse width modulation circuit 110, a current source 120, and a light emitting unit 130. The current source 120 is used for receiving the first data signal D1 from the first data line 101 and used for providing a driving current of a corresponding magnitude to the light emitting unit 130 according to the first data signal D1. in In this embodiment, the voltage or current of the first data signal D1 input to the current source 120 corresponds to the type of the light-emitting unit 130 (for example, the color of the light generated), so that the light-emitting unit 130 is operated at the point of maximum luminous efficiency.

The pulse width modulation circuit 110 is used to receive the second data signal D2 and the linearly varying voltage Vsw from the second data line 103, and the level of the linearly varying voltage Vsw will linearly increase or decrease with time. The pulse width modulation circuit 120 determines a preset value according to the second data signal D2, and compares the level of the linearly varying voltage Vsw with the preset value. If the level of the linearly varying voltage Vsw reaches the preset value, the pulse width modulation circuit Vsw will control the current source 120 to stop outputting the driving current, thereby determining the pulse width (ie, the duration) of the driving current. The pixel circuit 100 can generate driving currents of the same magnitude multiple times so that the light-emitting unit 130 is continuously operated at the maximum luminous efficiency point, and the pulse width of the driving current generated each time is adjusted to let the user feel Various brightness.

FIG. 2 is a functional block diagram of a pixel circuit 200 according to an embodiment of the present disclosure. The pixel circuit 200 is coupled to the first data line 201 and the second data line 203, and includes a pulse width modulation circuit 210, a current source 220, a light-emitting unit 230, a first node N1, and a second node N2. The first node N1 and the second node N2 are used to provide a first voltage V1 and a second voltage V2, respectively.

The pulse width modulation circuit 210 may be the pulse width modulation circuit 110 of FIG. 1 and includes a pulse width modulation transistor 212, a first switch 214, a second switch 216, and a first capacitor 218. The first terminal of the pulse width modulation transistor 212 is used to receive the power input PVDD. Pulse width adjustment The control terminal of the variable transistor 212 is coupled to the second node N2. The first terminal of the first switch 214 is coupled to the second node N2. The second end of the first switch 214 is coupled to the second end of the pulse width modulation transistor 212. The control terminal of the first switch 214 is used to receive the first control signal S1. The first end of the second switch 216 is coupled to the second end of the pulse width modulation transistor 212. The second terminal of the second switch 216 is coupled to the first node N1. The control terminal of the second switch 216 is used to receive the second control signal S2. The first capacitor 218 is coupled between the second data line 203 and the second node N2.

The current source 220 can be the current source 120 in FIG. 1 and includes a driving transistor 222, a third switch 224, and a second capacitor 226. The first terminal of the driving transistor 222 is used to receive the power input PVDD. The second terminal of the driving transistor 222 is coupled to the first terminal of the light-emitting unit 230, and the second terminal of the light-emitting unit 230 is used to receive the power input PVSS. The control terminal of the driving transistor 222 is coupled to the first node N1. The first terminal of the third switch 224 is coupled to the first node N1. The second end of the third switch 224 is coupled to the second end of the driving transistor 222 and the first end of the light-emitting unit 230. The control terminal of the third switch 224 is used to receive the first control signal S1. The second capacitor 226 is coupled between the first data line 201 and the first node N1.

In practice, the pulse width modulation transistor 212, the first switch 214, the second switch 216, the driving transistor 222, and the third switch 224 can be implemented by any suitable type of P-type transistor, such as a P-type thin film. Transistor (Thin-film Transistor, TFT for short) or P-type metal oxide semiconductor transistor, etc.

In addition, the light-emitting unit 230 may be realized by a micro light-emitting diode or an organic light-emitting diode (OLED), and the first end and the second end of the light-emitting unit 230 may be an anode terminal and The cathode end.

FIG. 3 is a simplified waveform diagram of various data signals and control signals provided to the pixel circuit 200 of FIG. 2. In the reset phase, the first data line 201 and the second data line 203 provide a reset voltage Vr. The first control signal S1 and the second control signal S2 have enable voltages (for example, voltages with a low level). The power input PVDD and the power input PVSS provide the first operating voltage Vp1, and the first operating voltage Vp1 has a low level capable of maintaining the first switch 214 and the driving transistor 222 in the off state.

In some embodiments that require higher design flexibility, the first data line 201 and the second data line 203 can provide voltages of different levels during the reset phase, and the power input PVDD and the power input PVSS are also in the reset phase. Can provide different levels of voltage.

FIG. 4A is a schematic diagram of the equivalent circuit operation of the pixel circuit 200 of FIG. 2 in the reset phase. As shown in FIG. 4A, the first switch 214, the second switch 216, and the third switch 224 are turned on, and the pulse width modulation transistor 212 and the driving transistor 222 are turned off. Therefore, the first voltage V1 and the second voltage V2 are set close to the first operating voltage Vp1.

In the compensation and writing stage, the first data line 201 and the second data line 203 provide the first data signal D1 and the second data signal D2, respectively. The power input PVDD and the power input PVSS have a second operating voltage Vp2, and the second operating voltage Vp2 is higher than the first operating voltage Vp1. The first control signal S1 is switched from the disable voltage (for example, a voltage with a high level) to the enable voltage And maintain the enable voltage for a preset time, and then switch back to the disable voltage. The second control signal S2 is maintained at the disable voltage during the compensation and writing phase.

FIG. 4B is a schematic diagram of the equivalent circuit operation of the pixel circuit 200 of FIG. 2 in the compensation and writing stage. As shown in FIG. 4B, when the first control signal S1 has an enabling voltage, the pulse width modulation transistor 212, the driving transistor 222, the first switch 214, and the third switch 224 are turned on, and the second switch 216 and the light emitting unit 230 are turned off. Therefore, the power input PVDD will charge the first node N1 and the second node N2 until the first voltage V1 and the second voltage V2 have the following levels shown in "Equation 1" and "Equation 2": V1=Vp2- |Vth1| "Formula 1"

V2=Vp2-|Vth2| "Formula 2" where Vth1 and Vth2 represent the threshold voltages of the driving transistor 222 and the pulse width modulation transistor 212, respectively.

In addition, after the first control signal S1 is switched back to the disable voltage, the first node N1 and the second node N2 will be in a floating state. At this time, even if the voltage levels of the first data signal D1 and the second data signal D2 are changed, the voltage difference between the two ends of the second capacitor 226 and the two ends of the first capacitor 218 will still be maintained at the following "Equation 3" and "Equation 4", respectively Value shown: Data1-(Vp2-|Vth1|) "Formula 3"

Data2-(Vp2-|Vth2|) 《Formula 4》 Data1 and Data2 respectively represent the voltage levels at which the first data signal D1 and the second data signal D2 are written into the pixel circuit 200 when the first control signal S1 has an enabling voltage. It is worth noting that the magnitude and pulse width of the driving current provided by the current source 220 in the subsequent stages are determined by the values shown in "Equation 3" and "Equation 4", respectively.

When the pixel circuit 200 enters the compensation and writing phase from the reset phase, the power input PVSS first changes the voltage, and then the power input PVDD changes the voltage. In this way, it can be ensured that the light-emitting unit 230 is maintained in the off state during the compensation and writing phase to stabilize the first voltage V1 and the second voltage V2, but the present disclosure is not limited to this. In some embodiments, the power input PVDD and the power input PVSS switch voltages at the same time.

In the light-emitting phase, the first data line 201 and the second data line 203 provide a reference voltage Vref and a linearly varying voltage Vsw, respectively. The first control signal S1 and the second control signal S2 have enable voltages. The power input PVDD and the power input PVSS provide the second operating voltage Vp2 and the first operating voltage Vp1, respectively. Therefore, the second switch 216 is turned on, and the first switch 214 and the third switch 224 are turned off.

Since the first node N1 is still in a floating state, the voltage difference across the second capacitor 226 will remain at the value shown in "Equation 3". Therefore, the first voltage V1 will have the level shown in the following "Formula 5": V1=Vp2-|Vth1|+Vref-Data1 "Formula 5"

Similarly, since the second node N2 is still in a floating state, the voltage difference between the two ends of the first capacitor 218 will remain at the value shown in "Equation 4". Therefore, the second voltage V2 will have a level as shown in the following "Equation 6": V2=Vp2-|Vth2|+Vsw-Data2 "Equation 6" In this embodiment, due to the pulse width modulation transistor 212 It is realized by a P-type transistor, and the level of the linearly changing voltage Vsw will linearly decrease with time. Therefore, the level of the second voltage V2 will also linearly decrease with time.

其中Idri代表驅動電流。k代表驅動電晶體222的載子遷移率(carrier mobility)、閘極單位電容大小、以及寬長比三者的乘積。值得一提的是，驅動電晶體222在第一子階段中是工作於飽和區。 FIG. 4C is a schematic diagram of the equivalent circuit operation of the pixel circuit 200 of FIG. 2 in the first sub-stage of the light-emitting stage. In the first sub-stage, the level of the second voltage V2 is higher than the level shown in the aforementioned "Equation 2", and the level of the first voltage V1 is lower than the level shown in the aforementioned "Equation 1". Therefore, the pulse width modulation transistor 212 is turned off and the driving transistor 222 is turned on, so that the current source 220 will provide a driving current as shown in the following "Equation 7" to the light-emitting unit 230:

Among them Idri represents the drive current. k represents the product of the carrier mobility of the driving transistor 222, the unit capacitance of the gate, and the aspect ratio. It is worth mentioning that the driving transistor 222 works in the saturation region in the first sub-stage.

FIG. 4D is a schematic diagram of the equivalent circuit operation of the pixel circuit 200 of FIG. 2 in the second sub-stage of the light-emitting stage. In the second sub-phase, the level of the second voltage V2 drops below the level shown in the aforementioned "Equation 2", so that the first switch 214 is turned on. At this time, the pulse width modulation circuit 210 transmits the power input PVDD through the pulse width modulation transistor 212 and the second switch 216 It is provided to the first node N1, so that the driving transistor 222 is turned off, so that the current source 220 stops providing the driving current to the light-emitting unit 230.

It can be seen from the above that during the light-emitting phase, the pulse width modulation circuit 210 inputs the second data signal D2 into the voltage level of the pulse width modulation circuit 210 (hereinafter referred to as the first The preset value) is compared with the linearly changing voltage Vsw. When the linearly varying voltage Vsw reaches the first preset value, "Equation 6" will be equal to "Equation 2", and the pulse width modulation circuit 210 will turn on the pulse width modulation transistor 212. In other words, the pulse width modulation circuit 210 compares the second voltage V2 (hereinafter referred to as the second preset value) in the compensation and writing phase with the second voltage V2 in the light-emitting phase. When the second voltage V2 in the light-emitting phase reaches the second preset value, the pulse width modulation circuit 210 turns on the pulse width modulation transistor 212.

In the light-emitting phase, the voltage difference between the two ends of the first capacitor 218 will determine the length of the first sub-phase and thus the pulse width of the driving current, and the voltage difference between the two ends of the second capacitor 226 will determine the magnitude of the driving current. From "Formula 3" and "Formula 4", it can be seen that the voltage difference between the two ends of the first capacitor 218 and the second capacitor 226 will adapt to the variation of the threshold voltage of the pulse width modulation transistor 212 and the driving transistor 222, respectively. To change. Therefore, the pulse width and magnitude of the driving current are immune to the threshold voltage variation of the pulse width modulation transistor 212 and the driving transistor 222, so that the display device using the pixel circuit 200 can provide high-quality display images.

In some embodiments, the first switch 214, the second switch 216, and the third switch 224 in Figure 2 are implemented by N-type transistors. At this time, the waveforms of the first control signal S1 and the second control signal S2 will be reversed from that in Figure 3. The corresponding waveform in.

FIG. 5 is a simplified functional block diagram of the pixel circuit 500 according to an embodiment of the present disclosure. The pixel circuit 500 includes a pulse width modulation circuit 510, a current source 520, a light-emitting unit 530, a first node N1, and a second node N2.

The pulse width modulation circuit 510 may be the pulse width modulation circuit 110 of FIG. 1 and includes a pulse width modulation transistor 512, a first switch 514, a second switch 516, and a first capacitor 518. The first terminal of the pulse width modulation transistor 512 is used to receive the power input PVSS. The control terminal of the pulse width modulation transistor 512 is coupled to the second node N2. The first terminal of the first switch 514 is coupled to the second node N2. The second end of the first switch 514 is coupled to the second end of the pulse width modulation transistor 512. The control terminal of the first switch 514 is used to receive the first control signal S1. The first terminal of the second switch 516 is coupled to the second terminal of the pulse width modulation transistor 512. The second terminal of the second switch 516 is coupled to the first node N1. The control terminal of the second switch 516 is used to receive the second control signal S2. The first capacitor 518 is coupled between the second data line 503 and the second node N2.

The current source 520 may be the current source 120 in FIG. 1 and includes a driving transistor 522, a third switch 524, and a second capacitor 526. The first terminal of the driving transistor 522 is used to receive the power input PVSS. The second terminal of the driving transistor 522 is coupled to the second terminal (for example, the cathode terminal) of the light emitting unit 530, and the first terminal (for example, the anode terminal) of the light emitting unit 530 is used to receive the power input PVDD. The control terminal of the driving transistor 522 is coupled to the first node N1. The first terminal of the third switch 524 is coupled to the first node N1. Third switch The second end of the 524 is coupled to the second end of the driving transistor 522. The control terminal of the third switch 524 is used to receive the first control signal S1. The second capacitor 526 is coupled between the first data line 501 and the first node N1.

FIG. 6 is a simplified waveform diagram of various data signals and control signals provided to the pixel circuit 500 in FIG. 5. The operations of the pixel circuit 500 in the reset phase, the compensation and writing phase, and the light-emitting phase are similar to the operations of the pixel circuit 200 in the corresponding multiple phases. For the sake of brevity, details are not repeated here. In addition, the remaining embodiments and advantages of the aforementioned pixel circuit 200 are also applicable to the pixel circuit 500.

In practice, the pulse width modulation transistor 512, the first switch 514, the second switch 516, the driving transistor 522, and the third switch 524 in FIG. 5 can be implemented by any suitable type of N-type transistor.

In some embodiments, the first switch 514, the second switch 516, and the third switch 524 in FIG. 5 may be implemented by P-type transistors. At this time, the waveforms of the first control signal S1 and the second control signal S2 will be opposite to the corresponding waveforms in Figure 6.

FIG. 7 is a simplified functional block diagram of the display device 700 according to an embodiment of the present disclosure. The display device 700 includes a pixel matrix 710, a source driver 720, a gate driver 730, a plurality of first data lines 740[1]~740[n], and a plurality of second data lines 750[1]~750[n ], and the pixel matrix 710 includes a plurality of pixel circuits 712. The pixel circuit 712 may be the pixel circuit 100 in FIG. 1, the pixel circuit 200 in FIG. 2, or the pixel circuit 500 in FIG. 5.

The source driver 720 passes through the first data line 740[1]~740[n] provides a plurality of first data signals D1[1]~D1[n] and reset voltage Vr, and each of the first data signals D1[1]~D1[n] can It is the first data signal D1 in the previous embodiments. The source driver 720 also provides a plurality of second data signals D2[1]~D2[n], a reset voltage Vr, and a plurality of linearly varying voltages Vsw[1] through the second data lines 750[1]~750[n] ]~Vsw[n], each of the first data signals D1[1]~D1[n] may be the second data signal D2 in the foregoing multiple embodiments, and the linearly varying voltage Vsw[1]~Vsw[n Each of] may be the linearly varying voltage Vsw in the foregoing multiple embodiments.

If the pixel circuit 712 is implemented by the pixel circuit 200 in FIG. 2, the waveform diagram of the various data signals and control signals input to the display device 700 will be as shown in FIG. 8. The gate driver 730 is used to sequentially enable the columns of the pixel matrix 710 through the first control signals S1[1]~S1[n], and each of the first control signals S1[1]~S1[n] This may be the aforementioned first control signal S1. The display device 700 writes the first data signal D1[1]~D1[n] into the corresponding pixel circuit 712 in the enabled column, so that each pixel circuit 712 in the enabled column sets the first voltage The level of V1 and the second voltage V2. The source driver 720 will synchronously provide a linearly varying voltage Vsw[1]~Vsw[n] to each pixel circuit 712, so that the pulse width modulation circuit of each pixel circuit 712 will synchronize the linearly varying voltage Vsw[ 1]~Vsw[n] is compared with the corresponding first preset value.

If the pixel circuit 712 is implemented by the pixel circuit 500 in FIG. 5, the waveform diagram of various data signals and control signals input to the display device 700 will be as shown in FIG. 9. Operation of the display device 700 with the waveform in Figure 9 The process is similar to the operation process with the waveform in Figure 8. For the sake of brevity, it will not be repeated here. In addition, the indices 1 to n in the aforementioned signal numbers are used to refer to different signals provided to different columns of the pixel matrix, and are not intended to limit the number of the aforementioned signals to a specific number. For example, the first control signal S1[1] will be provided to the first column of the pixel matrix, and the first control signal S1[2] will be provided to the second column of the pixel matrix, and so on.

The display panel 700 sets the light-emitting units of the pixel circuit 712 to work at the point of maximum luminous efficiency according to the types of light-emitting units in the pixel circuit 712 (for example, the light-emitting units are classified according to the light color corresponding to the light-emitting units). In other words, for the pixel circuits 712 corresponding to the same color light, the second capacitor 226 or the second capacitor 526 will be set to have the same voltage difference during the compensation and writing phases. Therefore, in one frame of picture, the pixel circuits 712 corresponding to the same color will generate the same drive current to avoid color shift, and adjust the pulse width of the drive current to make the human eye perceive different gray levels. Brightness, and each pixel circuit 712 will work at the point of maximum luminous efficiency.

Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with ordinary knowledge in the technical field should understand that the same element may be called by different terms. The specification and the scope of the patent application do not use the difference in names as a way of distinguishing elements, but the difference in function of the elements as the basis for distinguishing. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes the first element If the component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or indirectly through other components or connection means. Connect to the second element.

In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

The above are only the preferred embodiments of the present disclosure, and all equal changes and modifications made in accordance with the requirements of the present disclosure should fall within the scope of the disclosure.

100‧‧‧Pixel circuit

101‧‧‧First data line

103‧‧‧Second data line

110‧‧‧Pulse width modulation circuit

120‧‧‧Current source

130‧‧‧Lighting Unit

D1‧‧‧First data signal

D2‧‧‧Second data signal

Vsw‧‧‧Linear voltage

Claims (10)

A pixel circuit includes: a light-emitting unit for emitting light according to a driving current; a current source, coupled to a first data line, and including a driving transistor, wherein a control terminal of the driving transistor is coupled At a first node for providing a first voltage, the current source is used for receiving a first data signal from the first data line and used for setting the level of the first voltage according to the first data signal to Enabling the driving transistor to provide the driving current with a corresponding magnitude to the light-emitting unit; and a pulse width modulation circuit, coupled to a second data line and the first node, for the second data line Receive a linearly varying voltage, wherein the pulse width modulation circuit is used to compare the level of the linearly varying voltage with a first preset value, and determine the conduction time of the driving transistor and the driving according to the comparison result The pulse width of the current; wherein the first data line is different from the second data line. The pixel circuit of claim 1, wherein the pulse width modulation circuit includes a pulse width modulation transistor, and the pulse width modulation transistor includes a first terminal, a second terminal, and a control Terminal, the control terminal of the pulse width modulation transistor is coupled to a second node for providing a second voltage, and the first terminal of the pulse width modulation transistor is used for receiving a power input, The second end of the pulse width modulation transistor is coupled to the first node, wherein the pulse width modulation circuit sets the second voltage to be the same as the The linearly changing voltage changes linearly together. When the level of the second voltage reaches a second preset value, the pulse width modulation transistor is turned on to provide the power input to the first node, thereby turning off the driving power Crystal. For example, the pixel circuit of claim 2, wherein the pulse width modulation circuit further includes: a first switch including a first terminal, a second terminal, and a control terminal, wherein the first switch of the first switch One end is coupled to the second node, the second end of the first switch is coupled to the second end of the pulse width modulation transistor, and the control end of the first switch is used to receive a first Control signal; a second switch, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the pulse width modulation transistor , The second terminal of the second switch is coupled to the first node, the control terminal of the second switch is used to receive a second control signal; and a first capacitor is coupled to the second data line and Between the second node. Such as the pixel circuit of claim 3, wherein the driving transistor further includes a first terminal and a second terminal, the first terminal of the driving transistor is used for receiving the power input, and the second terminal of the driving transistor Terminal is coupled to the light-emitting unit, and the current source further includes: a third switch, including a first terminal, a second terminal, and a control Terminal, wherein the first terminal of the third switch is coupled to the first node, the second terminal of the third switch is coupled to the second terminal of the driving transistor, and the control terminal of the third switch For receiving the first control signal; and a second capacitor, coupled between the first data line and the first node. Such as the pixel circuit of claim 2, wherein if the driving transistor and the pulse width modulation transistor are P-type transistors, the level of the linearly changing voltage decreases linearly with time, wherein if the driving transistor and The pulse width modulation transistor is an N-type transistor, and the level of the linearly varying voltage linearly increases with time. A display device includes: a source driver for providing a plurality of first data signals through a plurality of first data lines, and for providing a plurality of linearly varying voltages through a plurality of second data lines; a pixel matrix, A plurality of pixel circuits are included, and each of the pixel circuits includes: a light-emitting unit for emitting light according to a driving current; a current source coupled to a corresponding first data line among the plurality of first data lines, And includes a driving transistor, wherein a control terminal of the driving transistor is coupled to a first node for providing a first voltage, and the current source is used for receiving the plurality of first data lines from the corresponding first data line One corresponding first data signal in one data signal, and is used according to The level of the first voltage is set according to the corresponding first data signal, so that the driving transistor provides the driving current with a corresponding magnitude to the light-emitting unit; and a pulse width modulation circuit coupled to the A corresponding second data line of the plurality of second data lines and the first node are used for receiving a corresponding linearly varying voltage of the plurality of linearly varying voltages from the corresponding second data line, wherein the pulse width The modulation circuit is used to compare the level of the corresponding linearly varying voltage with a first preset value, and determine the on-time of the driving transistor and the pulse width of the driving current according to the comparison result. The data line is different from the second data line; and a gate driver for sequentially enabling the rows of the pixel matrix, wherein each pixel circuit of the enabled row is based on the corresponding first data The signal sets the level of the first voltage; wherein the source driver is also used to provide the multiple linearly varying voltages to the pixel matrix synchronously, so that each pixel circuit of the pixel matrix synchronizes the corresponding linear The level of the changing voltage is compared with the first preset value. The display device of claim 6, wherein the pulse width modulation circuit includes a pulse width modulation transistor, and the pulse width modulation transistor includes a first terminal, a second terminal, and a control terminal , The control end of the pulse width modulation transistor is coupled to a second node for providing a second voltage, the first end of the pulse width modulation transistor is used for receiving a power input, the The second end of the pulse width modulation transistor is coupled to the The first node, wherein the pulse width modulation circuit sets the second voltage to linearly change together with the corresponding linearly changing voltage, and when the level of the second voltage reaches a second preset value, the pulse The wave-width modulation transistor is turned on to provide the power input to the first node, and then turn off the driving transistor. For example, the display device of claim 7, wherein the pulse width modulation circuit further includes: a first switch including a first terminal, a second terminal, and a control terminal, wherein the first switch of the first switch Terminal is coupled to the second node, the second terminal of the first switch is coupled to the second terminal of the pulse width modulation transistor, and the control terminal of the first switch is used to receive a first control Signal; a second switch, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the pulse width modulation transistor, The second terminal of the second switch is coupled to the first node, the control terminal of the second switch is used to receive a second control signal; and a first capacitor is coupled to the corresponding second data line And the second node. The display device of claim 8, wherein the driving transistor further includes a first terminal and a second terminal, the first terminal of the driving transistor is used for receiving the power input, and the second terminal of the driving transistor Coupled to the The light-emitting unit, and the current source further includes: a third switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the first node, the The second terminal of the third switch is coupled to the second terminal of the driving transistor, the control terminal of the third switch is used to receive the first control signal; and a second capacitor is coupled to the corresponding Between the first data line and the first node. Such as the display device of claim 7, wherein if the driving transistor and the pulse width modulation transistor are P-type transistors, the level of the corresponding linearly varying voltage decreases linearly with time, wherein if the driving transistor And the pulse width modulation transistor is an N-type transistor, and the level of the corresponding linearly changing voltage linearly increases with time.

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