TWI714056B - Timing controller and operating method thereof - Google Patents

Abstract

A timing controller and operating method are provided. The operating method of the timing controller includes detecting a frame rate of a pixel data stream. A gain value is determined according to the frame rate. A current pixel data is compensated according to the gain value associated with the frame rate to generate compensated pixel data.

Description

Timing controller and its operation method

The present invention relates to a display device, and more particularly to a timing controller and an operation method thereof.

With the advancement of electronic technology, consumer electronic products have become an indispensable tool in people's lives. In order to provide a good human-machine interface, it has also become a trend to configure high-quality display devices on consumer electronic products. Therefore, how to maintain the charging rate of each sub-pixel in a stable state when the frame rate of the pixel data stream received by the timing controller changes, thereby maintaining the quality of the display screen, will be in the art The subject of relevant technical personnel.

It should be noted that the content of the "prior art" paragraph is used to help understand the present invention. Part of the content (or all of the content) disclosed in the "prior art" paragraph may not be the conventional technology known to those with ordinary knowledge in the technical field. The content disclosed in the "prior art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The present invention provides a timing controller and an operation method thereof, which enable the processing circuit of the timing controller to determine a gain value according to the frame rate of the pixel data stream, and to compare the current pixel data according to the gain value. Compensation is performed to maintain the charging rate of each pixel.

The operating method of the present invention includes: detecting the frame rate of the pixel data stream; determining the gain value according to the frame rate; compensating the current pixel data according to the gain value related to the frame rate to generate compensated pixel data.

The timing controller of the present invention includes a detection circuit and a processing circuit. The detection circuit is used to detect the frame rate of the pixel data stream. The processing circuit is coupled to the detection circuit to obtain the frame rate, wherein the processing circuit determines the gain value according to the frame rate, and the processing circuit compensates the current pixel data according to the gain value related to the frame rate to generate compensated pixel data.

Based on the above, the timing controller of the embodiments of the present invention can detect the frame rate of the pixel data stream. According to the frame rate of the pixel data stream, the processing circuit can determine the gain value used to compensate the current pixel data. In this way, when the frame rate of the display panel is updated (or dynamically switched), the processing circuit can instantly and adaptively compensate the current pixel data to avoid the problem of insufficient charging of the sub-pixels in the display panel.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The term "coupling (or connection)" used in the full description of the case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. The terms "first" and "second" mentioned in the full text of the description of this case (including the scope of the patent application) are used to name the element (element), or to distinguish different embodiments or ranges, and are not used to limit the number of elements The upper or lower limit is not used to limit the order of components. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same reference numerals or using the same terms in different embodiments may refer to related descriptions.

FIG. 1 is a circuit block diagram of a timing controller 100 according to an embodiment of the invention. Please refer to FIG. 1, in this embodiment, the timing controller 100 includes a detection circuit 110 and a processing circuit 120. The detection circuit 110 can detect the frame rate of the pixel data stream PDS provided by an external device (for example, a display card), and the detection circuit 110 can generate according to the frame rate of the pixel data stream PDS Frame rate data FRD. In other words, the frame rate data FRD can carry information about the frame rate of the pixel data stream PDS. This embodiment does not limit the detection method of the detection circuit 110. The detection method of the detection circuit 110 can be determined according to design requirements. For example, under some design requirements, the detection method of the detection circuit 110 can be a conventional frame rate detection method or other detection methods.

The processing circuit 120 is coupled to the detection circuit 110 to receive frame rate data FRD and current pixel data CPD. Wherein, the current pixel data CPD may be the original pixel data of the pixel data stream PDS. Specifically, the processing circuit 120 can obtain the frame rate of the pixel data stream PDS according to the received frame rate data FRD, and determine the corresponding gain value according to the frame rate, so that the processing circuit 120 can be related to The gain value of the frame rate is used to compensate the current pixel data CPD. In other words, the processing circuit 120 can provide the compensated pixel data CSPD to the back-end source driver 200 according to the gain value and the current pixel data CPD.

This embodiment does not limit the manner in which the processing circuit 120 determines the gain value. The method of determining the gain value can be determined according to design requirements. For example, under some design requirements (in some embodiments), the processing circuit 120 may incorporate the frame rate into an equation (function) to calculate the gain value. Under other design requirements (in other embodiments), the processing circuit 120 may query the gain comparison table according to the frame rate to directly obtain the gain value.

On the other hand, the source driver 200 is coupled to the processing circuit 120 to receive the compensated pixel data CSPD. The source driver 200 can correspondingly generate the source driving signals S1 ˜SN according to the compensated pixel data CSPD. In addition, the source driver 200 can transmit the source driving signals S1 to SN to the corresponding data lines (or called source lines) in the display panel 300 to respectively drive the corresponding multiple sub-pixels. Wherein, the display panel 300 of this embodiment may be a single-gate structure, a dual-gate structure or a triple-gate structure, but the invention is not limited to this. In addition, the aforementioned N is a positive integer.

FIG. 2 is a circuit block diagram illustrating the processing circuit 120 shown in FIG. 1 according to an embodiment of the present invention. In this embodiment, the processing circuit 120 may include a gain comparison table 130 and a calculation circuit 140. Regarding the operation details of the processing circuit 120, please refer to FIG. 1 and FIG. 2. Specifically, the processing circuit 120 can be based on the frame rate of the frame rate data FRD or the frame rate of the frame rate data FRD and the gray level of the current pixel data CPD. The gain comparison table 130 is queried for the value to obtain a plurality of candidate gain values CGV1 to CGVN from the gain comparison table 130. Then, the processing circuit 120 may receive the candidate gain values CGV1 to CGVN through the calculation circuit 140, and calculate the candidate gain values CGV1 to CGVN (for example, interpolation calculation, but the invention is not limited to this) to obtain The gain value corresponding to the frame rate. In this way, the processing circuit 120 can compensate the current pixel data CPD according to the calculated gain value, and provide the compensated pixel data CSPD to the back-end source driver 200.

For example, in some embodiments of the present invention, the gain comparison table 130 in FIG. 2 may be implemented by the gain comparison table 130_1 in FIG. 3A. Please refer to FIG. 1, FIG. 2 and FIG. 3A at the same time. FIG. 3A is a schematic diagram illustrating the gain comparison table shown in FIG. 2 according to an embodiment of the present invention. Among them, in the gain comparison table 130_1, the values in the first row (column) C1 are multiple frame rates FR1 to FR9, and the values in the second row C2 are multiple candidates corresponding to these frame rates FR1 to FR9. Gain value CGV1～CGV9. In other words, the one-dimensional gain comparison table 130_1 shown in FIG. 3A may have relevant information about the correspondence between multiple frame rates and multiple candidate gain values.

In detail, in this embodiment, it is assumed that the detection circuit 110 detects that the frame rate of the pixel data stream PDS is 100 Hertz (Hz). At the same time, the processing circuit 120 can query the gain according to the frame rate data FRD. Check the table 130_1, and determine that the frame rate (that is, 100 Hz) detected by the current detection circuit 110 is between FR4 (that is, 96 Hz) and FR5 (that is, 112 Hz) in the gain comparison table 130_1.

In this case, the processing circuit 120 can obtain the candidate gain values CGV4 (that is, 1.1) and CGV5 (that is, 1.15) corresponding to the frame rates FR4 and FR5, respectively, according to the determination result. Then, the calculation circuit 140 may perform interpolation calculation on the candidate gain values 1.1 and 1.15 to obtain the gain value GM1 corresponding to the frame rate of the pixel data stream PDS operating at 100 Hz. Moreover, the processing circuit 120 can compensate the current pixel data CPD based on the gain value GM1 related to the frame rate of the pixel data stream PDS.

Furthermore, the processing circuit 120 may use the calculation circuit 140 to multiply the current pixel data CPD by the gain value GM1 to obtain the compensated pixel data CSPD. In addition, the source driver 200 can provide source driving signals S1 ˜SN according to the compensated pixel data CSPD, so that the source driving signals S1 ˜SN can respectively charge a plurality of sub-pixels in the display panel 300.

On the other hand, in some other embodiments of the present invention, the gain comparison table 130 in FIG. 2 may be implemented by the gain comparison table 130_2 in FIG. 3B. Please refer to FIG. 1, FIG. 2 and FIG. 3B at the same time. FIG. 3B is a schematic diagram illustrating the gain comparison table shown in FIG. 2 according to another embodiment of the present invention. Specifically, in FIG. 3B, the gain comparison table 130_2 may include multiple frame rates detected by the detection circuit 110 under different conditions and multiple gray levels of the current pixel data CPD received by the processing circuit 120. value. In other words, the two-dimensional gain comparison table 130_2 shown in FIG. 3B may have related information about a plurality of candidate gain values respectively corresponding to the plurality of frame rates and the plurality of grayscale values of the current pixel data CPD.

In detail, in this embodiment, it is also assumed that the frame rate of the pixel data stream PDS detected by the detection circuit 110 is 100 Hz, and at this time the grayscale value of the current pixel data CPD received by the processing circuit 120 Is 130. At the same time, the processing circuit 120 can query the gain comparison table 130_2 according to the received frame rate data FRD and the current pixel data CPD, and determine whether the frame rate (that is, 100 Hz) detected by the current detection circuit 110 is an intermediate The frame rate in the gain comparison table 130_2 is between FR10 (that is, 96 Hz) and FR11 (that is, 112 Hz), and it is determined that the gray scale value of the current pixel data CPD (that is, 130) is between the gain comparison table 130_2 The grayscale values in G1 (that is, 128) and G2 (that is, 144) are between.

In this case, the processing circuit 120 can make the gain comparison table 130_2 obtain the candidate gain values CGV110 (that is 1.12) and CGV111 (that is, 1.17) corresponding to the frame rates FR10 and FR11 and the gray scale values G1 and G2 respectively according to the judgment result. ), CGV210 (that is 1.12) and CGV211 (that is 1.17). Then, the calculation circuit 140 may perform interpolation calculation on the candidate gain values 1.12, 1.17, 1.12, and 1.17 to obtain the gain value GM2 corresponding to the frame rate of the pixel data stream PDS operating at 100 Hz. In addition, the processing circuit 120 can compensate the current pixel data CPD based on the gain value GM2 related to the frame rate of the pixel data stream PDS.

Furthermore, the processing circuit 120 can also use the calculation circuit 140 to multiply the current pixel data CPD by the gain value GM2 to obtain the compensated pixel data CSPD. In addition, the source driver 200 may also provide source driving signals S1 to SN according to the compensated pixel data CSPD, so that the source driving signals S1 to SN can respectively charge a plurality of sub-pixels in the display panel 300 .

According to the above-mentioned embodiments and descriptions of the implementations in FIGS. 3A and 3B, it can be known that in the timing controller 100 of the present invention, the processing circuit 120 can stream the frame rate of the PDS according to the pixel data or the frame rate and the current The grayscale value of the pixel data CPD is determined from the one-dimensional gain comparison table 130_1 or the two-dimensional gain comparison table 130_2 configured in the processing circuit 120 to compensate the current pixel data CPD gain value, so that the source driver 200 The sub-pixels in the display panel 300 can be charged according to the compensated pixel data CSPD. In this way, when the picture to be displayed on the display panel 300 is updated (or dynamically switched) too fast (or too frequently), which causes the frame rate of the pixel data stream PDS to change, the present invention can use The aforementioned compensation mechanism avoids the problem of insufficient charging of the sub-pixels in the display panel 300, and can improve the picture abnormality caused by the insufficient charging of the factor pixels.

FIG. 4 is a circuit block diagram of a timing controller 400 according to another embodiment of the invention. In the embodiment shown in FIG. 4, the timing controller 400 includes a detection circuit 410, a processing circuit 420, and an overdrive compensation circuit 430. The timing controller 400, the detection circuit 410, and the processing circuit 420 shown in FIG. 4 may refer to the timing controller 100, the detection circuit 110, and the processing circuit 120 mentioned in FIG. 1, FIG. 2, FIG. 3A, and/or FIG. 3B. The related descriptions are analogized, so I won't repeat them.

Please refer to FIG. 4, the driving compensation circuit 430 may be coupled to the processing circuit 420. The present embodiment does not limit the compensation method of the overdrive compensation circuit 430. The compensation method of the overdrive compensation circuit 430 can be determined according to design requirements. For example, under some design requirements, the overdrive compensation circuit 430 may be a compensation circuit known to those skilled in the art to perform overdrive compensation on pixel data, or other compensation circuits.

It should be noted that the parasitic capacitance and parasitic resistance of the traces in the display panel are often affected by the RC delay phenomenon, resulting in the source driver being unable to provide sufficient driving voltage to the current display panel based on the pixel data. The sub-pixels are charged. Therefore, the overdrive compensation circuit 430 of this embodiment can be used to perform overdrive compensation on the original pixel data OPD in the pixel data stream PDS to obtain the current pixel data CPD', so that the processing circuit 420 can respond to the process Drive the compensated current pixel data CPD' to provide the compensated pixel data CSPD' to the source driver of the back end.

Specifically, in this embodiment, the detection circuit 410 can detect the frame rate of the pixel data stream PDS, and provide frame rate data FRD to the processing circuit 420 based on the frame rate. On the other hand, the overdrive compensation circuit 430 can receive the original pixel data OPD in the pixel data stream PDS, and the overdrive compensation circuit 430 can be located in a frame based on the spatial position (also That is, on the same data line (or source line) and the pixel data of the previous sub-pixel corresponding to the current sub-pixel, overdrive compensation is performed on the original pixel data OPD to improve the original The voltage level of the pixel data OPD is used to obtain the current pixel data CPD' after driving compensation. In addition, the overdrive compensation circuit 430 can provide the current pixel data CPD' to the processing circuit 420.

Then, the processing circuit 420 can query the gain value from the gain comparison table in the processing circuit 420 according to the current pixel data CPD' and the frame rate data FRD, so as to compare the current pixel data CPD after driving compensation according to the gain value. 'Compensate and provide the compensated pixel data CSPD' to the source driver at the back end. In this way, the source driver can charge the sub-pixels in the display panel according to the compensated pixel data CSPD', and can effectively alleviate the problem of insufficient charging of the sub-pixels. For the relevant implementation details of the processing circuit 420 to query the gain value from the gain comparison table in the processing circuit 420 according to the current pixel data CPD' and the frame rate data FRD, please refer to the related description of FIG. 3A and/or FIG. 3B , I won’t repeat it here.

FIG. 5 is a circuit block diagram of a timing controller 500 according to still another embodiment of the invention. The timing controller 500 includes a detection circuit 510, a processing circuit 520, and an overdrive compensation circuit 530. The timing controller 500, the detection circuit 510, and the processing circuit 520 shown in FIG. 5 may refer to the timing controller 100, the detection circuit 110, and the processing circuit 120 mentioned in FIG. 1, FIG. 2, FIG. 3A, and/or FIG. 3B. The relevant description of the overdrive compensation circuit 530 shown in FIG. 5 can be analogized with reference to the relevant description of the overdrive compensation circuit 530 shown in FIG. 4, so it will not be repeated. In the embodiment shown in FIG. 5, the driving compensation circuit 530 can obtain the original pixel data OPD in the pixel data stream PDS through the detection circuit 510. Among them, the driving compensation circuit 530 is coupled between the detection circuit 510 and the processing circuit 520.

In detail, in this embodiment, the detection circuit 510 can detect the frame rate of the pixel data stream PDS, and transmit the frame rate data FRD to the processing circuit 520 based on the frame rate. In addition, the timing controller 500 can use the detection circuit 510 to transmit the original pixel data OPD in the pixel data stream PDS to the driving compensation circuit 530.

On the other hand, the drive compensation circuit 530 can perform overdrive compensation on the received original pixel data OPD, and provide the current pixel data CPD' after drive compensation to the processing circuit 520. Then, the processing circuit 520 can query the gain value from the gain comparison table in the processing circuit 520 according to the current pixel data CPD' and the frame rate data FRD, so as to compare the current pixel data CPD after driving compensation according to the gain value. 'Compensate and provide the compensated pixel data CSPD' to the source driver at the back end. In this way, the timing controller 500 of the present embodiment can also perform overdrive compensation on the original pixel data OPD to effectively improve the problem of insufficient charging of the sub-pixels in the display panel.

Among them, the above-mentioned overdrive compensation operation and the processing circuit 520 according to the current pixel data CPD' and the frame rate data FRD to query the gain value from the gain comparison table in the processing circuit 520 related implementation details are described in detail in the figure 3A, FIG. 3B, and the embodiments and implementation manners of FIG. 4, which will not be repeated here.

Fig. 6 is a flowchart of an operating method of a timing controller according to an embodiment of the present invention. 1 and FIG. 6 at the same time, in step S610, the detection circuit 110 can detect the frame rate of the pixel data stream PDS. In step S620, the processing circuit 120 may determine the gain value corresponding to the frame rate according to the frame rate. In step S630, the processing circuit 120 may compensate the current pixel data CPD according to the gain value related to the frame rate to generate the compensated pixel data CSPD. The implementation details of each step are described in detail in the foregoing embodiments and implementation manners, and will not be repeated here.

In summary, the timing controllers of the embodiments of the present invention can use the processing circuit to follow the frame rate of the pixel data stream or the frame rate and the grayscale value of the current pixel data to determine from one-dimensional or two-dimensional The gain value used to compensate the current pixel data is determined in the gain comparison table of the dimension, so that the source driver can charge the sub-pixels in the display panel according to the compensated pixel data. In this way, when the frame rate of the pixel data stream changes due to the update (or dynamic switching) rate of the picture to be displayed on the display panel is too fast (or too frequent), the present invention can use the above The compensation mechanism can avoid the problem of insufficient charging of the sub-pixels in the display panel, and can improve the picture abnormalities caused by insufficient charging of the factor pixels.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 400, 500: timing controller 110, 410, 510: detection circuit 120, 420, 520: processing circuit 130, 130_1, 130_2: Gain comparison table 200: source driver 300: display panel 430, 530: Overdrive compensation circuit CPD, CPD’: current pixel data CSPD, CSPD’: compensated pixel data CGV1～CGVN: Candidate gain value FRD: Frame rate data OPD: Original pixel data PDS: Pixel data streaming FR1～FR9: Frame rate C1, C2: OK S1～SN: Source drive signal S610～S630: steps

FIG. 1 is a schematic diagram of a circuit block (Circuit Block) of a timing controller according to an embodiment of the present invention. FIG. 2 is a circuit block diagram illustrating the processing circuit shown in FIG. 1 according to an embodiment of the present invention. FIG. 3A is a schematic diagram illustrating the gain comparison table shown in FIG. 2 according to an embodiment of the present invention. FIG. 3B is a schematic diagram illustrating the gain comparison table shown in FIG. 2 according to another embodiment of the present invention. FIG. 4 is a circuit block diagram of a timing controller according to another embodiment of the invention. FIG. 5 is a circuit block diagram of a timing controller according to still another embodiment of the invention. Fig. 6 is a flowchart of an operating method of a timing controller according to an embodiment of the present invention.

100: timing controller 110: Detection circuit 120: Processing circuit 200: source driver 300: display panel CPD: current pixel data CSPD: compensated pixel data FRD: Frame rate data PDS: Pixel data streaming S1～SN: Source drive signal

Claims (12)

An operating method of a timing controller includes: detecting a frame rate of a pixel data stream; determining a gain value according to the frame rate; and compensating a current pixel data according to the gain value related to the frame rate, To generate a compensated pixel data, wherein the step of determining the gain value includes: querying a gain comparison table according to the current pixel data and the frame rate to obtain a plurality of candidate gain values; and according to the candidate gain values Calculate the gain value. According to the operation method described in item 1 of the scope of patent application, the step of determining the gain value includes: querying a gain comparison table according to the current pixel data and the frame rate to obtain the gain value. As for the operation method described in item 1 of the patent application, the step of calculating the gain value includes: performing an interpolation calculation on the candidate gain values to obtain the gain value. In the operation method described in item 1 of the scope of patent application, the current pixel data is an original pixel data in the pixel data stream. For the operation method described in item 1 of the scope of patent application, the step of compensating the current pixel data includes: multiplying the current pixel data by the gain value to obtain the compensated pixel data material. An operating method of a timing controller includes: detecting a frame rate of a pixel data stream; determining a gain value according to the frame rate; compensating a current pixel data according to the gain value related to the frame rate to Generate a compensated pixel data; and perform an overdrive compensation on an original pixel data in the pixel data stream to obtain the current pixel data. A timing controller includes: a detection circuit for detecting a frame rate of a pixel data stream; and a processing circuit coupled to the detection circuit to obtain the frame rate, wherein the processing circuit is in accordance with The frame rate determines a gain value, the processing circuit compensates a current pixel data according to the gain value related to the frame rate to generate a compensated pixel data, and the processing circuit includes: a gain comparison table, wherein the The processing circuit queries the gain comparison table according to the current pixel data and the frame rate to obtain a plurality of candidate gain values; and a calculation circuit is used to calculate the gain value according to the candidate gain values. The timing controller according to item 7 of the scope of patent application, wherein the processing circuit comprises: a gain comparison table; wherein the processing circuit queries the gain comparison table according to the current pixel data and the frame rate to obtain the gain value. For the timing controller described in item 7 of the scope of patent application, the calculation circuit performs an interpolation calculation on the candidate gain values to obtain the gain value. The timing controller described in item 7 of the scope of patent application, wherein the current pixel data is an original pixel data in the pixel data stream. The timing controller according to item 7 of the scope of patent application, wherein the processing circuit multiplies the current pixel data by the gain value to obtain the compensated pixel data. A timing controller includes: a detection circuit for detecting a frame rate of a pixel data stream; a processing circuit coupled to the detection circuit to obtain the frame rate, wherein the processing circuit is in accordance with the The frame rate determines a gain value, and the processing circuit compensates a current pixel data according to the gain value related to the frame rate to generate a compensated pixel data; and an overdrive compensation circuit coupled to the processing circuit, The overdrive compensation circuit performs an overdrive compensation on an original pixel data in the pixel data stream to obtain the current pixel data, and provides the current pixel data to the processing circuit.

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