TWI712022B - Display apparatus - Google Patents

Abstract

A display apparatus is provided. The display apparatus includes a display array and a driving array. The display array has a plurality of pixel blocks, each of which includes a receiving antenna to receive a corresponding driving electromagnetic signal. The driving array has a plurality of driving circuits, and each driving circuit includes a transmitting antenna and a plurality of first impedance circuits. The transmitting antenna is coupled to the receiving antenna. The first impedance circuit is connected in parallel between the transmission antenna and a first AC signal, and each has a different impedance value. At least one of the first impedance circuits is enabled to transmit the first AC signal to the transmitting antenna after amplitude of the first AC signal adjusted according to the impedance value of the enabled impedance circuit.

Description

Display device

The present invention relates to a display device, and particularly relates to a transparent wireless signal.

Nowadays, a wireless-driven display is developed, which disassembles the high-resolution passive matrix self-luminous display module into many low-resolution passive matrix self-luminous modules, and each low-resolution passive matrix self-luminous module is called A block. All sub-pixels in the same block receive signals through the same data coil, and both ends of the coil are connected to the passive matrix through switches in the X or Y direction.

Due to the limitation of time, the number of gray levels that can be cut out within one pixel scan time (line time) is insufficient, resulting in a decrease in contrast. In other words, since the update frequency of each screen must be at least 60 Hertz (Hz), all sub-pixels in each block need to be scanned once within a limited time, so the switching time of one Y direction is about 1/(nX *mY*T) seconds, where n is the number of switches in the X direction, m is the number of switches in the Y direction, and T is the scan time of each pixel. In addition, the higher the update frequency and the higher the resolution controlled by each block, the number of pulses received by the data coil in each scan time is limited, resulting in insufficient gray levels.

The present invention provides a display device that can increase the order of driving electromagnetic signals between a pixel block and a driving circuit.

The display device of the present invention includes a display array and a driving array. The display array has a plurality of pixel blocks, and each includes a receiving antenna to receive the corresponding driving electromagnetic signal. The driving array has a plurality of driving circuits, and each driving circuit includes a transmission antenna and a plurality of first impedance circuits. The transmitting antenna is coupled with the receiving antenna. The first impedance circuit is connected in parallel between the transmission antenna and the first AC signal, and each has different impedance values. At least one of the first impedance circuits is enabled to adjust the amplitude of the first AC signal according to the impedance value it has and then transmit it to the transmitting antenna.

Based on the foregoing, in the display device of the embodiment of the present invention, through the adjustment of the amplitude, the driving electromagnetic signal generated by the transmitting antenna can have more levels, that is, the contrast of the pixels in each pixel block can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Display device

20: display array

21: pixel block

21a: pixel

100: drive array

110, 110a: drive circuit

111, 111a: drive signal generating circuit

113, 113a: control signal generation circuit

ARX: receiving antenna

ATX: transmit antenna

B1: The first bit part

B2: The second part

CMR11~CMR13, CMR21~CMR23: impedance matching circuit

CPX: pixel capacitance

CTR11~CTR13: the first impedance circuit

CTR21~CTR23: Second impedance circuit

DDX: display data

Even_CK: second clock signal

M11, M21, M31, M41, M51, M61: the first switch

M12, M22, M32, M42, M52, M62: second switch

Odd_CK: The first clock signal

OLD: Light-emitting element

SAC1, XSAC1: the first AC signal

SAC2, XSAC2: second AC signal

SC11~SC13: the first control signal

SC21~SC23: the second control signal

SDM: Drive electromagnetic signal

T1, T3: Transistor

T2, T4: clock switch

TX1~TX4, TX: the first axis switch

TY1~TY4, TY: second axial switch

VCOM: common voltage

X1~X4, Xm: first axis control signal

Y1~Y4, Yn: second axis control signal

FIG. 1 is a system diagram of a display device according to an embodiment of the invention.

2 is a schematic circuit diagram of a pixel block and a driving circuit according to an embodiment of the invention.

3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the invention.

4 is a schematic circuit diagram of a pixel block and a driving circuit according to another embodiment of the invention.

FIG. 5 is a schematic circuit diagram of a pixel block according to an embodiment of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the “first element”, “component”, “region”, “layer” or “portion” discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings herein.

The terminology used here is only for the purpose of describing specific embodiments and is not limiting. As used herein, unless the content clearly indicates The number forms "a", "an" and "the" are intended to include plural forms, including "at least one." "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the terms "including" and/or "including" designate the presence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more The existence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a system diagram of a display device according to an embodiment of the invention. Please refer to FIG. 1, in this embodiment, the display device 10 includes a display array 20 and a driving array 100. The display array 20 includes a plurality of pixel blocks 21 arranged in an array, and the driving array 100 includes a plurality of driving circuits 110 arranged in an array.

2 is a schematic circuit diagram of a pixel block and a driving circuit according to an embodiment of the invention. 1 and 2, in this embodiment, each pixel block 21 includes a receiving antenna ARX, a plurality of light-emitting elements OLD (such as organic light-emitting diodes, micro light-emitting diodes, sub-millimeter light-emitting diodes ), multiple first axial switches (such as TX1~TX4) and multiple second axial switches (such as TY1~TY4). The receiving antenna ARX is used to receive the corresponding driving electromagnetic signal SDM. The first ends of these first axial switches (such as TX1~TX4) are coupled to the first end of the receiving antenna ARX, and the second ends of each first axial switch (such as TX1~TX4) are coupled to the corresponding light emitting element The cathode end of OLD, and these first axial switches (such as TX1~TX4) are controlled by the corresponding first axial control signal (such as X1~X4) to be turned on or off. The first ends of these second axial switches (such as TY1~TY4) are commonly coupled to the second end of the receiving antenna ARX, and the second ends of each second axial switch (such as TY1~TY4) are coupled to the corresponding light emitting yuan The anode end of the element OLD, and these second axial switches (such as TY1~TY4) are controlled by the corresponding second axial control signal (such as Y1~Y4) to be turned on or off.

Each driving circuit 110 includes a transmission antenna ATX, a plurality of first impedance circuits CTR11 to CTR13, a driving signal generating circuit 111 and a control signal generating circuit 113. The driving signal generating circuit 111 receives the display data DDX to generate the first AC signal SAC1. The control signal generating circuit 113 receives the display data DDX to generate the first control signals SC11 to SC13.

The transmitting antenna ATX is used to couple with the receiving antenna ARX, that is, to generate the driving electromagnetic signal SDM. The first impedance circuits CTR11~CTR13 are connected in parallel between the first terminal of the transmitting antenna ATX and the first AC signal SAC1, and each have different impedance values, wherein the first terminal of the transmitting antenna ATX is coupled to a reference voltage (such as a ground voltage) .

The first impedance circuits CTR11 to CTR13 individually receive the first control signals SC11 to SC13 to be enabled in response to the corresponding first control signals SC11 to SC13. In other words, at least one of the first impedance circuits CTR11 to CTR13 is enabled to adjust the amplitude of the first AC signal SAC1 according to the impedance value it has and then transmit it to the transmitting antenna ATX. In this way, through the adjustment of the amplitude, the driving electromagnetic signal generated by the transmitting antenna can have more levels, that is, the contrast of the pixels in each pixel block can be improved.

In the embodiment of the present invention, only one of the first impedance circuits CTR11 to CTR13 can be used to adjust the amplitude of the first AC signal SAC1 according to the impedance value it has and then transmit it to the transmitting antenna ATX. Alternatively, one, two,..., or all of the first impedance circuits CTR11~CTR13 can be enabled, The amplitude of the first AC signal SAC1 is adjusted according to the impedance value it has and then transmitted to the transmitting antenna ATX.

In the embodiment of the present invention, the driving signal generating circuit 111 may refer to the first bit portion B1 of the display data DDX to generate the first AC signal SAC1, and the control signal generating circuit 113 may refer to the second bit portion of the display data DDX B2 generates first control signals SC11~SC13. The first bit portion B1 is, for example, the high bit portion, and the second bit portion B2 is, for example, the low bit portion. In the embodiment of the present invention, the first bit part B1 and the second bit part B2 may not overlap, or the first bit part B1 and the second bit part B2 partly overlap, which can be based on the circuit It depends on the design.

The first impedance circuit CTR11~CTR13 respectively include an impedance matching circuit (such as CMR11~CMR13), a first switch (such as M11, M21, M31), and a second switch (such as M12, M22, M32), of which the impedance matching circuit CMR11~ The CMR13 has a corresponding impedance value (that is, has a different impedance value). Taking the first impedance circuit CTR11 as an example, the first switch M11 is configured between the first AC signal SAC1 and the impedance matching circuits CMR11~CMR13, and is controlled by the corresponding first control signals SC11~SC13 to be turned on; the second switch M12 It is arranged between the impedance matching circuits CMR11 to CMR13 and the first end of the transmitting antenna ATX, and is controlled by the corresponding first control signals SC11 to SC13 to be turned on.

In the embodiment with the present invention, the impedance matching circuits CMR11 to CMR13 can be purely resistive, purely capacitive, purely inductive, or any combination of the foregoing. In other words, the impedance matching circuits CMR11 to CMR13 can be resistance-inductance-capacitance circuits (that is, including at least one resistor, at least one capacitor, and at least one inductance), and resistance circuits (also That is, it includes at least one resistor), a capacitor (that is, it includes at least one capacitor), or an inductive circuit (that is, it includes at least one inductance), but the embodiment of the present invention is not limited thereto. Among them, resistance, capacitance and/or inductance are used to form the corresponding impedance value.

3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the invention. 2 and FIGS. 3A to 3C, in this embodiment, the first AC signal SAC1 is a sine wave signal as an example, but the embodiment of the present invention is not limited thereto. In addition, with respect to the frequency of the first AC signal SAC1, the impedance value of the impedance matching circuit CMR11 is zero, the impedance value of the impedance matching circuit CMR12 is higher than that of the impedance matching circuit CMR11, and the impedance value of the impedance matching circuit CMR13 is the highest.

As shown in FIG. 3A, the first control signal SC11 is enabled, and the first control signals SC12 and SC13 are disabled. That is, the first AC signal SAC1 is only transmitted to the impedance matching circuit CMR11 of the first impedance circuit CTR11, and passes through the impedance matching circuit. The first AC signal XSAC1 whose amplitude is adjusted by the CMR11 has a larger amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 overlap.

As shown in FIG. 3B, the first control signal SC12 is enabled, and the first control signals SC11 and SC13 are disabled. That is, the first AC signal SAC1 is only transmitted to the impedance matching circuit CMR12 of the first impedance circuit CTR12, and passes through the impedance matching circuit. The first AC signal XSAC1 whose amplitude is adjusted by CMR12 has a smaller amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 do not overlap, and the amplitude of the first AC signal XSAC1 is smaller than the first AC signal SAC1 (as indicated by the dashed line Show).

As shown in FIG. 3C, the first control signal SC13 is enabled, and the first control signals SC11 and SC12 are disabled, that is, the first AC signal SAC1 is only transmitted to the first impedance The impedance matching circuit CMR13 of the circuit CTR13, and the first AC signal XSAC1 whose amplitude is adjusted by the impedance matching circuit CMR13 has the smallest amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 do not overlap and the first AC signal XSAC1 The amplitude of is smaller than the first AC signal SAC1 (shown by the dashed line) and the first AC signal XSAC1 shown in FIG. 3B.

In the above embodiment, three first impedance circuits (such as CTR11 to CTR13) are taken as an example, but in other embodiments, there may be any number of first impedance circuits. Moreover, in the above-mentioned embodiment, one of the first control signals SC11~SC13 is enabled, that is, the first AC signal SAC1 is only adjusted in amplitude through one of the impedance matching circuits CMR11~CMR13, but in other implementations In an example, any two or all of the first control signals SC11 to SC13 can be enabled, that is, the first AC signal SAC1 can be adjusted in amplitude through any two or all of the impedance matching circuits CMR11 to CMR13.

4 is a schematic circuit diagram of a pixel block and a driving circuit according to another embodiment of the invention. 2 and 4, the driving circuit 110a is substantially the same as the driving circuit 110, the difference is that the driving circuit 110a further includes a plurality of second impedance circuits CTR21 to CTR23. In this embodiment, the driving signal generating circuit 111a is more responsive to the first bit portion B1 of the display data DDX to generate the second AC signal SAC2, and the control signal generating circuit 113a is more responsive to the second bit portion of the display data DDX Part B2 generates a plurality of second control signals SC21~SC23. The second impedance circuits CTR21 to CTR23 individually receive one of the second control signals SC21 to SC23, and are controlled by the corresponding second control signals SC21 to SC23 to be enabled.

The second impedance circuits CTR21~CTR23 are connected in parallel between the first end of the transmitting antenna ATX and the second AC signal SAC2, and each have different impedance values, namely the first impedance circuit CTR11~CTR13 and the second impedance circuit CTR21~CTR23 Have different impedance values.

In this embodiment, the driving signal generating circuit 111a generates the first AC signal SAC1 and/or the second AC signal SAC2 in response to the first bit portion B1 of the display data DDX, wherein the first AC signal SAC1 and the second AC signal SAC2 can have a different frequency or a different length of time. In addition, the control signal generating circuit 113a responds to the second bit portion B2 of the display data DDX to enable one, part or all of the first control signals SC11 to SC13 and the second control signals SC21 to SC23.

The enabled first impedance circuit (such as CTR11~CTR13) is used to adjust the amplitude of the first AC signal SAC1 according to the impedance value (that is, the first AC signal XSAC1) to the transmitting antenna ATX, and the enabled The second impedance circuit (such as CTR21~CTR23) is used to adjust the amplitude of the second AC signal SAC2 according to the impedance value it has (ie, the second AC signal XSAC2) and transmit it to the transmitting antenna ATX. In this embodiment, the structure of the second impedance circuit (such as CTR21~CTR23) can be the same as that of the first impedance circuit (such as CTR11~CTR13), that is, the second impedance circuit (such as CTR21~CTR23) individually includes an impedance matching circuit ( Such as CMR21~CMR23), the first switch (such as M41, M51, M61), and the second switch (such as M42, M52, M62), in which the impedance matching circuit CMR21~CMR23 have corresponding impedance values (that is, have different impedance value).

FIG. 5 is a schematic circuit diagram of a pixel block according to an embodiment of the invention. 1 and 5, in this embodiment, the pixel block 21 includes a plurality of pixels 21a. The pixel 21a includes a receiving antenna ARX, multiple diodes (such as transistors T1 and T3 using diode connection), multiple clock switches (such as T2 and T4), a first axial switch TX, and a second Axial switch TY and pixel capacitance CPX. The receiving antenna ARX is used to receive the corresponding driving electromagnetic signal.

The first end of the transistor T1 is coupled to the first end of the receiving antenna ARX. The first terminal of the clock switch T2 is coupled to the second terminal of the transistor T1, and the control terminal of the clock switch T2 receives the first clock signal Odd_CK. The second end of the receiving antenna ARX receives the common voltage VCOM. The first end of the transistor T3 is coupled to the first end of the receiving antenna ARX. The first terminal of the clock switch T4 is coupled to the second terminal of the transistor T3, the control terminal of the clock switch T4 receives the second clock signal Even_CK, and the second terminal of the clock switch T4 is coupled to the second terminal of the clock switch T2. The enable period of the first clock signal Odd_CK does not overlap with the enable period of the second clock signal Even_CK, or the first clock signal Odd_CK and the second clock signal Even_CK are mutually inverted.

The first end of the first axial switch TX is coupled to the second end of the clock switch T2, and the first axial switch TX is controlled to be turned on or off by the corresponding first axial control signal Xm. The first end of the second axial switch TY is coupled to the second end of the first axial switch TX, the second end of the second axial switch TY is coupled to the first end of the pixel capacitor CPX, and the second axis The direction switch TY is controlled by the corresponding second axial control signal Yn to be turned on or off. The second end of the pixel capacitor CPX receives the common voltage VCOM.

In the embodiment, in the pixel block 21, the receiving antenna ARX, these diodes (For example, transistors T1 and T3 with diode connection) and these clock switches (such as T2 and T4) can be shared by all pixels 21a, that is, each pixel 21a can only include the first axis switch TX , The second axial switch TY and pixel capacitance CPX.

In summary, with the display device of the embodiment of the present invention, through the adjustment of the amplitude, the driving electromagnetic signal generated by the transmitting antenna can have more levels, which can increase the contrast of the pixels in each pixel block.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

110: drive circuit

111: Drive signal generating circuit

113: Control signal generating circuit

ARX: receiving antenna

ATX: transmit antenna

B1: The first bit part

B2: The second part

CMR11~CMR13: impedance matching circuit

CTR11~CTR13: the first impedance circuit

DDX: display data

M11, M21, M31: the first switch

M12, M22, M32: second switch

OLD: Light-emitting element

SAC1, XSAC1: the first AC signal

SC11~SC13: the first control signal

SDM: Drive electromagnetic signal

TX1~TX4: the first axis switch

TY1~TY4: second axial switch

X1~X4: first axis control signal

Y1~Y4: second axis control signal

Claims (14)

A display device includes: A display array having a plurality of pixel blocks, each of the pixel blocks includes a receiving antenna to receive corresponding driving electromagnetic signals; A driving array has a plurality of driving circuits, and each of the driving circuits includes: A transmitting antenna, coupled with the receiving antenna; A plurality of first impedance circuits are connected in parallel between the transmitting antenna and the first AC signal, and each has different impedance values, wherein at least one of the first impedance circuits is enabled to enable the first AC signal The amplitude is adjusted according to the impedance value and transmitted to the transmitting antenna. As for the display device described in claim 1, wherein the first impedance circuits receive a plurality of first control signals to be enabled in response to the corresponding first control signals. In the display device described in item 2 of the scope of patent application, the first impedance circuits individually include: An impedance matching circuit with a corresponding impedance value; A first switch, configured between the first AC signal and the impedance matching circuit, and controlled to be turned on by the corresponding first control signal; and A second switch is arranged between the impedance matching circuit and the transmitting antenna, and is controlled to be turned on by the corresponding first control signal. As for the display device described in item 3 of the scope of patent application, the impedance matching circuit is a resistance, inductance, and capacitance circuit. As described in item 3 of the scope of patent application, the impedance matching circuit includes a capacitor to form a corresponding impedance value. As the display device described in item 3 of the scope of patent application, it also includes A driving signal generating circuit that receives a display data to generate the first AC signal; and A control signal generating circuit receives the display data to generate the first control signals. The display device described in item 6 of the scope of patent application, wherein the driving signal generation circuit refers to a first bit portion of the display data to generate the first AC signal, and the control signal generation circuit refers to the display data A second bit part generates the first control signals. For the display device described in item 7 of the scope of patent application, the first bit part is a high bit part, and the second bit part is a low bit part. In the display device described in item 7 of the scope of patent application, the first bit portion and the second bit portion do not overlap. In the display device described in item 7 of the scope of patent application, the first bit portion and the second bit portion partially overlap. According to the display device described in item 6 of the scope of patent application, the driving signal generating circuit generates a second AC signal in response to the display data, and the control signal generating circuit generates a plurality of second controls in response to the display data signal, The display device further includes a plurality of second impedance circuits, individually controlled by corresponding second control signals to be enabled, connected in parallel between the transmitting antenna and the second AC signal, and each having a different impedance value, At least one of the first impedance circuits and the second impedance circuits is enabled to adjust the amplitude of the first AC signal and the second AC signal according to the impedance value that it has and then transmit to the transmitting antenna. In the display device described in item 11 of the scope of patent application, the first AC signal is a sine wave signal. In the display device described in the first item of the scope of patent application, one of the first impedance circuits is enabled to adjust the amplitude of the first AC signal according to the impedance value of the display device and then transmit it to the transmitting antenna. According to the display device described in item 1 of the scope of patent application, the first AC signal is a sine wave signal.

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