TWI711091B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a chip package structure includes a following steps. At least one diced wafer is provided. A carrier is provided with an adhesive layer. The diced wafer is positioned on the carrier through the adhesive layer. A redistribution layer is formed on the diced wafer. The diced wafer is electrically connected to the redistribution layer. A singulation process is performed on the diced wafer and the redistribution layer to form a plurality of chip package structures.

Description

Chip packaging structure and manufacturing method thereof

The invention relates to a packaging structure and a manufacturing method thereof, and more particularly to a chip packaging structure and a manufacturing method thereof.

With the advancement of electronic technology, the size of semiconductor components is gradually shrinking, while providing more powerful functions and including larger capacity integrated circuits. Due to the miniaturization of semiconductor components, wafer level chip scale package (WLCSP) is widely used in manufacturing.

As far as the packaging type of wafer-level chip scale packaging (WLCSP) is concerned, it is a technology to obtain a chip package structure by encapsulating a single wafer through semiconductor equipment and semiconductor manufacturing processes before cutting. However, because wafer-level chip scale packaging (WLCSP) uses semiconductor equipment and semiconductor manufacturing processes, it cannot effectively reduce manufacturing costs. In addition, in each manufacturing process, only one wafer is manufactured, so the productivity cannot be effectively increased.

The present invention provides a chip packaging structure and a manufacturing method thereof, which can have high throughput and can reduce production costs.

The manufacturing method of the chip package structure of the present invention includes the following steps. Provide at least one diced wafer. Provide a carrier board with an adhesive layer. The cut wafer is positioned on the carrier board through the adhesive layer. A reconfiguration circuit layer is formed on the diced wafer. The cut wafer is electrically connected to the reconfiguration circuit layer. A singulation process is performed on the cut wafer and the reconfiguration circuit layer to form a plurality of chip package structures.

In an embodiment of the present invention, the manufacturing method of the above-mentioned chip package structure further includes: providing at least one uncut wafer while providing the cut wafer. Before the diced wafer is positioned on the carrier board through the adhesive layer, a board with at least one first opening and at least one second opening is provided on the adhesive layer. The board is positioned on the carrier board through the adhesive layer. The uncut wafer and the cut wafer are respectively arranged in the first opening and the second opening, and are positioned on the carrier board through the adhesive layer.

In an embodiment of the present invention, the outline of the first opening described above is equal to or greater than the outline of the uncut wafer. The outline of the second opening is equal to or greater than the outline of the cut wafer.

In an embodiment of the present invention, the aforementioned uncut wafer has a first active surface and a first back surface opposite to each other. The diced wafer has a second active surface and a second back surface opposite to each other. The first back surface of the uncut wafer and the second back surface of the cut wafer directly contact the adhesive layer.

In an embodiment of the present invention, the above-mentioned board has an upper surface, and the first active surface of the uncut wafer and the second active surface of the cut wafer are aligned with the upper surface of the board.

In an embodiment of the present invention, the aforementioned uncut wafer includes a plurality of first pads arranged on the first active surface. The diced wafer includes a plurality of second pads arranged on the second active surface. The first pad and the second pad are respectively electrically connected to the reconfiguration circuit layer.

In an embodiment of the present invention, the manufacturing method of the aforementioned chip package structure further includes: forming a plurality of solder balls on the reconfiguration circuit layer before the singulation process is performed on the cut wafer and the reconfiguration circuit layer. The solder balls are electrically connected to the cut wafer through the reconfiguration circuit layer.

In an embodiment of the present invention, the manufacturing method of the aforementioned chip package structure further includes: after forming solder balls on the reconfiguration circuit layer, and before performing a singulation process on the cut wafer and the reconfiguration circuit layer, Remove the carrier board and the adhesive layer.

In an embodiment of the present invention, the outline of the diced wafer described above is at least composed of a straight line and an arc connecting the straight line.

The manufacturing method of the chip package structure of the present invention includes the following steps. Provide at least one diced wafer. Provide a carrier board with an adhesive layer. The cut wafer is positioned on the carrier board through the adhesive layer. A first singulation process is performed on the diced wafer to form a plurality of chips positioned on the carrier board through the adhesive layer. A packaging glue is formed on the adhesive layer, wherein the packaging glue covers the chip. The carrier board and the adhesive layer are removed, and a bottom surface of the packaging glue is exposed. A reconfiguration circuit layer is formed on the bottom surface of the packaging compound, wherein the reconfiguration circuit layer is electrically connected to the chip. A second singulation process is performed on the packaging glue, the chip and the reconfiguration circuit layer to form a plurality of chip packaging structures.

In an embodiment of the present invention, the manufacturing method of the above-mentioned chip package structure further includes: providing at least one uncut wafer while providing the cut wafer. The uncut wafer has a first active surface and a first back surface opposite to each other. The diced wafer has a second active surface and a second back surface opposite to each other. The first active surface of the uncut wafer and the second active surface of the cut wafer directly contact the adhesive layer.

In an embodiment of the present invention, there is a horizontal distance between the two adjacent wafers, and the horizontal distance is 30 μm to 100 μm.

In an embodiment of the present invention, the manufacturing method of the above-mentioned chip package structure further includes: forming a plurality of solder balls on the reconfiguration circuit before performing the second singulation process on the package compound, the chip and the reconfiguration circuit layer On the layer, the solder balls are electrically connected to the chip through the reconfiguration circuit layer.

In an embodiment of the present invention, there is a horizontal distance between an edge of the above-mentioned encapsulant and a peripheral surface of the chip, and the horizontal distance is 15 μm to 50 μm.

In an embodiment of the present invention, the outline of the diced wafer described above is at least composed of a straight line and an arc connecting the straight line.

The chip package structure of the present invention includes a chip and a reconfiguration circuit layer. The chip has an active surface and a back surface opposite to each other, and includes a plurality of pads arranged on the active surface. The reconfiguration circuit layer is disposed on the active surface of the chip and is electrically connected to the pads.

In an embodiment of the present invention, the above-mentioned chip package structure further includes: a plurality of solder balls disposed on the reconfiguration circuit layer and electrically connected to the pads of the chip through the reconfiguration circuit layer.

In an embodiment of the present invention, the edge of the aforementioned wafer is aligned with the edge of the reconfiguration circuit layer.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes: an encapsulating compound disposed on the reconfiguration circuit layer and covering the chip, wherein the encapsulating compound covers the backside of the chip.

In an embodiment of the present invention, the edge of the above-mentioned encapsulation glue is aligned with the edge of the reconfiguration circuit layer.

Based on the foregoing, in the manufacturing method of the chip package structure of the present invention, a reconfiguration circuit layer is formed on at least one diced wafer and a singulation process is performed to form a plurality of chip package structures. Compared with the conventional fabrication of wafer-level chip scale packages that only target one complete uncut wafer at a time, the fabrication method of the chip package structure of the present invention can have a higher yield and can effectively reduce production costs.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1F are schematic diagrams of a manufacturing method of a chip package structure according to an embodiment of the present invention. For the convenience of description, FIGS. 1A and 1C are shown in plan view, and FIGS. 1B, 1D to 1F are shown in cross section.

Regarding the manufacturing method of the chip package structure of this embodiment, first, please refer to FIG. 1A to provide at least one diced wafer (schematically shows a diced wafer 110b). Here, the outline of the cut wafer 110b is embodied by a straight line S and an arc C connecting the straight line S, but it is not limited to this.

As shown in FIG. 1A, the present embodiment provides at least one uncut wafer (one uncut wafer 110a is schematically shown) while providing a cut wafer 110b. Here, the size of the uncut wafer 110a is larger than the size of the cut wafer 110b, and the outline of the uncut wafer 110a is embodied as a circle.

Next, please refer to FIG. 1B to provide a carrier board 10 that has been configured with an adhesive layer 12. Here, the adhesive layer 12 is, for example, a double-sided thermal release tape, and the carrier board 10 is, for example, a printed circuit board or a temporary substrate without electrical functions, but not limited to this.

Next, referring to FIG. 1C, in order to improve the yield of the subsequent process, at least one first opening (schematically shows a first opening 22a) and at least one second opening (schematically shows a first opening 22a) can be selectively provided. Two openings 22b) a plate 20. Here, the board 20 is, for example, a printed circuit board or a temporary substrate without electrical functions, but it is not limited thereto.

Next, referring to FIGS. 1A, 1C and 1D at the same time, the board 20 is disposed on the adhesive layer 12 of the carrier board 10, and the board 20 is positioned on the carrier board 10 through the adhesive layer 12. Then, the uncut wafer 110a and the diced wafer 110b are positioned on the carrier board 10 through the adhesive layer 12. Here, the uncut wafer 110a and the diced wafer 110b are respectively arranged in the first opening 22a and the second opening 22b, and are positioned on the carrier board 10 through the adhesive layer 12. Preferably, the outline of the first opening 22a is equal to or larger than the outline of the uncut wafer 110a. The outline of the second opening 22b is equal to or larger than the outline of the cut wafer 110b.

Furthermore, in this embodiment, the uncut wafer 110a has a first active surface 111a and a first back surface 113a opposite to each other. The diced wafer 110b has a second active surface 111b and a second back surface 113b opposite to each other. The first back surface 113 a of the uncut wafer 110 a and the second back surface 113 b of the cut wafer 110 b directly contact the adhesive layer 12. That is, the uncut wafer 110a and the diced wafer 110b of this embodiment are arranged on the carrier board 10 in an active face-up manufacturing manner.

Furthermore, the plate 20 of this embodiment has an upper surface 21, and the first active surface 111a of the uncut wafer 110a and the second active surface 111b of the cut wafer 110b are aligned with the upper surface 21 of the plate 20 . That is, the upper surface 21 of the plate 20, the first active surface 111a of the uncut wafer 110a, and the second active surface 111b of the cut wafer 110b are coplanar, which can improve the subsequent reconfiguration circuit layer 120 (please refer to Figure 1E) Process yield. In addition, the uncut wafer 110a of this embodiment further includes a plurality of first pads 112a disposed on the first active surface 111a, and the diced wafer 110b further includes a plurality of second pads 112a disposed on the second active surface 111b.接垫112b.

Then, referring to FIG. 1E, a reconfiguration circuit layer 120 is formed on the uncut wafer 110a and the diced wafer 110b, wherein the first pad 112a of the uncut wafer 110a and the second pad of the diced wafer 110b 112b is electrically connected to the reconfiguration circuit layer 120 respectively. Next, a plurality of solder balls 130 are formed on the reconfiguration circuit layer 120, wherein the solder balls 130 are electrically connected to the uncut wafer 110a and the diced wafer 110b through the reconfiguration circuit layer 120.

Finally, referring to FIGS. 1E and 1F at the same time, remove the board 20, the carrier board 10 and the adhesive layer 12 on the carrier board 10, and perform the uncut wafer 110a and the reconfigured circuit layer 120 as well as the cut wafer 110b and The reconfiguration circuit layer 120 performs a singulation process to form a plurality of chip package structures (a chip package structure 100 is schematically shown). So far, the manufacturing method of the chip package structure 100 has been completed.

In terms of structure, please refer to FIG. 1F again. The chip package structure 100 of this embodiment includes a chip 110 and a reconfiguration circuit layer 120'. The chip 110 has an active surface 111 and a back surface 113 opposite to each other, and includes a plurality of pads 112 disposed on the active surface 111. The reconfiguration circuit layer 120' is disposed on the active surface 111 of the chip 110 and is electrically connected to the pad 112. The reconfiguration circuit layer 120' is, for example, a fan-in circuit. Here, the edge 115 of the wafer 110 is aligned with the edge 121 of the reconfiguration circuit layer 120'. In addition, the chip package structure 100 of this embodiment further includes a plurality of solder balls 130 disposed on the reconfiguration circuit layer 120', and electrically connected to the pad 112 of the chip 110 through the reconfiguration circuit layer 120'.

In the manufacturing method of the chip package structure 100 of this embodiment, the reconfiguration circuit layer 120 is formed on the at least one uncut wafer 110a and the at least one diced wafer 110b and the singulation process is performed to form the chip package structure 100. Compared with the conventional fabrication of wafer-level chip scale packaging for only one wafer at a time, the fabrication method of the chip packaging structure 100 of this embodiment can have a higher yield. In addition, the present embodiment uses the circuit board manufacturing process and equipment to manufacture the chip package structure 100, so the production cost can be effectively reduced.

It is worth mentioning that, in the above embodiment, only one uncut wafer 110a and one cut wafer 110b are shown on the carrier board 10, but not limited to this. In essence, the number of uncut wafers 110a and diced wafers 110b can be determined according to the size of the carrier plate 10, and the contour shape of the diced wafers 110b can also be determined according to the configuration of the uncut wafers 110a. The area of the carrier board 10 determines its shape, which can be used for maximum space configuration.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A to 2G are schematic diagrams of a manufacturing method of a chip package structure according to another embodiment of the present invention. For convenience of description, FIG. 2A is shown in a top view, and FIGS. 2B to 2G are shown in cross-section.

Regarding the manufacturing method of the chip package structure of this embodiment, first, please refer to FIG. 2A to provide at least one diced wafer (schematically show four diced wafers 210c, 210d, 210e, and 210f). Here, the outline of the cut wafer 210c, 210d, and 210f is composed of a straight line S and an arc C connecting the straight line S, and the outline of the cut wafer 210e is composed of two straight lines S1, S2 and The two straight lines S1 and S2 are formed by two arcs C1 and C2, but not limited to this.

As shown in FIG. 2A, while providing cut wafers 210c, 210d, 210e, and 210f, at least one uncut wafer is also provided (two uncut wafers 210a, 210b are schematically shown). Here, the size of the uncut wafers 210a, 210b is larger than the size of the cut wafers 210c, 210d, 210e, and 210f, and the outline of the uncut wafers 210a, 210b is embodied as a circle.

Next, referring to FIG. 2B, a carrier board 10 that has been configured with an adhesive layer 12 is provided. Here, the adhesive layer 12 is, for example, a double-sided thermal release tape (thermal release tape), but it is not limited thereto. Next, the uncut wafer (only the uncut wafer 210a is schematically shown) and the cut wafer (only the cut wafer 210c is schematically shown) are positioned on the carrier board 10 through the adhesive layer 12. Here, the uncut wafer 210a has a first active surface 211a and a first back surface 213a opposite to each other. The diced wafer 210c has a second active surface 211c and a second back surface 213c opposite to each other. The first active surface 211a of the uncut wafer 210a and the second active surface 211c of the diced wafer 210c directly contact the adhesive layer 12. In other words, the uncut wafer 210a and the diced wafer 210c of this embodiment are arranged on the carrier board 10 in an active face-down manufacturing manner.

Next, referring to FIG. 2C, perform a first singulation process on the undiced wafer (only the undiced wafer 210a is schematically shown) and the diced wafer (only the diced wafer 210c is schematically shown) , To form a plurality of chips 210 positioned on the carrier board 10 through the adhesive layer 12. Here, there is a horizontal gap G between two adjacent chips 210, and the horizontal gap G is 30 micrometers to 100 micrometers, which can have a better packaging margin.

Next, referring to FIG. 2D, an encapsulant 220 is formed on the adhesive layer 12, wherein the encapsulant 220 covers the chip 210.

Next, referring to FIG. 2E, the carrier board 10 and the adhesive layer 12 are removed, and a bottom surface 222 of the packaging glue 220 is exposed. At this time, the active surface 211 of the chip 210 is aligned with the bottom surface 222 of the packaging compound 220.

Afterwards, referring to FIG. 2F, a reconfiguration circuit layer 230 is formed on the bottom surface 222 of the encapsulant 220, wherein the reconfiguration circuit layer 230 is electrically connected to the chip 210. Next, a plurality of solder balls 240 are formed on the reconfiguration circuit layer 230, wherein the solder balls 230 are electrically connected to the pads 212 of the chip 210 through the reconfiguration circuit layer 230.

Finally, referring to FIG. 2G, a second singulation process is performed on the packaging compound 220, the chip 210, and the reconfiguration circuit layer 230 to form a plurality of chip packaging structures 200. So far, the fabrication of the chip packaging structure 200 with the packaging glue 220 has been completed.

In terms of structure, please refer to FIG. 2G again. The chip package structure 200 of this embodiment includes a chip 210 and a reconfiguration circuit layer 230'. The chip 210 has an active surface 211 and a back surface 213 opposite to each other, and includes a plurality of pads 212 disposed on the active surface 211. The reconfiguration circuit layer 230' is disposed on the active surface 211 of the chip 210 and is electrically connected to the pad 212. The reconfiguration circuit layer 230' is, for example, a fan-out circuit. Furthermore, the chip packaging structure 200 of this embodiment further includes a packaging glue 220' disposed on the reconfiguration circuit layer 230' and covering the chip 210, wherein the packaging glue 220' covers the back surface 213 of the chip 210. Here, the edge 221 of the encapsulant 220' is aligned with the edge 231 of the reconfiguration circuit layer 230. There is a horizontal distance between the edge 221 of the encapsulant 220' and a peripheral surface 215 of the chip 210, and the horizontal distance H is 15-50 microns to protect the chip 210. In addition, the chip package structure 200 of the present embodiment further includes a plurality of solder balls 240 disposed on the reconfiguration circuit layer 230' and electrically connected to the pads 212 of the chip 210 through the reconfiguration circuit layer 230'.

In summary, in the manufacturing method of the chip package structure of the present invention, a reconfiguration circuit layer is formed on at least one diced wafer and a singulation process is performed to form a plurality of chip package structures. Compared with the conventional fabrication of wafer-level chip size packages for only one wafer at a time, the fabrication method of the chip package structure of the present invention can have a higher yield and can effectively reduce production costs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Carrying board 12: Adhesive layer 20: Plate 21: upper surface 22a: first opening 22b: second opening 100: Chip package structure 110, 210: chip 110a, 210a, 210b: uncut wafers 110b, 210c, 210d, 210e, 210f: diced wafer 111, 211: Active side 111a, 211a: the first active surface 111b, 211c: second active surface 112, 212: pad 112a: first pad 112b: second pad 113, 213: Back 113a, 213a: first back 113b, 213c: second back 115, 121, 221, 231: edge 120, 120’, 230, 230’: reconfiguration line layer 130, 240: solder ball 215: Surrounding surface 220, 220’: Encapsulating gel 222: bottom surface C, C1, C2: arc G: Horizontal spacing H: horizontal distance S, S1, S2: straight line

1A to 1F are schematic diagrams of a manufacturing method of a chip package structure according to an embodiment of the present invention. 2A to 2G are schematic diagrams of a manufacturing method of a chip package structure according to another embodiment of the present invention.

10: Carrying board

12: Adhesive layer

20: Plate

110a: Uncut wafer

110b: diced wafer

112a: first pad

112b: second pad

120: reconfiguration line layer

130: solder ball

Claims (13)

A method for manufacturing a chip package structure includes: providing at least one diced wafer, wherein the outline of the at least one diced wafer is formed by at least a straight line and an arc connecting the straight line; and providing an adhesive Layer of a carrier board; enabling the at least one cut wafer to be positioned on the carrier board through the adhesive layer; forming a reconfiguration circuit layer on the at least one cut wafer, wherein the at least one cut wafer and The reconfiguration circuit layer is electrically connected; and a singulation process is performed on the at least one cut wafer and the reconfiguration circuit layer to form a plurality of chip package structures. The manufacturing method of the chip package structure according to claim 1, further comprising: providing at least one uncut wafer when the at least one cut wafer is provided; and positioning the at least one cut wafer through the adhesive layer Before the carrying plate, a plate having at least one first opening and at least one second opening is provided on the adhesive layer, and the plate is positioned on the carrying plate through the adhesive layer; and the at least one The uncut wafer and the at least one cut wafer are respectively disposed in the at least one first opening and the at least one second opening, and are positioned on the carrier board through the adhesive layer. The manufacturing method of the chip package structure according to claim 2, wherein the outline of the at least one first opening is equal to or greater than the outline of the at least one uncut wafer, and the outline of the at least one second opening The contour is equal to or greater than the outer contour of the at least one cut wafer. The method for manufacturing a chip package structure according to claim 2, wherein the at least one uncut wafer has a first active surface and a first back surface opposite to each other, and the at least one cut wafer has a first active surface opposite to each other The second active surface and a second back surface, the first back surface of the at least one uncut wafer and the second back surface of the at least one cut wafer directly contact the adhesive layer. The method for manufacturing a chip package structure according to claim 4, wherein the plate has an upper surface, and the first active surface of the at least one uncut wafer and the second active surface of the at least one cut wafer The surface is in line with the upper surface of the plate. The method for manufacturing a chip package structure according to claim 4, wherein the at least one uncut wafer includes a plurality of first pads disposed on the first active surface, and the at least one diced wafer includes A plurality of second pads on the second active surface, the first pads and the second pads are respectively electrically connected to the reconfiguration circuit layer. The manufacturing method of the chip package structure according to claim 1, further comprising: forming a plurality of solder balls on the reconfiguration circuit layer before performing the singulation process on the at least one diced wafer and the reconfiguration circuit layer Above, the solder balls are electrically connected to the at least one diced wafer through the reconfiguration circuit layer. The manufacturing method of the chip package structure according to claim 7, further comprising: after forming the solder balls on the reconfiguration circuit layer, and performing the monomer operation on the at least one cut wafer and the reconfiguration circuit layer Before the chemical process, remove the carrier board and the adhesive layer. A method for manufacturing a chip package structure includes: providing at least one diced wafer, wherein the outline of the at least one diced wafer is formed by at least a straight line and an arc connecting the straight line; and providing an adhesive The at least one cut wafer is positioned on the support board through the adhesive layer; the first singulation process is performed on the at least one cut wafer to form a through the adhesive layer And a plurality of chips positioned on the carrier board; forming an encapsulating glue on the adhesive layer, wherein the encapsulating glue covers the chips; removing the carrier board and the adhesive layer to expose a part of the encapsulating glue Bottom surface; forming a reconfiguration circuit layer on the bottom surface of the packaging compound, wherein the reconfiguration circuit layer is electrically connected to the chips; and performing a second operation on the packaging compound, the chips, and the reconfiguration circuit layer Secondary singulation process to form multiple chip package structures. The manufacturing method of the chip package structure according to claim 9, further comprising: when the at least one cut wafer is provided, at least one uncut wafer is simultaneously provided, wherein the at least one uncut wafer has a first An active surface and a first back surface, the at least one cut wafer has a second active surface and a second back surface opposite to each other, the first active surface and the at least one back surface of the at least one uncut wafer The second active surface of the dicing wafer directly contacts the adhesive layer. The manufacturing method of the chip package structure according to claim 9, wherein there is a horizontal interval between two adjacent chips, and the horizontal interval is 30 μm to 100 μm. The manufacturing method of the chip package structure according to claim 9, further comprising: forming a plurality of solder balls on the reconfiguration circuit layer before performing the second singulation procedure on the package compound, the chips and the reconfiguration circuit layer. On the configuration circuit layer, the solder balls are electrically connected to the chips through the reconfiguration circuit layer. The manufacturing method of the chip packaging structure according to claim 9, wherein there is a horizontal distance between an edge of the packaging compound and a peripheral surface of the chip, and the horizontal distance is 15 to 50 μm.

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