TWI709855B - Method for performing writing management in a memory device, and associated memory device and controller thereof - Google Patents

Abstract

A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.

Description

Method for writing management in a memory device, memory device and controller thereof

The present invention relates to flash memory (Flash memory) access, in particular to a method for writing management in a memory device and related memory devices and their controllers.

In recent years, due to the continuous development of memory technology, various portable or non-portable memory devices (for example: memory cards that conform to SD/MMC, CF, MS, XD or UFS standards; another example: solid state drives; and For example, embedded storage devices complying with UFS or EMMC specifications are widely implemented in many applications. Therefore, the access control of the memory in these memory devices has become a very hot topic.

In terms of commonly used NAND-type flash memory, it can be mainly divided into two types of flash memory, single level cell (SLC) and multiple level cell (MLC). Each transistor used as a memory cell in a single-level cell flash memory has only two charge values, which are used to represent a logic value of 0 and a logic value of 1. In addition, the storage capacity of each transistor used as a memory cell in the multi-level cell flash memory is fully utilized. It is driven by a higher voltage to record in a transistor through different levels of voltage. At least two sets of bit information (such as 00, 01, 11, 10); theoretically, the recording density of a multi-level cell flash memory can reach at least twice the recording density of a single-level cell flash memory. It is very good news for the related industries of NAND flash memory that have encountered bottlenecks in the development process.

Compared with single-level cell flash memory, multi-level cell flash memory is cheaper in price and can provide larger capacity in a limited space, so multi-level cell flash memory quickly becomes the market The mainstream memory devices are competing to adopt. However, the problems caused by the instability of multi-level cell flash memory have also emerged one by one. In order to ensure that the memory device's access control to the flash memory can comply with relevant specifications, the flash memory controller is usually equipped with some management mechanism to properly manage data access.

According to related technologies, memory devices with these management mechanisms still have shortcomings. For example, under the condition of using newer technology to manufacture flash memory, certain design concepts can cause the buffer size of the memory device to double the original requirement. There is a gap between budget control and product performance. The trade-off can be regarded as a bottleneck in the use of newer technologies to manufacture flash memory. Therefore, a novel method and related architecture are needed to improve the performance of the memory device without side effects or less likely to cause side effects.

An object of the present invention is to provide a method for writing management in a memory device and related memory device and its controller to solve the above problems.

Another object of the present invention is to provide a method for writing management in a memory device and related memory device and its controller, so as to achieve the performance of the memory device without side effects or less likely to cause side effects. Optimal performance.

At least one embodiment of the present invention provides a method for writing management in a memory device, wherein the memory device includes a non-volatile memory (NV memory), and the non-volatile memory includes One or more non-volatile memory elements (NV memory element), any of the one or more non-volatile memory elements includes multiple blocks, and any of the multiple blocks One contains multiple pages. The method includes: receiving a series of data from a host device to take out even-page data and odd-page data from the series of data; writing the first partial (partial) data of the even-page data to the non- Volatile memory; send a first group of commands without a confirmation command to the non-volatile memory to write the first partial data and the second partial data of the even page data into the non-volatile memory An internal buffer, wherein the confirmation command is used to trigger the non-volatile memory to execute at least one command to program at least one non-volatile memory element in the non-volatile memory ; Send a second set of commands and the confirmation command to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the at least one command Includes the second set of commands, and the confirmation command triggers the non-volatile memory to execute the second set of commands; writes the third partial data in the odd page data to the non-volatile memory; and the first partial Data and the second partial data are written to an even page of another block in the non-volatile memory, and the third partial data and the fourth partial data of the odd page data are written to the other An odd page of the block.

At least one embodiment of the present invention provides a memory device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes one or more non-volatile memory elements, the one or more Any one of a non-volatile memory device includes multiple blocks, and any one of the multiple blocks includes multiple pages; and a controller coupled to the non-volatile memory for controlling The operation of the memory device. The controller may include a processing circuit, and the processing circuit may control the controller according to a plurality of master device commands from a master device to allow the master device to access the non-volatile memory through the controller. For example: the controller receives a series of data from the main device to retrieve even page data and odd page data from the series of data; the controller writes the first partial data of the even page data to the non-volatile memory ; The controller sends a first set of commands without a confirmation command to the non-volatile memory to write the first partial data and the second partial data in the even page data into the non-volatile memory An internal buffer, wherein the confirmation command is used to trigger the non-volatile memory to execute at least one command to program at least one non-volatile memory element in the non-volatile memory; the controller sends a second Group command and the confirmation command to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the at least one command includes the second group Command, and the confirmation command triggers the non-volatile memory to execute the second set of commands; the controller writes the third partial data in the odd page data to the non-volatile memory; and the controller uses the first The partial data and the second partial data are written to an even page of another block in the non-volatile memory, and the third partial data and the fourth partial data of the odd page data are written to the other An odd page of a block.

At least one embodiment of the present invention provides a controller for a memory device, wherein the memory device includes the controller and a non-volatile memory, the non-volatile memory includes one or more non-volatile memory elements, and the one Any one of the or multiple non-volatile memory devices includes multiple blocks, and any one of the multiple blocks includes multiple pages. The controller may include a processing circuit, and the processing circuit may control the controller according to a plurality of master device commands from a master device to allow the master device to access the non-volatile memory through the controller. For example: the controller receives a series of data from the main device to retrieve even page data and odd page data from the series of data; the controller writes the first partial data of the even page data to the non-volatile memory ; The controller sends a first set of commands without a confirmation command to the non-volatile memory to write the first partial data and the second partial data in the even page data into the non-volatile memory An internal buffer, wherein the confirmation command is used to trigger the non-volatile memory to execute at least one command to program at least one non-volatile memory element in the non-volatile memory; the controller sends a second Group command and the confirmation command to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the at least one command includes the second group Command, and the confirmation command triggers the non-volatile memory to execute the second set of commands; the controller writes the third partial data in the odd page data to the non-volatile memory; and the controller uses the first The partial data and the second partial data are written to an even page of another block in the non-volatile memory, and the third partial data and the fourth partial data of the odd page data are written to the other An odd page of a block.

One of the advantages of the present invention is that, through write management, the present invention can properly control the operation of the controller to break through the bottleneck when using newer technology to manufacture flash memory. In addition, the implementation according to the embodiments of the present invention does not increase a lot of additional costs. Therefore, the related technical problems can be solved, and the overall cost will not increase too much. Compared with the related art, the present invention can achieve the optimized performance of the memory device without side effects or less likely to cause side effects.

I. Memory System

Please refer to FIG. 1, which is a schematic diagram of a memory device 100 and a host device 50 according to a first embodiment of the present invention. For example, the memory device 100 may be a portable memory device (for example, a memory card conforming to SD/MMC, CF, MS, or XD standards) or a solid state drive (SSD). In addition, examples of the main device 50 may include (but are not limited to): multifunctional mobile phone, tablet, wearable device, and personal computer such as desktop Computers and laptops. According to this embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile memory (NV memory) 120, where the controller is used to access (Access) The non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include one or more non-volatile memory elements (NV memory elements), such as non-volatile memory elements 122-1, 122-2, ... and 122-N, where the symbol "N" Can represent a positive integer greater than one. For example: the non-volatile memory 120 can be a flash memory, and the non-volatile memory devices 122-1, 122-2, ... and 122-N can be a plurality of flash memory chips, respectively (Flash memory chip; may be referred to as a flash chip for short) or a plurality of flash memory die (Flash memory die; may be referred to as a flash die for short), but the present invention is not limited to this.

As shown in Figure 1, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage such as a read only memory (read only memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and In the transmission interface circuit 118, these components can be coupled to each other through a bus. The buffer memory 116 is implemented by random access memory (RAM). In addition, the read-only memory 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the non-volatile memory 120. Please note that the program code 112C must also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include an error correction code circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may conform to a specific communication standard (such as serial advanced technology attachments (Serial Advanced) Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, or Peripheral Component Interconnect Express (PCIE) standard) and can communicate according to the specific communication standard.

In this embodiment, the host device 50 can indirectly access the non-volatile memory 120 in the memory device 100 by sending a plurality of host commands and corresponding logical addresses to the memory controller 110 . The memory controller 110 receives the plurality of host device commands and logical addresses, and respectively translates the plurality of host device commands into memory operation commands (referred to as operation commands), and then controls the non-volatile memory 120 to read by the operation commands Fetching, writing/programming the memory unit (memory unit) or data page (page) of a specific physical address in the non-volatile memory 120, where the physical address corresponds to the logical address. For example, the memory controller 110 may generate or update at least one logical-to-physical address mapping table to manage the relationship between the physical address and the logical address.

II. Access control corresponding to the block type

In the non-volatile memory 120, any one of the non-volatile memory elements 122-1, 122-2, ... and 122-N is the non-volatile memory element 122-n (the symbol "n" can represent the interval [ 1, N] can contain multiple blocks, and one of the multiple blocks can contain and can record a specific number of pages. The memory controller 110 is non-volatile The smallest unit for the operation of erasing data by the non-volatile memory 120 can be a block, and the smallest unit for the operation of writing data to the non-volatile memory 120 by the memory controller 110 can be a page, but the invention is not limited to this . Regarding the access structure of the non-volatile memory 120, the block may include M word-lines {WL(0), WL(1), …, WL(M-1)}. For example, the memory controller 110 can write information to any word line in the block through a single-level cell (SLC) write mode. In this case, the word line can contain a single page. For another example, the memory controller 110 can write information to any word line in the block through a multi-level cell (MLC) write mode. In this case, the word line can include at least two pages. According to some embodiments, when the memory controller 110 writes information to a word line in the block through a triple level cell (TLC) write mode, the word line may include three pages.

FIG. 2 shows a block management scheme of the memory device 100 shown in FIG. 1 in an embodiment. The memory controller 110 can divide a plurality of blocks in the non-volatile memory 120 (which can include the respective blocks of the non-volatile memory elements 122-1, 122-2, ... and 122-N) into Multiple types of blocks, such as a parent block 210, a sub-block 220, and a cache block 230, which can be controlled respectively to improve the memory controller 110 The performance when accessing (for example, reading or writing) the non-volatile memory 120, in which the type of a block can be changed when needed. The memory controller 110 can select certain blocks, such as blocks 231 and 232, as the cache block 230 for temporarily storing information, and can use the single-stage cellular write mode to perform any of these blocks Write operation to save time. In addition, the memory controller 110 can use the multi-level cell write mode to perform the write operation of certain blocks to make full use of the storage capacity of these blocks. The write operations of the parent block 210 and the sub-block 220 All operations can be performed using the multi-stage cell writing mode. For example, the blocks 211 and 212 can be fully programmed blocks and can belong to the parent block 210, where the blocks 211 and 212 can store user data, but the invention is not limited thereto.

According to this embodiment, the host device 50 can send a request to the memory controller 110 to update or write data to a parent block (such as block 211 or block 212) through the memory controller 110, wherein the request It can include a host device command and corresponding logical address. The memory controller 110 can check whether any sub-block (such as the block 221 or the block 222) mapped to the parent block is stored in the non-volatile memory 120. If there is the sub-block mapped to the parent block in the non-volatile memory 120, the memory controller 110 can update the host write data to the sub-block; otherwise, the memory The controller 110 may select a blank block as a child block mapped to the parent block. For example, the parent block may represent the block 211, and the sub-block mapped to the parent block may represent the block 221. The request may indicate that the main device 50 wants to update or write the data of the sub-set 211B (eg, pages 10 to 20) of the block 211. The memory controller 110 can copy the data of the sub-set 211A (for example, pages 0-9) of the block 211 to the corresponding sub-set 221A (for example, the pages 0-9) of the block 221 so that it stores the copied data , And can write the master device write data to the sub-set 221B of block 221 (for example, pages 10 to 20) so that it stores the updated data to update or write to the same or corresponding to the parent block The location of the address, but the present invention is not limited to this. When needed, the memory controller 110 can copy the data of the sub-set 211C of the block 211 (for example, the subsequent pages from page 21) to the sub-set 221C of the block 221 (for example, the subsequent pages from the 21st page), and erase Block 211 makes it a blank block, removes the mapping relationship between block 221 and block 211, and updates the type of block 221 to make it belong to parent block 210. The end of block 211 (such as the last Page) and the end of the block 221 (such as the last page) can respectively store related management information, such as their end-of-block information (EOB information), but the invention is not limited to this.

In addition, the request can be replaced by a series of requests, which can indicate that the master device 50 wants to update the parent block multiple times, wherein the master device write data can be replaced by multiple sets of master device writes corresponding to the series of requests. Into the information. For example, the parent block may represent the block 212, and the sub-block mapped to the parent block may represent the block 222. The first request in the series of requests may indicate that the master device 50 wants to update or write data in the sub-set 212B (eg, pages 10 to 20) of the block 212. The memory controller 110 can copy the data of the sub-set 212A (for example, pages 0-9) of the block 212 to the corresponding sub-set 222A (for example, pages 0-9) of the block 222 so that it can store the copied data , And can write the master device write data corresponding to the first request to the sub-set 222B of block 222 (for example, pages 10 to 20) so that it can store the updated data to update or write to the parent area The position of the same or corresponding address in the block. The second request in the series of requests may indicate that the main device 50 wants to update or write data in the sub-set 212B (eg, pages 10-20) of the block 212. The memory controller 110 can write the master device write data corresponding to the second request to a subsequent part of the sub-set 222C of the block 222, such as a part of the same size as the sub-set 222B (for example, pages 21 to 31) ), as a replacement for the previously updated data in the subset 222B, where the previously updated data in the subset 222B can be regarded as invalid data. When necessary, the memory controller 110 can perform garbage collection, especially an empty block, and copy the data of the sub-set 212A of the block 212 (for example, pages 0 to 9) to this empty block. Corresponding position (for example, pages 0-9), copy the data of the subsequent part (for example, pages 21 to 31) in the sub-set 222C to this blank block corresponding to the position of the sub-set 212B (for example, the 10th to the 20), copy the data of the sub-set 212C of the block 212 (for example, the subsequent pages from page 21) to the corresponding position of the blank block (for example, the subsequent pages from the 21st page), erase the block 212 and 222 turns them into blank blocks, cancels the mapping relationship between the block 222 and the block 212, and updates the type of the blank block so that it belongs to the parent block 210.

In addition, the block 223 may belong to the sub-block 220, but the block 223 need not be mapped to any parent block. For example, in the case of insufficient hardware resources (such as buffers) of the main device 50, the main device 50 can cut continuous data (such as video data) into a large number of small pieces of data, and can send them separately These small pieces of information. In this way, these small fragments of data transmitted from the main device 50 to the memory device 100 correspond to the aforementioned continuous data. The memory controller 110 can respectively write at least a part of the data of these small fragments to the sub-sets 223A, 223B, 223C... of the block 223 to store the written data in the sub-sets 223A, 223B, 223C... Each of them may include at least one page (for example, one or more pages), and when the block 223 is full, the memory controller 110 may update the type of the block 223 so that it belongs to the parent block 210, but The present invention is not limited to this. For example, the size of each small fragment of the data of these small fragments may be equal to 32 KB (kilobyte), and the size of each page in the block 223 may be equal to 16 KB. For another example, the size of each small fragment of the data of these small fragments may be equal to 16 KB, and the size of each page in the block 223 may be equal to 16 KB. For another example, the size of each small fragment of the data of these small fragments may be equal to 8 KB, and the size of each page in the block 223 may be equal to 16 KB. According to some embodiments, the memory controller 110 may buffer the received small fragments so that each of the subsets 223A, 223B, 223C... may include one page, but the invention is not limited to this.

According to some embodiments, the size of the buffer area 116A in the buffer memory 116 may be greater than or equal to the amount of data written into the non-volatile memory 120 at one time. When the main device 50 writes the aforementioned continuous data (such as the video data, the data length can be very long) into the memory device 100, the memory controller 110 can use a series of sub-blocks that are not mapped to any parent block ( Such as sub-block 223) to store and receive the multiple small pieces of data to avoid extra work, such as garbage collection operations. When needed (for example, the main device writes data that does not fill a page and needs to fill in the beginning or end), the memory controller 110 can use a cache block (such as any one of the cache blocks 230) to perform data Write.

III. Data writing management

Regarding the manufacture of non-volatile memory 120, there are a variety of technologies available, such as: 2D/Planar NAND Flash (2D/Planar NAND Flash) technology in which memory cells are arranged in a single layer; and memory cells are arranged in multiple vertical stacks. Three-dimensional NAND flash (3D NAND Flash) technology. According to some embodiments, the non-volatile memory 120 can be implemented as a planar NAND flash structure with memory cells arranged in a single layer. According to some embodiments, the non-volatile memory 120 can be implemented as a three-dimensional NAND flash structure with multiple memory cells stacked vertically. For example, based on certain design concepts, the non-volatile memory 120 can be designed such that when the multi-level cell writing mode is used to write information, two pages of data must be written at a time, such as even pages plus odd pages (even pages). page plus odd page); this means that the size of buffer 116A has doubled the original requirement. Assuming sufficient hardware resources (for example, the total storage capacity of the buffer memory 116 is large enough), the allowable size of the buffer 116A is more than two pages. In this situation, when the main device 50 writes the above-mentioned continuous data (such as the video data, whose data length can be very long) into the memory device 100, the microprocessor 112 can dynamically monitor the data in the buffer 116A , Such as the data of one or more of the plurality of small fragments, to accurately determine whether the data of the one or more small fragments should be written into a cache block or a sub-block. For example, when the data of the one or more small segments is subsequent data of the data of the previous small segment, the microprocessor 112 can accurately determine that the data of the one or more small segments should be written to the sub-block. Therefore, the memory controller 110 can use the series of sub-blocks (such as the sub-block 223) to store and receive the plurality of small fragments of data, and the memory device 100 can have excellent writing performance.

It is assumed that insufficient hardware resources (for example, the total storage capacity of the buffer memory 116 is limited) makes the size of the buffer 116A equal to the size of one page. In this situation, when the main device 50 writes the aforementioned continuous data (such as the recorded data) into the memory device 100, the microprocessor 112 may not have enough information to accurately determine the one or more small pieces of data Whether it should be written to a cache block or a sub-block, which may invalidate the above-mentioned mechanism of using the series of sub-blocks to store and receive the multiple small fragments of data (for example, the memory controller 110 may not be able to avoid Extra work, such as garbage collection operations), in which write performance may be reduced. Figure 3 is a schematic diagram of a method for writing management in a memory device according to an embodiment of the present invention, where the method can be applied to the memory device 100 and can be applied to the controller such as a memory controller 110. The main device 50 can be implemented as any one of a video recorder, a driving recorder, etc., but the present invention is not limited thereto. Due to the limited buffer space of video recorders, driving recorders, etc., the above-mentioned continuous data (such as the video data) can be cut, especially into many small pieces of data mentioned above. For example: the size of the recorded data reaches 1 MB (megabyte; megabytes) or more, and the size of each small fragment of these small fragments of data can be equal to 8 KB, and any one of the series of sub-blocks The size of each page in a sub-block (such as block 223) may be equal to 16 KB.

According to this embodiment, when the data of the double page is full, through a tail process, the memory controller 110 can make the data enter a double page of a sub-block, and use dummy data or Other data is added or filled into an odd page of the sub-block, such as the next page of the even page, to complete the double-page writing of the sub-block, but the invention is not limited to this. The data from a small fragment under the main device 50 originally needed to enter the odd page of the sub-block, but now it can only be written into a cache block, because the odd page of the sub-block has just passed through The ending program is used. Therefore, the aforementioned mechanism of using the series of sub-blocks to store and receive the data of the multiple small fragments fails. In the case of long-term recording, the memory controller 110 may not be able to avoid additional tasks, such as garbage collection operations, in which the writing performance may be reduced.

For ease of understanding, the data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} can be used as an example of four consecutive small fragments of the above-mentioned many small fragments of data, data {1st-8K(1) , 2nd-8K(1), 3rd-8K(1), 4th-8K(1)} respectively represent data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} located in the memory controller 110 ( Especially the buffer version in the buffer 116A), and the data {1st-8K(2), 2nd-8K(2), 3rd-8K(2), 4th-8K(2)} respectively represent the data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} are written versions in non-volatile memory 120, where the symbol "X" can stand for "Don't Care". The main device 50 sequentially executes steps {S01, S02, S03, S04} to write data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} to the memory device 100 respectively. For example, the memory controller 110 may receive a series of data such as data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} from the host device 50 to obtain data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} take out a part as even page data, and take out another part from the data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} as odd page data, but the present invention does not take this as limit. Assuming that the data {1st-8K, 2nd-8K} and the data {3rd-8K, 4th-8K} are expected to be written into an even page and an odd page of a block in the non-volatile memory 120 respectively ( For example, the data on page 0 and the data on page 1); this means that the data {1st-8K, 2nd-8K} and the data {3rd-8K, 4th-8K} can be regarded as even page data and odd page data, respectively. {1st-8K(1), 2nd-8K(1)} and data {3rd-8K(1), 4th-8K(1)} can be regarded as even page data and odd page data respectively, and data {1st-8K (2), 2nd-8K(2)} and data {3rd-8K(2), 4th-8K(2)} can be regarded as even page data and odd page data respectively (labeled as "even page" and "odd page" respectively Page" for brevity).

In response to step S01 of the host device 50, the data 1st-8K can be stored in the first part of the buffer 116A as the data 1st-8K(1), and can be written to a page of block 231 belonging to the cache block 230 As the data 1st-8K(2), the size of the first part is equal to 8 KB. For example, through the ending process, the memory controller 110 can combine the data 1st-8K(1) with 8 KB of dummy data (or other data), and write the combined data to the page of the block 231. In response to step S02 of the host device 50, the data 2nd-8K can be stored in the second part of the buffer 116A as the data 2nd-8K(1) for being written to the non-volatile memory 120 as the data 2nd-8K( 2), where the size of the second part is equal to 8 KB. In this situation, the memory controller 110 has received even page data in the buffer 116A, such as data {1st-8K(1), 2nd-8K(1)}. The memory controller 110 may have detected that the main device 50 has suspended or stopped data transmission (for example: after receiving data 2nd-8K(1) from the main device 50, the memory controller 110 may have received a stop from the main device 50 Command), and at this moment, it is impossible to determine whether the next data and data {1st-8K(1), 2nd-8K(1)} belong to the same series of data, of which data {1st-8K(1), 2nd-8K( 1)} The buffer zone 116A is full. The memory controller 110 can combine the data 1st-8K(2) (obtained from the page of block 231) and the data 2nd-8K(1) (obtained from the buffer 116A) to use the combined data as It is expected to write data {1st-8K(2), 2nd-8K(2)} of an even page (for example, page 0) belonging to the block 223 of the sub-block 220. For example: through this ending procedure, the memory controller 110 can combine data {1st-8K(2), 2nd-8K(2)} and 16 KB fake data (or other data) to combine data {1st-8K (2), 2nd-8K(2)} and the above-mentioned 16 KB fake data are written into the even page of block 223 (for example, page 0) and the next page, such as an odd page of block 223 (for example, Page 1) to complete a double-page write operation for this sub-block. In response to step S03 of the host device 50, the first part of the data 3rd-8K can be stored in the buffer 116A as the data 3rd-8K(1), and can be written to another page of the block 231 as the data 3rd-8K (2). For example, through the ending process, the memory controller 110 can combine data 3rd-8K(1) with 8 KB of dummy data (or other data), and write the combined data to the other part of block 231 page. In response to step S04 of the host device 50, the data 4th-8K can be stored in the second part of the buffer 116A as the data 4th-8K(1) for writing to the non-volatile memory 120 as the data 4th-8K (2). In this situation, the memory controller 110 has received odd pages of data in the buffer 116A, such as data {3rd-8K(1), 4th-8K(1)}. Since the odd page (such as page 1) of block 223 has been used to store the 16 KB fake data (or other data), the data {3rd-8K(2), 4th-8K(2)} is It is stored in block 231 instead of block 223. For example, the memory controller 110 can combine data 3rd-8K(2) (obtained from the other page of block 231) and data 4th-8K(1) (obtained from buffer 116A) to combine all The combined data is written into another page of the block 231 as data {3rd-8K(2), 4th-8K(2)}. After the above operation, because valid even page data (such as data {1st-8K(2), 2nd-8K(2)}) is located in block 223 belonging to sub-block 220, and valid odd page data (such as The data {3rd-8K(2), 4th-8K(2)}) is located in the block 231 belonging to the cache block 230, so the memory controller 110 may not be able to avoid extra work, such as garbage collection operations, but the present invention does not Limited to this.

According to some embodiments, when the total storage capacity of the buffer memory 116 is limited (for example, the size of the buffer 116A is equal to the size of a page), the memory controller 110 can adjust (for example, suspend, cancel, and/or modify ) Part of the operating instructions for the non-volatile memory 120 to avoid valid even page data (such as data {1st-8K(2), 2nd-8K(2)}) and valid odd page data (such as data {3rd -8K(2), 4th-8K(2)}) are distributed in different types of blocks; and the memory controller 110 can obtain enough information to accurately determine whether the data of the one or more small fragments It should be written to a cache block or a sub-block to ensure that the above-mentioned mechanism of using the series of sub-blocks to store and receive the multiple small fragments of data is effective. For example, in the case that the manufacturer of the non-volatile memory 120 does not provide an operation command for controlling an internal buffer 121 in the non-volatile memory 120, the memory controller 110 can use the command Adjust to properly utilize the internal buffer 121 in the non-volatile memory 120, especially the data can be transferred to the non-volatile memory 120 first to temporarily store the data in the internal buffer 121. As long as the memory controller 110 does not send a confirmation command to the non-volatile memory 120, the non-volatile memory 120 will not execute programming. Therefore, before sending the confirmation command to the non-volatile memory 120, the memory controller 110 The target writing position of one of the data can be changed, for example, it can be dynamically determined whether to change the target writing position from the block 223 belonging to the sub-block 220 to the block 231 belonging to the cache block 230. In addition, in order to avoid the problem of unreadable data (such as the problem that the randomized version of the data cannot be correctly derandomized) caused by changing the target writing position, the memory controller 110 can temporarily change the buffer memory The purpose of at least a part of the small remaining storage space in the body 116 (for example, part or all of the remaining storage space) is used to arrange a data exchange area 116B (which may only have 2 KB size or smaller), and the random seed can be modified through data exchange between the data exchange area 116B and the internal buffer 121, especially for the data to perform multiple random data out operations Operate with multiple random data in to correct the random seed. Assuming that the target writing location was originally a first location in a first block (for example, block 223), and before the data is transferred to the non-volatile memory 120, the memory controller 110 has already performed a A random seed randomizes the data to convert it into a first set of randomized data as a randomized version of the data, wherein the first random seed corresponds to the first block (for example, block 223) The first position. When it is determined to change the target writing location to a second location in a second block (for example, block 231), the multiple random data output operations and the multiple random data input operations are performed in turn, and memory control The device 110 may de-randomize the first set of randomized data according to the first random seed to retrieve the data, and may randomize the data according to a second random seed to convert it into a second set of randomized data. As another randomized version of the data, the second random seed corresponds to the second position in the second block (for example, block 231). Thus, in the internal buffer 121, the first set of randomized data becomes the second set of randomized data. In this situation, the memory controller 110 can send the confirmation command to the non-volatile memory 120 to trigger the non-volatile memory 120 to program the second set of randomized data to the second position in the block 231. Similarly, when necessary, the first block and the second block can be changed. For example, the first block and the second block can represent the block 231 and the block 223 respectively. Therefore, the memory controller 110 can arbitrarily change the target writing position before sending the confirmation command to the non-volatile memory 120 without the aforementioned data unreadable problem.

Since the memory controller 110 can arbitrarily change the target writing position without the aforementioned data unreadable problem, the memory controller 110 can avoid the embodiment shown in Figure 3 by changing the target writing position The problem. Figure 4 is a schematic diagram of a method for writing management in a memory device according to another embodiment of the present invention, where the method can be applied to the memory device 100 and can be applied to the controller such as memory control器110. In response to step S01 of the host device 50, the first part of the data 1st-8K can be stored in the buffer 116A as the data 1st-8K(1), and can be written to a block 231 belonging to the cache block 230 Page as data 1st-8K(2). For example, through the ending process, the memory controller 110 can combine the data 1st-8K(1) with 8 KB of dummy data (or other data), and write the combined data to the page of the block 231. In response to step S02 of the host device 50, the data 2nd-8K can be stored in the second part of the buffer 116A as the data 2nd-8K(1) for being written to the non-volatile memory 120 as the data 2nd-8K (2). For example: through a header process, the memory controller 110 can combine the data 1st-8K(2) (obtained from the page of block 231) and the data 2nd-8K (obtained from the buffer 116A) (1) At least one data write command is issued to indicate that the memory controller 110 intends to write the combined data to an even page of the block 223 of the sub-block 220 in the non-volatile memory 120 as data {1st-8K(2), 2nd-8K(2)}, but avoid sending the confirmation command to the non-volatile memory 120 immediately, where the confirmation command can trigger the non-volatile memory 120 to perform at least one data write instruction. The memory controller 110 may have detected that the main device 50 has suspended or stopped data transmission (for example: after receiving data 2nd-8K(1) from the main device 50, the memory controller 110 may have received a stop from the main device 50 Command), and at this moment, it is impossible to determine whether the next data and data {1st-8K(1), 2nd-8K(1)} belong to the same series of data, of which data {1st-8K(1), 2nd-8K( 1)} The buffer zone 116A is full. The memory controller 110 may first transfer the data {1st-8K(2), 2nd-8K(2)} (especially, the data {1st-8K(2), 2nd-8K(2)} to the corresponding multiple The randomized version before the random data output operation and the corresponding multiple random data input operations; this randomized version can be used as an example of the first set of randomized data) is transferred to the non-volatile memory 120 and temporarily stored in The internal buffer 121 can perform the corresponding multiple random data output operations and the corresponding multiple random data input operations in turn, so as to avoid the aforementioned data unreadable problem when changing the target writing position. For example: after changing the target writing position, the memory controller 110 can send the confirmation command to the non-volatile memory 120 to trigger the non-volatile memory 120 to store data {1st-8K(2), 2nd-8K (2)} (especially, the randomized version of the data {1st-8K(2), 2nd-8K(2)} after the corresponding multiple random data output operations and the corresponding multiple random data input operations ; This randomized version can be used as an example of the second set of randomized data) to be programmed into block 231. In this way, when the data of the next page (such as data {3rd-8K(1), 4th-8K(1)}) has been completely received in the buffer 116A, the memory controller 110 can store the data belonging to the same series In block 223, the problem of irrelevant data (such as the above-mentioned fake data of 16 KB or other data) occupying block 223 will not be encountered.

In addition, in response to step S03 of the host device 50, the first part of the data 3rd-8K can be stored in the buffer 116A as the data 3rd-8K(1), and can be written to another page of the block 231 as the data 3rd -8K(2). For example, through the ending process, the memory controller 110 can combine data 3rd-8K(1) with 8 KB of dummy data (or other data), and write the combined data to the other part of block 231 page. In response to step S04 of the host device 50, the data 4th-8K can be stored in the second part of the buffer 116A as the data 4th-8K(1) for writing to the non-volatile memory 120 as the data 4th-8K (2). For example: through the initial procedure, the memory controller 110 can try to combine the data 3rd-8K(2) (obtained from the page of block 231) and the data 4th-8K(1) (obtained from the buffer 116A) , And the detected data {1st-8K(2), 2nd-8K(2), 3rd-8K(2), 4th-8K(2)} belongs to the same series of data, and the confirmation command has not been issued to non-volatile The memory 120, and the data {3rd-8K(1), 4th-8K(1)} has filled up the buffer 116A. For example: for even page data, such as data {1st-8K(2), 2nd-8K(2)} in block 231, the memory controller 110 can perform multiple random data output operations and multiple random data input operations , To adjust the random seed of the randomized version of the data {1st-8K(2), 2nd-8K(2)} to an even page corresponding to block 223 (for example, page 0), so that it stays in the internal buffer器121中. Thus, the memory controller 110 can write data {1st-8K(2), 2nd-8K(2), 3rd-8K(2), 4th-8K(2)} in the double page of block 223, where The data {1st-8K(2), 2nd-8K(2)} is written into the even page (such as page 0) of block 223, and the data {3rd-8K(2), 4th-8K(2)} It is written to the next page (for example, page 1) of the even page, but the present invention is not limited to this.

After the above operation, the data belonging to the small fragments of the same series of data are continuously stored in the block 223 of the sub-block 220 (for example: valid even page data (such as data {1st-8K(2), 2nd -8K(2)}) and valid odd-page data (such as data {3rd-8K(2), 4th-8K(2)}) located in two consecutive pages in block 223 of sub-block 220), so memory The volume controller 110 can avoid extra tasks, such as garbage collection operations, and the memory device 100 can have excellent writing performance.

According to some embodiments, the size of the small fragment of data, the size of a page, the size of the buffer zone 116A, and/or the size of the data exchange area 116B can be changed. For ease of understanding, the above-mentioned at least one data writing instruction may include a first group of instructions such as {0x80, Child_Addr(0), DATA(0), 0x11, 0x80, Child_Addr(1), DATA(1)}, and the The confirmation command can include the command {0x10}, which can be regarded as a confirmation write command, where 0x80 can represent the write command in the multi-level cell write mode, and can be regarded as a pre-announce data write A preview write command, Child_Addr(0) can represent the physical address of the even page of block 223 in plane 0, and DATA(0) can represent the data to be written (such as data 1st-8K(2)), 0x11 can represent a plane switching command, Child_Addr(1) can represent the physical address of the even page of block 223 in plane 1, and DATA(1) can represent the data to be written (such as data 2nd-8K(1)), But the present invention is not limited to this. Before the confirmation command (such as command {0x10}) is issued, the data {DATA(0), DATA(1)} (especially its randomized version) can stay in the internal buffer, and the memory controller 110 The target write location can be changed by changing the address so that the data {DATA(0), DATA(1)} is written to block 231 (not block 223) to avoid irrelevant data (such as 16 above) KB size fake data or other data) occupy block 223. For example: a second set of commands corresponding to a single-stage cell write operation, such as commands {0xDA, 0x85, Cache_Addr(0), 0x11, 0x85, Cache_Addr(1)}, can be included in the above at least one data write command, where 0xDA can represent switching to the single-level cell write mode, 0x85 can represent the write command in the single-level cell write mode, and can be regarded as a preview write command used to predict data writing, Cache_Addr(0) It can represent the physical address of a page in block 231 on plane 0, and Cache_Addr(1) can represent the physical address of this page in block 231 on plane 1. The memory controller 110 can issue the first set of commands such as commands {0x80, Child_Addr(0), DATA(0), 0x11, 0x80, Child_Addr(1), DATA(1)}, the second set of commands such as commands { 0xDA, 0x85, Cache_Addr(0), 0x11, 0x85, Cache_Addr(1)}, and the confirmation command (such as the command {0x10}) to change/update the address in the single-stage cell write mode (by changing the bit Address {Child_Addr(0), Child_Addr(1)} is changed/updated to address {Cache_Addr(0), Cache_Addr(1)}) to write data {DATA(0), DATA(1)} to block 231, But the present invention is not limited to this. According to some embodiments, the memory controller 110 can set the first set of commands such as commands {0x80, Child_Addr(0), DATA(0), 0x11, 0x80, Child_Addr(1), DATA(1)} and the first set of commands Insert at least one set of additional instructions between two sets of instructions such as instructions {0xDA, 0x85, Cache_Addr(0), 0x11, 0x85, Cache_Addr(1)}, such as instructions {0x00, 0x05, 0xE0} and {0x85} to pass the above At least one set of additional commands adjust the random seed to ensure the correctness and/or readability of the data written in the non-volatile memory 120, especially to avoid randomizing/de-randomizing operations The mechanism is affected by the change/update of the address, but the invention is not limited to this. For example, the memory controller 110 can execute the commands {0x00, 0x05, 0xE0} and {0x85} one or more times for even pages to perform copy-back reading and randomized data writing to change the internal The random seed that the randomized data in the buffer 121 should use. Among the above at least one set of additional commands, the commands {0x00, 0x05, 0xE0} and {0x85} can be regarded as random data output commands and random data input commands, respectively, for performing a random data output operation and a random data input operation. Thus, the memory controller 110 can execute the commands {0x00, 0x05, 0xE0} and {0x85} multiple times to modify the random seed by alternately performing multiple random data output operations and multiple random data input operations. For example: when the data exchange area has a size of 2 KB, the memory controller 110 can execute the commands {0x00, 0x05, 0xE0} and {0x85} four times for the randomized data of 8 KB size to modify its random seed.

FIG. 5 shows the workflow 300 of the method shown in FIG. 4 in an embodiment. According to this embodiment, the memory controller 110 can receive the series of data such as data {1st-8K, 2nd-8K, 3rd-8K, 4th-8K} from the host device 50, and take a part of the series of data as even-page data And take out another part from the series of data as odd page data, but the invention is not limited to this.

In step S30, the memory controller 110 can write the first partial data (such as data 1st-8K) of the even page data to the non-volatile memory 120 (for example, belonging to the cache block 230). Block 231).

In step S32, the memory controller 110 may transmit a first group of commands without the confirmation command (such as command {0x10}) (for example, the first group of commands mentioned above, such as the command {0x80, Child_Addr(0) ), DATA(0), 0x11, 0x80, Child_Addr(1), DATA(1)}) to the non-volatile memory 120 to store the first partial data (such as data 1st-8K) and the even page data The second partial data (such as data 2nd-8K) is written into the internal buffer 121 in the non-volatile memory 120, wherein the confirmation command can be used to trigger the non-volatile memory 120 to execute at least one command, such as the aforementioned at least one data Write at least a part (such as part or all) of the command to write at least one non-volatile memory device in the non-volatile memory 120 (such as non-volatile memory devices 122-1, 122-2, ... and 122). -N at least one) to perform programming operations. For example, the first set of commands may indicate that the non-volatile memory 120 should write the first partial data and the second partial data to a sub-area of the non-volatile memory 120 through the multi-level cell writing mode A block, such as the block 223 belonging to the sub-block 220.

In step S34, for the even page data (such as the first partial data and the second partial data), the memory controller 110 may send at least one set of additional commands (for example, the aforementioned at least one set of additional commands, such as commands {0x00, 0x05, 0xE0} and {0x85}) to the non-volatile memory 120 to adjust the random seed through the at least one set of additional commands to ensure the correctness of the written data in the non-volatile memory 120 and/ Or readability. According to this embodiment, through data exchange between the data exchange area 116B and the internal buffer 121, the memory controller 110 can modify the random seed of at least a part of the data in the internal buffer 121.

In step S36, the memory controller 110 may transmit a second set of commands (for example, the above-mentioned second set of commands, such as commands {0xDA, 0x85, Cache_Addr(0), 0x11, 0x85, Cache_Addr(1)}) And the confirmation command (such as command {0x10}) to the non-volatile memory 120 to write the first partial data and the second partial data to a cache block of the non-volatile memory 120, such as The block 231 belongs to the cache block 230. For example, the second set of commands may indicate that the non-volatile memory 120 should write the first partial data and the second partial data to the cache block through the single-stage cell write mode. According to this embodiment, the at least one command may include the second set of commands, and the confirmation command triggers the non-volatile memory 120 to execute the second set of commands, wherein the second set of commands can replace at least one of the first set of commands A part (for example, a part or all), and can be regarded as an update command of the first group of commands. For example, the memory controller 110 does not need to retransmit certain data (such as DATA(0) and DATA(1)) to the non-volatile memory 120, but the invention is not limited to this. In addition, the first group of instructions and the second group of instructions respectively correspond to different target writing positions. For example: by transmitting the second set of commands, the memory controller 110 can replace a first target write location (such as the first location) specified by the first set of commands with one specified by the second set of commands The second target writing position (such as the second position). The memory controller 110 can modify the random seed of the at least part of the data in the internal buffer 121 to match the second target writing position.

In step S38, the memory controller 110 can write the third partial data (such as data 3rd-8K) in the odd page data to the non-volatile memory 120 (for example, a block belonging to the cache block 230). 231).

In step S40, the memory controller 110 can check whether the odd page data has been completely received, especially the third partial data (such as data 3rd-8K) and the fourth partial data in the odd page data (Such as data 4th-8K) have been received, and whether the odd page data has been completely received can correspond to the third partial data (such as data 3rd-8K) and the fourth partial data (such as data 4th-8K) have all been received. For example, the memory controller 110 can check whether the fourth partial data (such as data 4th-8K) has been received to determine whether the odd page data has been received completely. When the odd page data has been completely received (for example, the fourth partial data (such as data 4th-8K) has been received), go to step S42; otherwise, the workflow 300 ends, but the present invention is not limited to this .

In step S42, for the even page data (such as the first partial data and the second partial data), the memory controller 110 may send the at least one set of additional commands (such as commands {0x00, 0x05, 0xE0} and { 0x85}) to the non-volatile memory 120 to adjust the random seed through the at least one additional set of commands to ensure the correctness and/or readability of the data written in the non-volatile memory 120.

In step S44, the memory controller 110 may write the first partial data (such as data 1st-8K) and the second partial data (such as data 2nd-8K) into the sub-block (such as block 223) And write the third partial data (such as data 3rd-8K) and the fourth partial data (such as data 4th-8K) to an odd page of the sub-block (such as block 223), The odd page is the next page of the even page.

Due to valid even page data (such as data {1st-8K(2), 2nd-8K(2)}) and valid odd page data (such as data {3rd-8K(2), 4th-8K(2)}) Since the two consecutive pages are located in the block 223, the memory controller 110 can have excellent write performance and can avoid additional tasks (such as garbage collection operations). For the sake of brevity, the content of this embodiment similar to the foregoing embodiment will not be repeated here. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

50‧‧‧Main unit 100‧‧‧Memory device 110‧‧‧Memory Controller 112‧‧‧Microprocessor 112C‧‧‧Code 112M‧‧‧Read only memory 114‧‧‧Control logic circuit 116‧‧‧Buffer memory 116A‧‧‧Buffer 116B‧‧‧Data Exchange Area 118‧‧‧Transmission Interface Circuit 120‧‧‧Non-volatile memory 121‧‧‧Internal buffer 122-1, 122-2, …, 122-N‧‧‧Non-volatile memory components 210‧‧‧Mother block 220‧‧‧subblock 230‧‧‧Cache block 211, 212, …,221, 222, 223, …,231, 232, …‧‧‧block 211A, 211B, 211C,212A, 212B, 212C,221A, 221B, 221C,222A, 222B, 222C, 1st-8K, 1st-8K(1), 1st-8K(2),2nd-8K, 2nd-8K(1), 2nd-8K(2),3rd-8K, 3rd-8K(1), 3rd-8K (2),4th-8K, 4th-8K(1), 4th-8K(2)‧‧‧Data S01, S02, S03, S04, S30, S32, S34, S36, S38, S40, S42, S44‧‧‧Step

FIG. 1 is a schematic diagram of a memory device and a host device according to an embodiment of the invention. Fig. 2 shows a block management scheme of the memory device shown in Fig. 1 in an embodiment. FIG. 3 is a schematic diagram of a method for writing management in a memory device according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a method for writing management in a memory device according to another embodiment of the present invention. Figure 5 shows the workflow of the method shown in Figure 4 in an embodiment.

116A‧‧‧Buffer

Block 223,231‧‧‧

1st-8K,1st-8K(1),1st-8K(2),2nd-8K,2nd-8K(1),2nd-8K(2),3rd-8K,3rd-8K(1),3rd-8K (2),4th-8K,4th-8K(1),4th-8K(2)‧‧‧Data

S01,S02,S03,S04‧‧‧Step

Claims (10)

A method for writing management in a memory device, the memory device including a non-volatile memory (non-volatile memory, NV memory), the non-volatile memory including one or more non-volatile memory Element (NV memory element), any one of the one or more non-volatile memory elements includes multiple blocks, and any one of the multiple blocks includes multiple pages, the method includes : Use a buffer in a buffer memory of the memory device to buffer a series of data received from a host device, wherein a first set of fragments and a second set of fragments in the series of data are used respectively To be used as even page data and odd page data; Writing first partial (partial) data in the even page data to the non-volatile memory, wherein the first partial data includes at least one first segment in the first set of segments; Send a first set of commands to the non-volatile memory to write the first partial data and the second partial data of the even page data into an internal buffer in the non-volatile memory, and Does not trigger the non-volatile memory to perform any programming operation on any non-volatile memory element in the non-volatile memory, wherein the second partial data includes at least one second segment in the first set of segments; A second set of commands and a confirmation command are sent to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the confirmation command triggers the non-volatile memory The volatile memory executes the second set of commands to perform a corresponding programming operation on at least one non-volatile memory element in the non-volatile memory; Writing the third partial data in the odd page data to the non-volatile memory, wherein the third partial data includes at least one third segment in the second set of segments; and Write the first partial data and the second partial data to an even page of another block in the non-volatile memory, and write the third partial data and the fourth partial data of the odd page data Enter an odd page of the other block, where the fourth partial data includes at least one fourth segment in the second group of segments. The method described in claim 1, wherein in the series of data, the second set of fragments are subsequent fragments of the first set of fragments. The method according to claim 1, wherein in the first set of fragments, the at least one second fragment is at least one subsequent fragment of the at least one first fragment; and in the second set of fragments, the The at least one fourth segment is at least one subsequent segment of the at least one third segment. According to the method described in claim 1, wherein the size of each of the first group of segments and the second group of segments is not greater than half of the size of the buffer. The method described in item 1 of the scope of patent application, wherein the block and the other block are of different types. The method described in item 5 of the scope of patent application, wherein the block represents a cache block, and the other block represents a child block. In the method described in claim 1, wherein a target writing location specified by the first set of instructions is located in the other block. The method described in claim 1, wherein the memory device includes a controller located outside the non-volatile memory, and the controller includes the buffer memory, wherein the buffer memory in the buffer memory The size is equal to the size of a page. A memory device including: A non-volatile memory (NV memory) is used to store information, where the non-volatile memory includes one or more non-volatile memory elements (NV memory element), and the one or more non-volatile memory elements Any one of the volatile memory elements includes multiple blocks, and any one of the multiple blocks includes multiple pages; and A controller coupled to the non-volatile memory for controlling the operation of the memory device, wherein the controller includes: A buffer memory for temporarily storing information; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the controller, among them: The controller uses a buffer in the buffer memory to buffer a series of data received from the host device, wherein a first set of fragments and a second set of fragments in the series of data are respectively used as even page data And odd page information; The controller writes first partial (partial) data in the even page data to the non-volatile memory, wherein the first partial data includes at least one first segment in the first set of segments; The controller sends a first set of commands to the non-volatile memory to write the first partial data and the second partial data in the even page data into an internal buffer in the non-volatile memory. ) Without triggering the non-volatile memory to perform any programming operation on any non-volatile memory element in the non-volatile memory, wherein the second partial data includes at least one of the first set of segments Two fragments The controller sends a second set of commands and a confirmation command to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the confirmation The instruction triggers the non-volatile memory to execute the second set of instructions to perform a corresponding programming operation on at least one non-volatile memory element in the non-volatile memory; The controller writes the third partial data in the odd page data to the non-volatile memory, wherein the third partial data includes at least one third segment in the second set of segments; and The controller writes the first partial data and the second partial data to an even page of another block in the non-volatile memory, and the third partial data and the fourth of the odd page data The partial data is written to an odd page of the other block, wherein the fourth partial data includes at least one fourth segment in the second group of segments. A controller for a memory device. The memory device includes the controller and a non-volatile memory (NV memory). The non-volatile memory includes one or more non-volatile memory devices (NV memory). element), any one of the one or more non-volatile memory elements includes multiple blocks, any one of the multiple blocks includes multiple pages, and the controller includes: A buffer memory for temporarily storing information; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the controller, among them: The controller uses a buffer in the buffer memory to buffer a series of data received from the host device, wherein a first set of fragments and a second set of fragments in the series of data are respectively used as even page data And odd page information; The controller writes first partial (partial) data in the even page data to the non-volatile memory, wherein the first partial data includes at least one first segment in the first set of segments; The controller sends a first set of commands to the non-volatile memory to write the first partial data and the second partial data in the even page data into an internal buffer in the non-volatile memory. ) Without triggering the non-volatile memory to perform any programming operation on any non-volatile memory element in the non-volatile memory, wherein the second partial data includes at least one of the first set of segments Two fragments The controller sends a second set of commands and a confirmation command to the non-volatile memory to write the first partial data and the second partial data to a block in the non-volatile memory, wherein the confirmation The instruction triggers the non-volatile memory to execute the second set of instructions to perform a corresponding programming operation on at least one non-volatile memory element in the non-volatile memory; The controller writes the third partial data in the odd page data to the non-volatile memory, wherein the third partial data includes at least one third segment in the second set of segments; and The controller writes the first partial data and the second partial data to an even page of another block in the non-volatile memory, and the third partial data and the fourth of the odd page data The partial data is written to an odd page of the other block, wherein the fourth partial data includes at least one fourth segment in the second group of segments.

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