TWI709122B - Timing controller and display device comprising the same - Google Patents

Abstract

Provided are a timing controller capable of compensating for Mura defects of a display panel with high quality while reducing the size of a memory required for storing look-up table (LUT) data and a display device comprising the same. The timing controller includes a memory controller which reads compressed LUT data from an external memory, a decompressor which decompresses the compressed LUT data received from the memory controller to generate original LUT data before the compression, a line buffer which temporarily stores the original LUT data received from the decompressor, and an image signal processor which compensates for Mura defects of input image signal data by using the original LUT data stored in the line buffer.

Description

Timing controller and display device containing the timing controller

The invention relates to a timing controller and a display device including the timing controller.

The display device usually includes a display panel and a driving part of the display panel. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The driving part of the display panel includes a timing controller, a gate driver and a source driver.

Generally, the pixel includes multiple transistors, storage capacitors, and organic light-emitting elements. The brightness difference between the pixels caused by the threshold voltage distribution of the transistor has the problem of generating MURA defects (MURA defects; hereinafter referred to as MURA defects). The panel that produces this MURA defect is called MURA panel (MURA panel).

In this case, in order to compensate for the MURA defect, a look-up table (Look Up Table; hereinafter referred to as LUT) can be used. However, the resolution of the display panel has recently become higher. As the number of bits used by the LUT increases, the size of the LUT also increases, which has the problem of requiring a larger memory capacity to store the LUT. Moreover, in order to reduce the overall size of the LUT, when using one LUT data per specific unit pixel, There is a problem of reducing the quality of compensation for trace defects.

The problem to be solved by the present invention is to provide a timing controller that reduces the size of the memory required for storing LUT data, but can compensate for the MURA defect of the display panel with high quality.

Another problem to be solved by the present invention is to provide a display device that can reduce the size of the memory required for storing LUT data, but can compensate the MURA defect of the display panel with high quality.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems that have not been mentioned will be clearly understood by those skilled in the art from the following description.

The aspect of the timing controller of the present invention for solving the problem is to include: a memory controller that reads compressed LUT data from an external memory; decompresses the compression received from the memory controller LUT data, and a decompressor that generates original LUT data before compression; a row buffer that temporarily stores the original LUT data received from the decompressor; and uses the data stored in the row buffer The original LUT data is an image signal processing unit that compensates for MURA defects of the input image signal data.

In some embodiments of the present invention, the image signal processing unit may include: reading the original LUT data from the column buffer, and receiving from an external device After the image signal data, the MURA controller (De-MURA controller) that synchronizes the original LUT data and the image signal data; and receives the synchronized original from the MURA controller LUT data and the image signal, and using the original LUT data to eliminate the MURA defect contained in the image signal, thereby generating a de-MURA core of compensated image signal data .

In some embodiments of the present invention, the MURA defect may include non-uniform contrast, luminous, or brightness values between image signals of adjacent pixels.

In some embodiments of the present invention, the decompressor uses a lossless decompression algorithm to generate the original LUT data from the compressed LUT data.

In some embodiments of the present invention, the lossless decompression algorithm may include a CTW, LZ77, or LZW decompression algorithm.

In some embodiments of the present invention, the image signal data includes data about N pixels (the N is a natural number), and the original LUT data may include compensation values corresponding to all the N pixels.

In some embodiments of the present invention, the image signal data includes data about L*M pixels (the L and M are natural numbers), and the original LUT data may include data corresponding to the L vertical lines The compensation value, and the compensation value corresponding to the M horizontal lines.

In some embodiments of the present invention, the image signal data includes data about N pixels (where N is a natural number), and the original LUT data can be calculated for every K unit pixels (where K is a ratio of The small natural number N) includes a compensation value.

In some embodiments of the present invention, the timing controller may be included in A semiconductor package without the external memory.

The point of view of the display device of the present invention for solving the problem is that it includes: a display panel; an external memory storing compressed LUT data; for multiple input images for uniformity testing, multiple outputs of the display panel are captured Image, and use the captured multiple output images as a basis to generate original LUT data equivalent to compensation data, and store the compressed LUT data in the external memory. And using the compressed LUT data stored in the external memory to compensate for MURA defects contained in the image signal data input from the outside, and provide the compensated image signal data to the display panel Timing controller.

In some embodiments of the present invention, the image capture device may include: a controller that applies the plurality of input images for uniformity testing to the display panel; and captures a plurality of outputs of the display panel Image camera; a processor that generates the original LUT data equivalent to compensation data based on the captured multiple output images; a compressor that compresses the original LUT data; and compresses the LUT The data is sent to the interface of the external memory.

In some embodiments of the present invention, the compressor uses CTW, LZ77, or LZW compression algorithms to compress the original LUT data.

In some embodiments of the present invention, the image capturing device may be included in the timing controller.

In some embodiments of the present invention, the image capture device may be included in a semiconductor package separate from the timing controller and the external memory.

In some embodiments of the present invention, the timing controller may include: a memory controller that reads compressed LUT data from the external memory; The compressed LUT data and the decompressor that generates the original LUT data before compression; the row buffer that temporarily stores the original LUT data received from the decompressor; and the use of all the data stored in the row buffer The original LUT data, the image signal processing unit that compensates the MURA defect of the input image signal data.

In some embodiments of the present invention, the decompressor uses an algorithm complementary to the compressor to process the original LUT data.

In some embodiments of the present invention, the timing controller may be included in a semiconductor package separate from the external memory and the image capture device.

Another aspect of the display device of the present invention for solving the above-mentioned problem is to include: a plurality of pixels respectively arranged in the intersection area of a plurality of gate lines and a plurality of data lines; and a gate driving the plurality of gate lines A source driver that drives the plurality of data lines; an external memory that stores compressed LUT data; and responds to image signal data and control signals input from the outside to control the gate driver and the source driver , And using the compressed LUT data stored in the external memory to compensate for the MURA defect contained in the input image signal data, and the timing of providing the compensated image signal data to the source driver Controller.

In some embodiments of the present invention, the timing controller may include: a memory controller that reads compressed LUT data from the external memory; decompresses the compressed LUT data, and generates the original LUT before compression A data decompressor; a row buffer that temporarily stores the original LUT data received from the decompressor; and a row buffer that uses the original LUT data stored in the row buffer to compensate the input image signal data MURA defect image signal processing unit.

In some embodiments of the present invention, it may further include: for a plurality of input images for uniformity testing, capturing a plurality of output images of each of the plurality of pixels, and Using the captured multiple output images as a basis, generating original LUT data equivalent to compensation data, and storing the compressed LUT data in the image capturing device of the external memory.

In some embodiments of the present invention, the image capturing device may include: a control unit that applies the plurality of uniformity test input images to the plurality of pixels; and captures information about each of the plurality of pixels Multiple output images of the camera; using the captured multiple output images as a basis to generate the original LUT data equivalent to the compensation data processor; compressing the original LUT data; compressing the The LUT data is sent to the interface of the external memory.

In some embodiments of the present invention, the timing controller may be included in a semiconductor package separate from the external memory.

Other specific matters of the present invention are included in the detailed description and drawings.

100: timing controller

110: Memory Controller

120: Decompressor

130: column buffer

150: Image signal processing department

100: timing controller

152: Go to MURA control department

154: Go to MURA processing department

160: Image capture device

161: Camera

162: processor

163: Compressor

164: Controller

165: Facial

166: internal memory

167: Bus

190: External memory

200: source driver

300: Gate driver

340: Second interface circuit

400: Voltage generator

500: The first interface circuit

1000: display device

1001: display device

1100: display panel

1201: display drive circuit

2000: display module

2100: display device

2110: display panel

2120: printed circuit board

2130: display driver chip

2200: Polarizing plate

2300: Touch panel

2301: Window glass

2400: Touch controller

3100: processor

3200: display device

3210: Panel

3220: drive circuit

3300: peripheral devices

3400: memory

3500: system bus

4000: display device

4100: mobile phone

4200: TV

4300: ATM

4400: elevator

4500: Automatic ticket vending machine

4600: portable multimedia player

4700: e-book reader

4800: navigation equipment

AVDD: voltage

CMD1: The first command

CNT1, CNT2: control signal

Cst: storage capacitor

DL1, DL2, DLk-1, DLk: data line

EXE: End signal

GL1, GL2, GLj-1, GLj: gate line

Idrv: current

PX: pixel

RGB: The first image signal data

RGB': 2nd image signal data

SSYNC1: the first synchronization signal

S210, S220, S230, S240, S250: steps of method flow chart

drv: Drive transistor

Tsw: switching transistor

VCI: power supply voltage

VDD: power supply voltage

Von: Voltage/gate turn-on voltage

Voff: voltage

VSS: voltage

FIG. 1 is a block diagram for explaining a display device according to an embodiment of the invention.

Fig. 2 is a block diagram for explaining the timing controller shown in Fig. 1.

FIG. 3 shows a block diagram of an embodiment of the image signal processing unit of FIG. 2.

4 is a block diagram for explaining a display device according to another embodiment of the invention.

FIG. 5 is a block diagram for explaining a display device according to another embodiment of the invention.

FIG. 6 shows a block diagram of an image capture device according to some embodiments of the invention.

FIG. 7 is a flowchart of an operation method of an image capture device according to some embodiments of the present invention Cheng Tu.

Fig. 8 is a diagram of a display module according to an embodiment of the present invention.

Fig. 9 is a diagram of a display system according to an embodiment of the present invention.

FIG. 10 is an application example diagram of a display device mounted on a variety of electronic products according to some embodiments of the present invention.

The advantages, features, and methods of the present invention will be clarified by the accompanying drawings and detailed embodiments described later. However, the present invention is not limited to the embodiments described here, and may be embodied in other different forms. On the contrary, the embodiments disclosed herein make the present invention more complete, and provide a complete idea of the present invention to those skilled in the art to which the present invention belongs. The present invention is defined by the scope of the claims. The same reference symbols denote the same elements throughout the specification.

The so-called "connected to" or "coupled to" an element (elements) and another element refers to the case of being directly connected to another element, or the case of intervening other elements during the connection. On the other hand, the so-called "directly connected to" or "directly coupled to" between one element and another element refers to a situation where no other element is intervened. The same reference symbols denote the same elements throughout the specification. "And/or" includes all the items involved and all combinations of more than one.

In order to describe various elements, elements and/or parts, although the first, second, etc. terms are used, it is obvious that these elements, elements and/or parts are not limited to these terms. These terms are only used to distinguish one element, element and/or part from other elements, elements and/or parts. Therefore, the first element, the first element, or The first part may be the second element, the second element, or the second part within the technical idea of the present invention.

The terms used in this specification are used to illustrate the embodiments, and are not intended to limit the present invention. The expression of the singular number includes the expression of the plural number when the context does not require special instructions. The elements, steps, actions and/or elements mentioned in terms of "comprises" or "comprising" used in the specification do not exclude more than one other element, step, action and/or element The presence or addition of.

In the absence of other definitions, all terms (including technical and scientific terms) used in the specification have the same meanings as understood by those skilled in the art to which the present invention belongs. Moreover, the terms defined in commonly used dictionaries shall not be interpreted as ideal or exaggerated meanings without special definitions.

Hereinafter, in conjunction with FIGS. 1 to 10, a timing controller according to some embodiments of the present invention and a display device including the timing controller will be described.

FIG. 1 is a block diagram for explaining a display device according to an embodiment of the invention.

1, a display device 1000 according to a first-line embodiment of the present invention may adopt any one of various display devices. For example, it can be an organic light emitting diode display (OLED), a liquid crystal display (LCD), a plasma display panel (DP) device, and electronic color rendering Display (Electrochromic Display, ECD), Digital Mirror Device (DMD), Actuated Mirror Device (AMD), Grating Light Valve (Grating Light) Valve, GLV), Plasma Display Panel (PDP) or Electro Luminescent Display (ELD). Hereinafter, the display panel is described with an organic light emitting panel as an example.

Specifically, the display device 1000 includes a display panel 1100 and a display driving circuit 1201.

The display panel 1100 includes: a plurality of gate lines GL1~GLj that transmit scan signals in a row direction; a plurality of data lines DL1~DLk that are arranged in a direction crossing the gate lines and transmit data signals in a column direction; and A plurality of pixels PX are arranged in an area where the polar lines GL1 to GLj and the data lines D1 to Dk intersect.

When a plurality of gate lines GL1~GLj are sequentially selected, a gray-scale voltage is applied to the pixel PX connected to the selected gate line through the plurality of data lines DL1~DLk.

Each pixel PX may include: a switching transistor Tsw, a driving transistor Tdrv, a storage capacitor Cst, and an organic light emitting diode. The gate line GL and the data line DL are connected to the gate and source of the switching transistor Tsw, and the drain and power supply voltage VDD of the switching transistor Tsw are connected to the gate and source terminals of the driving transistor Tdrv, respectively. The drain terminal of the crystal Tdrv is connected to the anode of the organic light emitting diode.

In this pixel structure, when the gate line GL is selected, the switching transistor Tsw is turned on, and the provided gray-scale voltage is applied to the gate terminal of the driving transistor Tdrv through the data line DL, according to the driving power voltage VDD and gray The voltage difference of the step voltage causes the driving current Idrv to flow through the organic light emitting diode to emit light, thereby completing the display operation.

The display driving circuit 1201 may include: a timing controller 100, a source driver 200, a gate driver 300, a voltage generator 400, a first interface circuit 500, a second interface circuit 340, and an external memory 190.

The timing controller 100 can be externally, for example, loaded with a display device The system host of 1000 receives the first image signal data RGB and the first command CMD1, and provides the source driver 200 and the gate driver 300 with the control signals CNT1, CNT2 and the second image signal data RGB' required for operation.

Specifically, the timing controller 100 may respond to image signal data and control signals input from the outside, control the gate driver 300 and the source driver 200, and utilize the compression stored in the external memory 190 The LUT data compensates for MURA defects included in the input image signal data, and provides the compensated image signal data to the source driver 200.

At this time, the timing controller 100 may include: a memory controller 110, a decompressor 120, a column buffer 130, and an image signal processing unit 150. The specific components of the timing controller 100 and their operations will be described later with reference to FIG. 2.

The external memory 190 can function as an action memory required by the timing controller 100 to perform actions. In some embodiments of the present invention, the external memory 190 may be configured outside the timing controller 100 as shown in the figure. Specifically, the external memory 190 may be packaged in a package on package (PoP) form different from the timing controller 100. However, the present invention is not limited to this.

The source driver 200 converts the digital data applied by the timing controller 100, that is, the second image signal data RGB' into gray-scale voltages and outputs them to the data lines DL1 to DLk of the panel 1100. The gate driver 300 scans the gate lines GL1˜GLj of the panel 1100 sequentially. The gate driver 300 applies the gate-on voltage Von to the selected gate line to activate the selected gate line, and the source driver 200 outputs the corresponding gray-scale voltage to the pixels connected to the activated gate line. Therefore, the panel 1100 is in units of horizontal lines, that is, images can be displayed line by line.

The voltage generator 400 receives the power supply voltage (VCI) applied from the outside, and produces Generate voltages AVDD, Von, and Voff required by the source driver 200 and the gate driver 300.

The first interface circuit 500 is used to communicate with a host (for example, an application processor). The first interface circuit 500 receives the first image signal data RGB and the first command CMD1 applied in parallel or in series by the host, and then provides it to the timing controller 100. The first image signal data RGB and the first command CMD1 can be transmitted by the system host of the display device 1000. The first interface circuit 500 can receive the first image signal data RGB and the first command CMD1 corresponding to the interface mode of the host transmission mode. For example, the interface method used in the first interface circuit 500 may be an RGB interface, a CPU interface, a service provider interface (PSI), a mobile display digital interface (MDDI), and a mobile industry processor interface. (Mobile industry processor interface, MIPI) one of the methods.

The second interface circuit 340 is used to communicate with other display drive circuits (ie, a second display drive circuit (not shown)). The second interface circuit 340 can provide the first synchronization signal SSYNC1 generated by the timing controller 100 to the second display Drive circuit (not shown). The first synchronization signal SSYNC1 is a signal generated in response to the end signal EXE. The second interface circuit 340 may be a different type of interface from the first interface circuit 500. For example, the second interface circuit 340 may be Serial peripheral interface (Serial Peripheral Interface, SPI), internal integrated circuit (Inter Integrated Circuit, I2C), etc., but not limited to this.

Fig. 2 is a block diagram for explaining the timing controller shown in Fig. 1. FIG. 3 shows a block diagram of an embodiment of the image signal processing unit of FIG. 2.

2, a timing controller (TCON) 100 according to an embodiment of the present invention may include: a memory controller (memory controller 110, decompressor 120, line buffer 130, and image signal processor 150.

The memory controller 110 can be connected to an external memory 190.

Specifically, the memory controller 110 is configured to access the external memory 190. For example, the memory controller 110 is configured to control the reading, writing, erasing, and background actions of the external memory 190. The memory controller 110 is configured to provide an interface between the external memory 190 and the timing controller 100. The memory controller 110 is configured to drive and control firmware of the external memory 190. Thus, the memory controller 110 can read the compressed LUT data from the external memory 190. Then, the memory controller 110 may send the read compressed LUT data to the decompressor 120.

The decompressor 120 can decompress the compressed LUT data received from the memory controller 110 to generate original LUT data before compression. The original LUT data may include data for compensating for a MURA defect of the display panel 1100. The MURA defect may include a non-uniformity contrast, luminous or brightness value between image signals of adjacent pixels.

Therefore, when a MURA defect occurs in the display panel 1100, a significant difference in contrast, illuminance, or brightness value will occur between the first pixel and the second pixel adjacent to the first pixel. This MURA defect can include line MURA (line MURA), black spot MURA (black spot MURA), white spot MURA (white spot MURA), black region MURA (black region MURA), white region MURA (white region MURA), ring MURA (ring MURA) and so on.

The decompressor 120 uses a lossless decompression algorithm, which can LUT data generates original LUT data. In this case, the lossless decompression algorithm may include a CTW, LZ77, or LZW decompression algorithm. The lossless decompression algorithm is a well-known technology, so its detailed description is omitted. Then, the decompressor 120 may send the original LUT data to the column buffer 130.

The column buffer 130 may temporarily store the original LUT data received from the decompressor 120. Since the size of the original LUT data is relatively large, the column buffer 130 can temporarily store the original LUT data in order to activate the image signal processing unit 150 during the decompression of the compressed LUT data. Thus, the image signal processing unit 150 can continuously receive the original LUT data. Furthermore, the column buffer 130 can serve as a buffer between the image signal processing unit 150 and the decompressor 120 in order to minimize the time delay required for decompressing the compressed LUT data by the decompressor 120. However, the present invention is not limited to this, and when the decompressor 120 has a high data processing speed, the column buffer 130 may be omitted.

2 and 3, the image signal processing unit 150 can use the original LUT data stored in the column buffer 130 to compensate (compensate) the MURA defect of the input first image signal data RGB, and generate a second Image signal data RGB'.

Specifically, the image signal processing unit 150 may include: a de-MURA controller 152 (De-MURA controller) and a de-MURA processing unit 154 (De-MURA core).

The MURA control unit 152 reads the original LUT data from the column buffer 130, and receives the first image signal data RGB from an external device, and can synchronize the original LUT data and the image signal. The MURA control unit 152 may transmit the aligned original LUT data and the image signal to Go to the MURA processing section 154.

The MURA removal processing unit 154 receives the synchronized original LUT data and the image signal from the MURA removal control unit 152, and uses the original LUT data to eliminate the MURA defect contained in the image signal, Thus, the compensated second image signal data RGB' can be generated.

Specifically, the MURA removal processing unit 154 uses the original LUT data to convert the first image signal data RGB into the second image signal data RGB' that compensates for MURA defects. At this time, the MURA processing unit 154 compensates the first image signal data RGB to the second image signal data RGB'. For example, a MURA correction algorithm such as a brute-force algorithm (MURA) can be used. correction algorithm). As a result, a MURA panel (MURA panel) that has a MURA defect can become a display panel 1100 that operates normally. However, the original LUT data used to activate the MURA correction algorithm will require a relatively large memory capacity, which results in the need to have a relatively large-capacity memory device. Therefore, in the present invention, the original LUT data is compressed by a compression algorithm, thereby reducing the memory capacity and the compressed LUT data can be stored in the external memory 190. In addition, the external memory 190 is separated from the memory controller 110, thereby reducing the size and manufacturing cost of the memory controller 110.

In an embodiment of the present invention, the display device 1000 includes N (the N is a natural number) pixels, and the first image signal data RGB may have data about the N pixels. Moreover, the original LUT data may include compensation values corresponding to all the N pixels. That is, the original LUT data can have MURA defect compensation values for all pixels. In this case, the compensation processing for MURA defects is of high quality, but the memory capacity used to store the original LUT data will increase.

In another embodiment of the present invention, the display device 1000 includes N (the N is a natural number) pixels, and the first image signal data RGB may have data about the N pixels. Moreover, the original LUT data may include a compensation value for every K unit pixels (the K is a natural number smaller than the N). That is, the original LUT data can have MURA defect compensation values related to each unit pixel. In this case, the quality of compensation processing for MURA defects is slightly lower, but the memory capacity used to store the original LUT data will be slightly reduced.

In another embodiment of the present invention, the display device 1000 includes L*M (the L and M are natural numbers) pixels, and the first image signal data RGB may have data about L*M pixels. Moreover, the original LUT data may include compensation values corresponding to the L vertical lines and compensation values corresponding to the M horizontal lines. That is, the original LUT data may have MURA defect compensation values corresponding to the vertical line and the horizontal line of the display panel 1100, respectively. In this case, the quality of compensation processing for MURA defects is low, but the memory capacity used to store the original LUT data will be significantly reduced.

In this way, Power can compensate for MURA defects by using LUT (Look Up Table). However, the resolution of the display panel has recently become higher. As the number of bits used by the LUT increases, the size of the LUT also increases. Therefore, in order to store the LUT, a larger memory capacity is required. Moreover, in order to reduce the overall size of the LUT, when one LUT data is used for each specific unit pixel, the compensation quality of MURA defects will be reduced. In order to solve this problem, the display device 1000 according to an embodiment of the present invention compresses the original LUT data and stores it in the external memory 190. Using a small memory capacity, it can also perform high-quality compensation for display panels containing MURA defects. .

In addition, the external memory 190 is separated from the memory controller 110, thereby reducing the size and manufacturing cost of the memory controller 110.

As mentioned above, considering the display device and various conditions, some original LUT data can be selected to compensate for MURA defects. However, the present invention is not limited to this.

4 is a block diagram for explaining a display device according to another embodiment of the invention. FIG. 5 is a block diagram for explaining a display device according to another embodiment of the invention. For the convenience of description, the following description will focus on the same matters as those in the previously described embodiment, and omit repeated descriptions, and focus on the differences.

4 and 5, the display devices 1001 and 1002 according to some embodiments of the present invention include a display panel 1100, a timing controller 100, and an external memory 190. Actually, the display devices 1001 and 1002 can perform the same operations as the display device 1000 described with reference to FIG. 1.

The display devices 1001 and 1002 according to some embodiments of the present invention may further include an image capturing device 160.

The image capturing device 160 can capture the image output on the display panel 1100. Specifically, the contrast, luminous, or brightness value of each pixel contained in the display panel 1100 can be captured. Thus, it can be determined whether there is a MURA defect on the display panel 1100. When there is a MURA defect on the display panel 1100, the image capturing device 160 can calculate a compensation value related to the MURA defect, and then generate original LUT data including the compensation value.

Specifically, the image capturing device 160 may capture multiple output images of the display panel 1100 for multiple uniform test input images (series of uniform test input images), and combine the multiple The output image is used as a basis to generate original LUT data equivalent to compression data, and the compressed LUT data is stored in the external memory 190. Then, the timing controller 100 can use the compressed LUT data stored in the external memory 190 to compensate The image signal data input from the outside contains the MURA defect, and the compensated image signal data is provided to the display panel 1100. Through this compensation, the display panel 1100 (ie, the MURA panel) that outputs the MURA defect performs an action within a normal range.

In the display device 1001 according to another embodiment of the present invention, the image capture device 160 may be included in a semiconductor package separate from the timing controller 100 and the external memory 190. That is, it can be formed by modules separate from the timing controller 100 and the external memory 190.

However, the present invention is not limited thereto. In the display device 1002 according to another embodiment of the present invention, the image capturing device 160 may be included in the timing controller 100. However, in this case, the timing controller 100 and the image capturing device 160 may be included in a semiconductor package separate from the external memory 190.

FIG. 6 shows a block diagram of an image capture device according to some embodiments of the invention.

6, the image capture device 160 according to some embodiments of the present invention may include: a camera 161 (camera), a processor 162 (processor), a compressor 163 (compressor), a controller 164 (controller), and an interface 165 (interface), internal memory 166 (memory) and bus 167 (bus). The camera 161, the processor 162, the compressor 163, the controller 164, the interface 165, and the internal memory 166 can be combined with each other through the bus 167. The bus 167 corresponds to the path of data movement.

The camera 161 may include an image sensor. The camera 161 can capture the image output on the display panel 1100. Specifically, multiple output images of the display panel 1100 can be captured. For example, the camera 161 can capture the display panel 1100 including The contrast, luminous, or brightness value of each pixel. However, the present invention is not limited to this. The values retrieved in this way can be temporarily stored in the internal memory 166, and can be used in the calculation of the processor 162.

The processor 162 can perform calculations required to drive the image capture device 160. In some embodiments of the present invention, the processor 162 may be configured as a multi-core environment including multiple cores. The processor 162 may use multiple output images captured by the camera 161 as a basis to generate the original LUT data equivalent to the compensation data.

The compressor 163 can compress the original LUT data. At this time, the compressor 163 can compress the original LUT data by using a compression algorithm. The compression algorithm may be in a complementary relationship with the decompression algorithm used by the decompressor 120 of the timing controller 100. For example, the compressor 163 can compress the original LUT data by using CTW, LZ77, or LZW compression algorithms. After the compressed LUT data is temporarily stored in the internal memory 166, it can be transmitted to the external memory 190. However, according to the data transmission capability of the interface 165, it may be directly transmitted to the external memory 190 without passing through the internal memory 166.

The controller 164 can control the entire operation of the image capturing device 160. The controller 164 may include at least one of a microprocessor, digital signal processing, microcontroller, and logic elements capable of performing similar functions. Specifically, the controller 164 can perform instructions to apply a plurality of uniform test input images to the display panel 1100, and then control the camera 161 to capture the display panel related to uniformity test 1100 output image. However, the present invention is not limited to this. The multiple input images for uniformity testing are used to confirm whether there are MURA defects on the display panel 1100 and to generate basic data as input values for compensation data. Multiple input images for uniformity testing are passed through the timing controller 100, can be transmitted to the display panel 1100.

The interface 165 can perform the function of transmitting data to or receiving data from the communication network. The interface 165 may be wired or wireless. For example, the interface surface 165 may include an antenna or a wired and wireless universal transceiver. The interface surface 165 can provide an environment required for smooth connection with external devices (for example, a motherboard). Therefore, the interface surface 165 can be provided with various channels and ports to exchange external devices connected to the image capturing device 160. The interface 165 can transmit the compressed LUT data from the compressor 163 to the external memory 190.

The internal memory 166 can store data and/or commands processed inside the image capture device 160. The internal memory 166 can provide an environment for the processor 162 to connect to an external device for high-speed operation. Moreover, the internal memory 166 can temporarily store a plurality of input image values for uniformity testing, or LUT data compressed by the compressor 163, and the like. However, the present invention is not limited to this.

FIG. 7 is a flowchart of an operation method of an image capture device according to some embodiments of the invention.

Referring to FIGS. 6 and 7, first, the controller 164 of the image capturing device 160 applies the plurality of input images for uniformity testing to the display panel 1100. Next, the camera 161 captures a plurality of output images of the display panel 1100 for the plurality of input images for uniformity testing (S210).

Next, the processor 162 performs a calibration operation on the plurality of output images (S220). The calibration operation is to calibrate multiple images, and can calibrate the focus, tone scale and sensitivity of each image. However, the present invention is not limited to this.

Next, the processor 162 uses the calibrated multiple output images as a basis to produce The original LUT data equivalent to the compensation data is generated (S230). At this time, for the input for the uniformity test, compensation data can be formed based on the different points of the multiple output image data. As described above, the original LUT data may include compensation values related to all pixels, or may only include compensation values related to horizontal lines or vertical lines, or may include one compensation value per unit pixel. However, the present invention is not limited to this.

Next, the compressor 163 compresses the original LUT data to generate compressed LUT data (S240). At this time, the compressor 163 uses a compression algorithm. For example, the compression algorithm may include a CTW, LZ77, or LZW compression algorithm. Moreover, the algorithm may be in a complementary relationship with the decompression algorithm used by the decompressor 120.

Then, the interface 165 transmits the compressed LUT data to the external memory 190 (S250). The compressed LUT data stored in the external memory 190 can be used by the timing controller 100. The timing controller 100 can use the compressed LUT data stored in the external memory 190 to compensate for the MURA defect contained in the input image signal data, and transmit the compensated image signal data to the display panel 1100 . Specifically, the timing controller 100 may include: a memory controller 110 that reads compressed LUT data from the external memory 190; a decompressor that decompresses the compressed LUT data and generates the original LUT data before compression 120; a column buffer 130 that temporarily stores the original LUT data received from the decompressor 120; and a MURA that uses the original LUT data stored in the column buffer 130 to compensate the input image signal data Defective image signal processing unit 150.

Thus, the display device can perform high-quality full-frame compensation processing operations using a small amount of memory. In addition, the external memory 190 is separated from the memory controller 110, so that the size and manufacturing cost of the memory controller 110 can be reduced.

Fig. 8 is a diagram of a display module according to an embodiment of the present invention.

Referring to FIG. 8, the display module 2000 may include a display device 2100, a polarizing plate 2200 and a window glass 2301. The display device 2100 includes a display panel 2110, a printed circuit board 2120 and a display driver chip 2130.

The window glass 2301 is usually made of acrylic or strengthened glass, and protects the display module 2000 from scratches caused by external impact or repeated touch. The polarizing plate 2200 is used to improve the optical characteristics of the display panel 2110. The display panel 2110 is formed on a printed circuit board 2120 with a transparent electrode pattern. The display panel 2110 includes a plurality of pixel units for displaying frames. According to an embodiment, the display panel 2110 may be an organic light emitting diode panel. The pixel unit includes an organic light emitting diode that emits light in response to the flow of current. However, it is not limited to this, and the display panel 2110 may include various display elements. For example, the display panel 2110 may be LCD (Liquid Crystal Display), ECD (Electrochromic Display), DMD (Digital Mirror Device), AMD (Actuated Mirror Device), GLV (Grating Light Value), PDP (Plasma Display Panel), ELD ( Electro Luminescent Display), LED (Light Emitting Diode) display, one of VFD (Vacuum Fluorescent Display).

The display driver chip 2130 may include the above-mentioned display driver circuit. In this embodiment, it is represented by one wafer, but it is not limited to this. Multiple driver chips can be installed. Moreover, COG (Chip On Glass) can be used for mounting on the glass printed circuit board 2120. However, this is only an example, and the display driver chip 213O can be mounted in various forms such as COF (Chip on Film), COB (chip on board), etc.

The display module 2000 can also include a touch panel 2300 and a touch controller 2400. The touch panel 2300 is formed by patterning the same transparent electrode as ITO (Indium Tin Oxide) on a glass substrate or PET (Polyethylene Terephthalate) film. The touch controller 2400 detects the touch on the touch panel 2300, calculates the touch coordinates and transmits them to the host (not shown). The touch controller 2400 can be integrated with the display driver chip 2130 on a semiconductor chip.

Fig. 9 is a diagram of a display system according to an embodiment of the present invention.

9, the display system may include a processor 3100 electrically connected to a system bus 3500, a display device 3200, a peripheral device 3300, and a memory 3400.

The processor 3100 controls the data registration and output of the peripheral device 3300, the memory 3400, and the display device 3200, and can perform image data processing transmitted between the devices.

The display device 3200 includes a panel 3210 and a driving circuit 3220. The image data applied through the system bus 3500 is stored in the frame memory included in the driving circuit 3220, and then displayed on the panel 3210. The display device 3200 may be the display device 1000 of FIG. 1. Therefore, it operates asynchronously with the processor 3100, so that the system load of the processor 3100 can be reduced.

The peripheral device 3300 may be a device that converts video or still images into electrical signals, such as a camera, scanner, webcam, etc. The image data obtained by the peripheral device 3300 can be stored in the memory 3400 or displayed on the panel of the display device 3200 in real time.

The memory 3400 may include a volatile memory device like DRAM and/or a non-volatile memory device like flash memory. The memory 3400 can be composed of DRAM, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, NAND flash memory, and fusion flash memory (for example, SRAM slow It is composed of flash area, NAND flash memory and NOR interface logic combined memory). The memory 3400 can store image data obtained from the peripheral device 3300 or image signals processed by the processor 3100.

The display system according to the embodiments of the present invention may include mobile electronic products such as smart phones. But it is not limited to this. The display system may include various electronic products that display images.

FIG. 10 is an application example diagram of a display device mounted on a variety of electronic products according to some embodiments of the present invention.

The display device 4000 according to some embodiments of the present invention may be used on various electronic products. It can be used not only on the mobile phone 4100, but also on the TV (TV) 4200, the automatic teller machine (ATM) 4300 that automatically replaces bank cash withdrawals, the elevator 4400, the automatic ticket vending machine 4500 used in subway stations, etc., and the portable multimedia player ( PMP) 4600, e-book reader (e-book) 4700, navigation device 4800, etc. are widely used.

The display device 4000 according to some embodiments of the present invention may act asynchronously with the processor of the system. Therefore, the drive load of the processor is reduced, and the processor can be operated at low power and high speed, thereby improving the function of the electronic product. The display device 4000 compresses the original LUT data related to the MURA panel and stores it in an external memory separate from the timing controller, thereby using a small memory capacity, and can also perform high-quality compensation processing on display panels containing MURA defects.

Above, the embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the technical field of the present invention with ordinary knowledge can understand that the present invention can use other specific methods without changing its technical ideas or basic features. Form to implement. Therefore, it should be understood that the described embodiments are merely illustrative in all aspects, and It is not intended to limit the invention.

100‧‧‧Timing Controller

190‧‧‧External memory

200‧‧‧Source Driver

300‧‧‧Gate Driver

340‧‧‧Second interface circuit

400‧‧‧Voltage Generator

500‧‧‧The first interface circuit

1000‧‧‧Display device

1100‧‧‧Panel

1201‧‧‧Display drive circuit

AVDD‧‧‧Voltage

CMD1‧‧‧The first command

CNT1, CNT2‧‧‧Control signal

Cst‧‧‧Storage capacitor

DL1, DL2, DLk-1, DLk‧‧‧Data line

EXE‧‧‧End signal

GL1, GL2, GLj-1, GLj‧‧‧Gate line

Idrv‧‧‧Current

PX‧‧‧Pixel

RGB‧‧‧The first image signal data

RGB'‧‧‧Second image signal data

SSYNC1‧‧‧First sync signal

Tdrv‧‧‧drive transistor

Tsw‧‧‧switching transistor

VCI‧‧‧Power supply voltage

VDD‧‧‧Power supply voltage

Von‧‧‧Voltage/gate conduction voltage

Voff‧‧‧Voltage

VSS‧‧‧Voltage

Claims (20)

A timing controller, comprising: a memory controller that reads compressed look-up table data from an external memory; decompresses the compressed look-up table data received from the memory controller, and generates the original look-up table data before compression A decompressor; a row buffer that temporarily stores the original look-up table data received from the decompressor; and the use of the original look-up table data stored in the row buffer to compensate the input image signal data Image signal processing unit for trace defects. The timing controller according to claim 1, wherein the image signal processing unit includes: reading the original look-up table data from the column buffer, and receiving the image signal data from an external device Afterwards, a de-trace control unit that synchronizes the original look-up table data and the image signal data; and receives the synchronized original look-up table data and the image signal data from the de-trace control unit, And using the original look-up table data to eliminate the trace defects contained in the image signal data, thereby generating a de-trace processing part of the compensated image signal data. The timing controller described in item 1 of the scope of patent application, wherein the trace defect includes non-uniform contrast, illuminance or brightness values between image signals of adjacent pixels. The timing controller described in item 1 of the scope of patent application, wherein the decompressor uses a lossless decompression algorithm to generate the original lookup table data from the compressed lookup table data. The timing controller according to item 4 of the scope of patent application, wherein the lossless decompression algorithm includes a CTW, LZ77, or LZW decompression algorithm. The timing controller described in item 1 of the scope of patent application, wherein the image signal data includes data about N pixels, the N is a natural number, and the original look-up table data includes all data corresponding to the N pixels The compensation value. The timing controller described in item 1 of the scope of patent application, wherein the image signal data includes data related to L*M pixels, the L and the M are natural numbers, and the original look-up table data includes corresponding The compensation values of the L vertical lines and the compensation values corresponding to the M horizontal lines. The timing controller described in item 1 of the scope of patent application, wherein the image signal data includes data about N pixels, where N is a natural number, and the original look-up table data includes one for every K unit pixels For the compensation value, the K is a natural number smaller than the N. The timing controller described in claim 1, wherein the timing controller is included in a semiconductor package that does not include the external memory. A display device includes: a display panel; an external memory storing compressed look-up table data; for a plurality of input images for uniformity testing, a plurality of output images of the display panel are captured, and the captured A plurality of output images are used as a basis to generate original look-up table data equivalent to compensation data, and store the compressed look-up table data in the image capture device of the external memory; and use the image capture device stored in the external memory The compressed look-up table data is compensated from The externally input image signal data contains trace defects, and the compensated image signal data is provided to the timing controller of the display panel. The display device according to claim 10, wherein the image capture device includes: a controller that applies the plurality of input images for uniformity testing to the display panel; and captures the display panel A plurality of output image cameras; a processor that generates the original look-up table data equivalent to compensation data based on the plurality of captured output images; a compressor that compresses the original look-up table data; And transmitting the compressed look-up table data to the interface of the external memory. The display device according to item 11 of the scope of patent application, wherein the compressor uses CTW, LZ77, or LZW compression algorithms to compress the original look-up table data. The display device according to claim 10, wherein the image capturing device is included in the timing controller. The display device according to claim 10, wherein the image capture device is included in a semiconductor package separate from the timing controller and the external memory. The display device according to claim 10, wherein the timing controller includes: a memory controller that reads compressed lookup table data from the external memory; decompresses the compressed lookup table data, and generates A decompressor for compressing the original lookup table data mentioned before; A row buffer that temporarily stores the original look-up table data received from the decompressor; and a diagram of using the original look-up table data stored in the row buffer to compensate for trace defects of input image signal data Like the signal processing department. The display device according to the 15th patent application, wherein the decompressor uses an algorithm complementary to the compressor to process the original look-up table data. A display device includes: a plurality of pixels respectively arranged in the intersection area of a plurality of gate lines and a plurality of data lines; a gate driver for driving the plurality of gate lines; and a source of the plurality of data lines Driver; an external memory storing compressed look-up table data; and responding to image signal data and control signals input from the outside, controlling the gate driver and the source driver, and using all the data stored in the external memory The compressed look-up table data compensates for trace defects contained in the input image signal data, and provides the compensated image signal data to the timing controller of the source driver. The display device according to claim 17, wherein the timing controller includes: a memory controller that reads compressed lookup table data from the external memory; decompresses the compressed lookup table data, and generates A decompressor for compressing the original lookup table data before compression; a row buffer for temporarily storing the original lookup table data received from the decompressor; and The image signal processing unit compensates for trace defects of the input image signal data by using the original look-up table data stored in the column buffer. The display device described in item 17 of the scope of patent application further includes: for a plurality of input images for uniformity testing, a plurality of output images of each of the plurality of pixels are captured, and the captured plurality of Based on each output image, the original look-up table data equivalent to the compensation data is generated, and the compressed look-up table data is stored in the image capturing device of the external memory. The display device according to claim 19, wherein the image capturing device includes: a control unit that applies the plurality of input images for uniformity testing to the plurality of pixels; A camera with multiple output images of multiple pixels; a processor that generates original look-up table data equivalent to compensation data based on the multiple captured output images; compresses the original look-up table data器; and the compressed look-up table data is transmitted to the interface of the external memory.

Images