TWI708395B - Wafer backside thin film structure, semiconductor device including the same, and manufacturing method of wafer backside thin film structure - Google Patents

Abstract

Embodiments of the present disclosure provide a wafer backside thin film structure, a semiconductor device including a wafer backside thin film structure, and a manufacturing method of a wafer backside thin film structure. The wafer backside thin film structure includes a first conductivity type layer, a metal or semiconductor layer, a titanium-containing metal layer, a diffusion barrier layer, and a reactive metal layer. The first conductivity type layer is formed on a silicon substrate of a wafer. The first conductivity type layer includes silicon and a metal or semiconductor component. The first conductivity type layer has a first type conductivity, and the silicon substrate has a second conductivity type that is opposite to the first conductivity type. The metal or semiconductor layer includes the metal or semiconductor component, and the first conductivity type layer is formed between the metal or semiconductor layer and the silicon substrate. The titanium-containing metal layer is formed on the metal or semiconductor layer, the diffusion barrier layer is formed on the titanium-containing metal layer, and the reactive metal layer is formed on the diffusion barrier layer.

Description

Back crystal film structure, semiconductor device including the same, and manufacturing method of back crystal film structure

The content of this disclosure is related to thin film structures and manufacturing methods thereof, and particularly to back crystal thin film structures, semiconductor devices including them, and manufacturing methods of back crystal thin film structures.

Power components are widely used in various electronic products, household appliances, or power systems. In electronic devices, one of the most important components that affect the efficiency of electrical energy conversion is the power element. The power element is a key element for power processing and is used to process electrical energy conversion and power control. As the application of power components becomes more and more popular, new functional requirements are constantly emerging, and the industry also proposes many new development research and improvement solutions for the production and packaging of power components.

For example, improving the high-voltage and high-temperature resistance characteristics of power devices, improving the shortcomings of existing power device packaging technologies, reducing the manufacturing cost of power devices, and simplifying the manufacturing process of power devices are the current research directions in the industry. Therefore, the packaging technology of power components and power modules still faces many new challenges.

Some embodiments of the present disclosure provide a back crystal film structure, which includes a first conductivity type layer, a metal or semiconductor layer, a titanium-containing metal layer, a diffusion barrier layer, and a reactive metal layer. The first conductivity type layer is formed on the silicon substrate of the chip. The first conductivity type layer includes silicon and a metal or semiconductor component. The first conductivity type layer has a first conductivity type, the silicon substrate has a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The metal or semiconductor layer includes the aforementioned metal or semiconductor components, and the first conductivity type layer is formed between the metal or semiconductor layer and the silicon substrate. The titanium-containing metal layer is formed on the metal or semiconductor layer, the diffusion barrier layer is formed on the titanium-containing metal layer, and the reactive metal layer is formed on the diffusion barrier layer.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a silicon substrate, a gate layer, a source structure, a drain layer, and a metal or semiconductor layer. The silicon substrate has a front surface and a back surface opposite to the front surface. The gate layer is formed on the front surface of the silicon substrate. The source structure is formed on both sides of the gate layer. The drain layer is formed on the back surface of the silicon substrate, and the drain layer includes silicon and a metal or semiconductor component. The metal or semiconductor layer contains the aforementioned metal or semiconductor components. The drain layer is formed between the metal or semiconductor layer 150 and the silicon substrate.

Some embodiments of the present disclosure provide a method for manufacturing a back-crystal thin film structure. The method includes: forming a metal or semiconductor layer on a silicon substrate of a wafer, wherein the metal or semiconductor layer includes a metal or semiconductor component; The diffusion process causes the metal or semiconductor components to diffuse into the silicon substrate to form a first conductivity type layer, where the first conductivity type layer includes silicon and the aforementioned metal or semiconductor components; the metal or semiconductor layer is opposite to the first conductivity type layer A titanium-containing metal layer is formed on the surface of the titanium-containing metal layer; a diffusion barrier layer is formed on the titanium-containing metal layer; and a reactive metal layer is formed on the diffusion barrier layer.

The back-crystal film structure of the present disclosure can be applied to various types of semiconductor devices. In order to make the features and advantages of the present disclosure more obvious and easy to understand, a number of embodiments are listed below in conjunction with the accompanying drawings for details described as follows.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the disclosure. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the same or similar component numbers may be used repeatedly in different examples of the embodiments of the present disclosure. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

Some changes of the embodiment are described below. In the embodiments of different drawings and descriptions, similar component symbols are used to denote similar components. It is understood that additional steps may be provided before, during, and after the method, and some of the described steps may be substituted or deleted in other embodiments of the method.

In addition, terms related to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These space-related terms are In order to facilitate the description of the relationship between one element(s) or characteristic part and another element(s) or characteristic part in the illustration, these spatially related terms include the different orientations of the device in use or operation, and the The orientation described. When the device is turned in different directions (rotated by 90 degrees or other directions), the space-related adjectives used therein will also be interpreted according to the turned position.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by the general artisans to whom this disclosure belongs. It is understandable that unless there are special definitions in the embodiments of the disclosure, these terms, such as those defined in commonly used dictionaries, should be interpreted as having meaning consistent with the related technology and the background or context of the disclosure. , And should not be interpreted in an idealized or overly formal way.

The full text of this disclosure describes "pure metal" and "substantially not included" (for example: pure aluminum, substantially not including insulating non-metal elements), which means that it is expected to be designed to be free of other elements, compounds, etc. Impurities, but in the actual smelting, refining, coating and other processes, it is difficult to completely remove the above impurities to achieve mathematical or theoretical 100% pure metal, or mathematical or theoretical 100% does not contain a certain component, and when the above impurity content If the range falls within the allowable range set by the corresponding standard or specification, it can be regarded as "pure metal" and "substantially not included." Those with ordinary knowledge in the technical field to which the content of this disclosure belongs should understand that the above-mentioned corresponding standards or specifications will be different according to different natures, conditions, requirements, etc., so no specific standards or specifications are listed below.

The different embodiments disclosed below may use the same reference symbols and/or marks repeatedly. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures discussed.

FIG. 1 is a schematic cross-sectional view of a back crystal thin film structure 10 according to some embodiments of the present disclosure. Please refer to FIG. 1, the back crystal thin film structure 10 includes a first conductivity type (conductivity type) layer 160, a metal or semiconductor layer 150, a titanium-containing metal layer 110, a diffusion barrier layer 120, and a reactive metal layer 140. The first conductivity type layer 160 is formed on the silicon substrate 100 of the chip. The first conductivity type layer 160 includes silicon and a metal or semiconductor component. The first conductivity type layer 160 has a first conductivity type, the silicon substrate 100 has a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The metal or semiconductor layer 150 includes the aforementioned metal or semiconductor components, and the first conductivity type layer 160 is formed between the metal or semiconductor layer 150 and the silicon substrate 100. The titanium-containing metal layer 110 is formed on the metal or semiconductor layer 150, the diffusion barrier layer 120 is formed on the titanium-containing metal layer 110, and the reactive metal layer 140 is formed on the diffusion barrier layer 120.

In an embodiment, one of the first conductivity type and the second conductivity type is a P-type conductivity type, and the other is an N-type conductivity type.

According to some embodiments of the present disclosure, the first conductivity type layer 160 is in direct contact with the silicon substrate 100 having the second conductivity type, and a PN junction is formed at the interface. Therefore, the back crystal thin film structure 10 can be applied to An electronic device with a PN junction on the back of the chip.

In some embodiments, the metal or semiconductor component may include a metal element or a semiconductor element, and has the property of being capable of being dissolved in silicon. In an embodiment, the metal or semiconductor component does not substantially contain insulating non-metallic elements.

In some embodiments, the metal or semiconductor component is a trivalent element of the periodic table, which may include boron (B), aluminum (Al), indium (In), or any combination of the foregoing. For example, the silicon substrate 100 may have an N-type conductivity type, and the first conductivity type layer 160 has a P-type conductivity type and includes silicon, boron (B), aluminum (Al), indium (In), or any combination of the foregoing. In other words, the first conductivity type layer 160 can be regarded as a P-type doped layer of the N-type silicon substrate 100.

In some other embodiments, the metal or semiconductor component is a pentavalent element of the periodic table, which may include antimony (Sb), bismuth (Bi), or a combination thereof. For example, the silicon substrate 100 may have a P-type conductivity type, and the first conductivity type layer 160 has an N-type conductivity type and includes silicon, antimony (Sb) and/or bismuth (Bi). In other words, the first conductivity type layer 160 can be regarded as an N-type doped layer of the P-type silicon substrate 100.

In some embodiments, as shown in FIG. 1, the first conductivity type layer 160 directly contacts the metal or semiconductor layer 150 and the silicon substrate 100.

In some embodiments, the thickness of the first conductivity type layer 160 is, for example, 0.001 μm to 0.5 μm. In some embodiments, the thickness of the first conductivity type layer 160 is equal to or less than the thickness of the metal or semiconductor layer 150.

In some embodiments, the first conductivity type layer 160 is, for example, a silicon aluminum (AlSi) alloy layer, and the metal or semiconductor layer 150 is, for example, an aluminum (Al) layer. In an embodiment, the first conductivity type layer 160 is, for example, a silicon-aluminum solid solution alloy layer, and the metal or semiconductor layer 150 is, for example, a pure aluminum layer. In some embodiments, the metal or semiconductor layer 150 is, for example, a pure aluminum layer and has a purity of 3N or more.

FIG. 2 is a schematic cross-sectional view of a back crystal thin film structure 10A according to some other embodiments of the present disclosure. In this embodiment, the same or similar component numbers are used for the same or similar components in the previous embodiments, and the related description of the same or similar components please refer to the foregoing description, which will not be repeated here.

In an embodiment, as shown in FIG. 2, the first conductivity type layer 260 of the back crystal thin film structure 10A may include a bottom layer 261 and a plurality of protrusion structures 263. In an embodiment, the bottom layer 261 directly contacts the metal or semiconductor layer 150, and the protrusion structure 263 extends outward from the bottom layer 261 into the silicon substrate 100.

In some embodiments, the concentration of the metal or semiconductor component in the protrusion structure 263 is higher than the concentration of the metal or semiconductor component in the bottom layer 261. For example, in some embodiments, the metal or semiconductor layer 150 is, for example, a pure aluminum layer (that is, the metal or semiconductor component of the metal or semiconductor layer 150 is pure aluminum), then the bottom layer 261 and the protrusion structure 263 both include Silicon and aluminum, and the concentration of aluminum in the protruding structure 263 is higher than the concentration of aluminum in the bottom layer 261. In other words, in the embodiment, both the bottom layer 261 and the protrusion structure 263 including silicon and aluminum can be regarded as the aluminum-doped P-type doped layer of the silicon substrate 100, and the doping concentration of the protrusion structure 263 is higher than that of the bottom layer 261. Doping concentration.

In some embodiments, the thickness of the bottom layer 261 is, for example, 0.001 μm to 0.5 μm. In some embodiments, the thickness of the bottom layer 261 is, for example, 0.01 μm to 0.1 μm.

In some embodiments, the height of the protruding structure 263 is, for example, 0.001 μm to 3 μm. In some embodiments, the height of the protruding structure 263 is, for example, 0.01 μm to 1 μm.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 20 formed by using the back crystal thin film structure 10 of FIG. 1 according to some embodiments of the present disclosure. In this embodiment, the same or similar component numbers are used for the same or similar components in the previous embodiments, and the related description of the same or similar components please refer to the foregoing description, which will not be repeated here. It should be noted that the present embodiment uses the back crystal film structure 10 of FIG. 1 as an example, but it is not limited to this. The power module package of the embodiment of the present disclosure may also include the foregoing as shown in FIG. 2 The back crystal film structure 10A.

In an embodiment, as shown in FIG. 3, the semiconductor device 20 includes a silicon substrate 100, a gate layer 310, a source structure 320, a first conductivity type layer 160, and a metal or semiconductor layer 150. The first conductivity type layer 160 may It serves as the drain layer of the semiconductor device 20. The silicon substrate 100 has a front surface 100a and a back surface 100b opposite to the front surface 100a. The gate layer 310 is formed on the front surface 100 a of the silicon substrate 100. The source structure 320 is formed on both sides of the gate layer 310. The first conductivity type layer 160 (drain layer) is formed on the rear surface 100b of the silicon substrate 100, and as described above, the first conductivity type layer 160 (drain layer) includes silicon and a metal or semiconductor component. The metal or semiconductor layer 150 includes the same metal or semiconductor composition as the first conductivity type layer 160. The first conductivity type layer 160 (drain layer) is formed between the metal or semiconductor layer 150 and the silicon substrate 100.

In some embodiments, as shown in FIG. 3, the semiconductor device 20 may further include a dielectric layer 330. In an embodiment, the dielectric layer 330 surrounds the gate layer 310, and the gate layer 310 and the source structure 320 are separated from each other by the dielectric layer 330.

In some embodiments, as shown in FIG. 3, the semiconductor device 20 may further include a first conductivity type doped region 340. In some embodiments, the first conductivity type doped region 340 has the first conductivity type, the source structure 320 has the second conductivity type, and the first conductivity type doped region 340 surrounds the source structure 320. In some embodiments, the silicon substrate 100 has the second conductivity type, and the source structure 320 and the silicon substrate 100 are separated by the first conductivity type doped region 340.

In some embodiments, the semiconductor device 20 shown in FIG. 3 is, for example, a metal oxide semiconductor transistor (MOSFET) chip or an insulated gate bipolar transistor (IGBT) chip in a power module.

In some embodiments, the silicon substrate 100 has an N-type conductivity type, and the first conductivity type layer 160 (drain layer) has a P-type conductivity type, so the first conductivity type layer 160 (drain layer) and the metal or semiconductor layer 150 The metal or semiconducting component contains boron, aluminum, indium, or any combination of the above.

In some other embodiments, the silicon substrate 100 has P type conductivity, and the first conductivity type layer 160 (drain layer) has N type conductivity. The first conductivity type layer 160 (drain layer) and the metal or semiconductor layer The metal or semiconductor component of 150 contains antimony, bismuth, or a combination of the above.

In some embodiments, as shown in FIG. 3, the semiconductor device 20 may further include a titanium-containing metal layer 110, a diffusion barrier layer 120, and a reactive metal layer 140. In an embodiment, the titanium-containing metal layer 110 is formed on the metal or semiconductor layer 150, the diffusion barrier layer 120 is formed on the titanium-containing metal layer 110, and the reactive metal layer 140 is formed on the diffusion barrier layer 120.

In some embodiments, as shown in Figure 1, the titanium-containing metal layer 110 may include a titanium (Ti) layer, a titanium tungsten (TiW) alloy layer, or a titanium-titanium tungsten-titanium (Ti-TiW-Ti) composite layer (Not shown in Figure 1). The titanium-containing metal layer 110 can be used to improve the adhesion between the subsequent metal film layer and the silicon surface. In some embodiments, the thickness of the titanium-containing metal layer 110 is, for example, 0.001 μm to 1 μm. In some embodiments, the thickness of the titanium-containing metal layer 110 is, for example, 0.1 micrometer to 0.8 micrometer. However, the thickness can be adjusted adaptively according to actual applications, and the content of the disclosure is not limited to this.

In some embodiments, the diffusion barrier layer 120 may include nickel. The diffusion barrier layer 120 can be used to prevent the subsequent metal layer from diffusing toward the silicon substrate 100, or to prevent the titanium-containing metal layer 110 from diffusing toward the subsequent metal layer. In some embodiments, the thickness of the diffusion barrier layer 120 is, for example, 0.1 μm to 10 μm. In some embodiments, the thickness of the diffusion barrier layer 120 is, for example, 0.1 μm to 1 μm. However, the thickness can be adjusted adaptively according to actual applications, and the content of the disclosure is not limited to this.

In some embodiments, the reactive metal layer 140 may include silver, copper, nickel, gold, or any combination of the foregoing. The reactive metal layer 140 can be a reactive layer used for subsequent die-bonding with other substrates, and can also protect the underlying metal film layer (such as the diffusion barrier layer 120) from oxidation. In some embodiments, the thickness of the reactive metal layer 140 is, for example, 0.01 μm to 10 μm. In some embodiments, the thickness of the reactive metal layer 140 is, for example, 0.5 μm to 1 μm. However, the thickness can be adjusted adaptively according to actual applications, and the content of the disclosure is not limited to this.

In some embodiments, as shown in FIG. 3, the semiconductor device 20 may further include a substrate 200, a substrate reactive metal layer 210, and a bonding structure 170. In an embodiment, the substrate reactive metal layer 210 is formed on the substrate 200, and the bonding structure 170 directly contacts the reactive metal layer 140 and the substrate reactive metal layer 210.

In some embodiments, the substrate 200 may be any substrate suitable for bonding with the silicon substrate 100 of the chip, such as a ceramic substrate, a printed circuit board, a copper substrate, a silicon interposer, a lead frame, or Another chip.

In some embodiments, the substrate reactive metal layer 210 may include silver, copper, nickel, gold, or any combination of the foregoing.

In some embodiments, the bonding structure 170 may include tin and one or more additive metals, and the additive metals may include copper, silver, bismuth, indium, zinc, antimony, or any combination thereof. In some embodiments, the bonding structure 170 is, for example, lead-free solder.

In some embodiments, the semiconductor device 20 is bonded to the substrate 200 by the reactive metal layer 140, the bonding structure 170, and the substrate reactive metal layer 210 to form a metal oxide semiconductor transistor (MOSFET) or an insulated gate pair and transistor. (IGBT) power module package 30.

4A to 4D are schematic cross-sectional views illustrating various stages of forming the back crystal thin film structure 10 according to some embodiments of the present disclosure. In this embodiment, the same or similar component numbers are used for the same or similar components in the previous embodiments, and the related description of the same or similar components please refer to the foregoing description, which will not be repeated here.

Referring to FIG. 4A, a metal or semiconductor layer 150A is formed on the silicon substrate 100 of the wafer. The metal or semiconductor layer 150A includes a metal or semiconductor component. The metal or semiconductor composition of the metal or semiconductor layer 150A is the same as the metal or semiconductor composition of the aforementioned metal or semiconductor layer 150, and will not be repeated here.

In some embodiments, the metal or semiconductor components can be formed on the silicon substrate 100 by evaporation, sputtering, electroplating, or deposition. According to some embodiments of the present disclosure, a metal or semiconductor component is fabricated on the surface of the silicon substrate 100 by vapor deposition to obtain a metal or semiconductor layer 150A with higher purity, which is beneficial to the subsequent formation of the first conductivity type layer 160 And at the same time, it can have the advantages of fast deposition rate and low cost.

In some embodiments, before the subsequent diffusion process, the purity of the metal or semiconductor component of the metal or semiconductor layer 150A is, for example, 3N or more.

In some embodiments, before the subsequent diffusion process, the thickness of the metal or semiconductor layer 150A is, for example, 0.1 μm to 1 μm. In some embodiments, before the subsequent diffusion process, the thickness of the metal or semiconductor layer 150A is, for example, 0.1 μm to 0.5 μm.

Next, referring to Figure 4B, a diffusion process 180 is performed on the metal or semiconductor layer 150A to diffuse the metal or semiconductor components into the silicon substrate 100 to form a first conductivity type layer 160. The formed first conductivity type layer 160 includes silicon And the metal or semiconductor component of the metal or semiconductor layer 150A.

In some embodiments, the diffusion process 180 may include a thermal process, and the temperature of the thermal process is less than the melting point of the metal or semiconductor component. In some embodiments, the heating temperature of the thermal process is, for example, 100°C to 300°C. In some embodiments, the heating time of the thermal process is, for example, 30 minutes to 300 minutes. Specifically, when the heating temperature of the thermal process is higher and/or the heating time is longer, the formed first conductivity type layer 160 may have a higher thickness and/or a higher concentration of metal or semiconductor components. .

In some embodiments, the metal or semiconductor layer 150A is a pure aluminum layer, and the heating temperature of the diffusion process 180 is, for example, less than the melting point of aluminum, that is, less than about 550°C, to form the first conductive layer 160 containing silicon and aluminum. The formed first conductivity type layer 160 is, for example, a silicon aluminum solid solution alloy.

Specifically, in some embodiments, the silicon atoms in the silicon substrate 100 diffuse toward the metal or semiconductor layer 150A and dissolve between aluminum atoms in the metal or semiconductor layer 150A to form a silicon-aluminum solid solution alloy. The aluminum solid solution alloy is the first conductive type layer 160. Since part of the aluminum atoms and silicon atoms form a silicon-aluminum solid solution alloy (first conductivity type layer 160), after the first conductivity type layer 160 is formed, a part of the metal or semiconductor layer 150A is consumed, and A thinner metal or semiconductor layer 150 is formed.

In some other embodiments, please refer to Figure 4B and Figure 2 at the same time. When the silicon atoms in the silicon substrate 100 diffuse toward the metal or semiconductor layer 150A, and dissolve between the aluminum atoms in the metal or semiconductor layer 150A to form silicon In the case of aluminum solid solution alloys, the separation of silicon atoms may cause voids to be formed in the silicon substrate 100. At this time, aluminum atoms in the metal or semiconductor layer 150A may diffuse into the silicon substrate 100 and fill these voids, thus forming As shown in the protruding structure 263 shown in FIG. 2, the silicon-aluminum solid solution alloy formed by dissolving silicon atoms between aluminum atoms constitutes the bottom layer 261 as shown in FIG. In this way, according to some embodiments of the present disclosure, the bottom layer 261, the protrusion structure 263, and the thinned metal or semiconductor layer 150 as shown in FIG. 2 are formed, and the metal or semiconductor layer 150 is, for example, a pure aluminum layer Both the bottom layer 261 and the protruding structure 263 include silicon and aluminum, and the concentration of aluminum in the protruding structure 263 is higher than the concentration of aluminum in the bottom layer 261.

Generally speaking, ion implantation is usually used to fabricate the PN junction structure in electronic devices, but the ion implantation machine is expensive, resulting in high manufacturing costs. According to some embodiments of the present disclosure, the metal or semiconductor layer 150A is first formed on the silicon substrate 100 by evaporation, sputtering, electroplating, or deposition, and then the first conductive layer is formed on the silicon substrate 100 by a diffusion process 180 Type layer 160/260, the first conductivity type layer 160/260 formed contains silicon and selected metal or non-metal components and has a conductivity type opposite to that of the silicon substrate 100. Therefore, it can be used in silicon without ion implantation process. The surface of the substrate 100 is formed with doped layers with different conductivity types, and the manufacturing cost can be greatly reduced.

Furthermore, according to some embodiments of the present disclosure, the first conductivity type layer 160/260 made by the high-purity metal or semiconductor layer 150A by a diffusion process has a relatively high concentration of metal or semiconductor components, which is comparable Compared with the general doped layer produced by ion implantation, it is equivalent to a high doping concentration, so it is suitable for applications that require a high doping concentration, such as the drain layer of a transistor.

Next, referring to FIG. 4C, a titanium-containing metal layer 110 is formed on the surface of the metal or semiconductor layer 150 opposite to the first conductivity type layer 160. The material of the titanium-containing metal layer 110 is as described above, and will not be repeated here.

In some embodiments, the titanium-containing metal layer 110 may be formed on the surface of the silicon substrate 100 by evaporation, sputtering, electroplating, or deposition. For example, as shown in FIG. 4C, in some embodiments, a titanium layer or a titanium-tungsten (TiW) alloy layer may be formed on the silicon substrate 100 by evaporation or sputtering to form a single-layer structure The titanium-containing metal layer 110. In some other embodiments, a titanium layer, a titanium tungsten layer, and a titanium layer may be sequentially formed on the silicon substrate 100 by evaporation or sputtering to form a titanium-titanium-tungsten-titanium composite layer having a three-layer structure (Not shown in Figure 4C).

Next, referring to FIG. 4D, a diffusion barrier layer 120 is formed on the titanium-containing metal layer 110. The material of the diffusion barrier layer 120 is as described above, and will not be repeated here. In some embodiments, the diffusion barrier layer 120 may be formed on the titanium-containing metal layer 110 by evaporation, sputtering, electroplating, or deposition.

Next, referring to FIGS. 1 and 2, a reactive metal layer 140 is formed on the diffusion barrier layer 120. The material of the reactive metal layer 140 is as described above, and will not be repeated here. In some embodiments, the reactive metal layer 140 may be formed on the metal material layer 130 by evaporation, sputtering, electroplating, or deposition. So far, the back crystal thin film structure 10 shown in FIG. 1 or the back crystal thin film structure 10A shown in FIG. 2 is formed.

The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can better understand the embodiments of the disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other manufacturing processes and structures based on the embodiments of the present disclosure, so as to achieve the same purpose and/or as described here. The same advantages as the embodiment. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the disclosure. Without departing from the inventive spirit and scope of the embodiments of the disclosure, various changes, substitutions or modifications can be made to the embodiments of the disclosure. Therefore, the scope of protection of the disclosure should be defined by the scope of the attached patent application. Whichever prevails. In addition, although the content of the present disclosure has been disclosed in several preferred embodiments as described above, it is not intended to limit the content of the present disclosure, and not all advantages have been described in detail here.

Each claim item of the present disclosure may be an individual embodiment, and the scope of the present disclosure includes each claim of the present disclosure and any combination of each embodiment with each other.

10.10A: Back crystal film structure

20: Semiconductor device

30: Power module package

100: Silicon substrate

100a: front surface

100b: rear surface

110: Ti-containing metal layer

120: diffusion barrier

140: reactive metal layer

150, 150A: metal or semiconductor layer

160, 260: first conductivity type layer

170: Joint structure

180: diffusion process

200: substrate

210: substrate reactive metal layer

261: bottom

263: protruding structure

310: gate layer

320: source structure

330: Dielectric layer

340: first conductivity type doped region

In order to make the features and advantages of this disclosure more comprehensible, different embodiments are specifically cited below, and detailed descriptions are made in conjunction with the accompanying drawings as follows: Figure 1 is a back crystal film structure according to some embodiments of the disclosure Schematic diagram of the cross-section. FIG. 2 is a schematic cross-sectional view of a back crystal film structure according to some other embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view of a semiconductor device formed using the back crystal film structure of FIG. 1 according to some embodiments of the present disclosure. FIGS. 4A to 4D are schematic cross-sectional views illustrating various stages of forming the back crystal film structure according to some embodiments of the present disclosure.

10: Back crystal film structure

100: Silicon substrate

100a: front surface

100b: rear surface

110: Ti-containing metal layer

120: diffusion barrier

140: reactive metal layer

150: Metal or semiconductor layer

160: first conductivity type layer

Claims (18)

A back crystal film structure includes: a first conductivity type (conductivity type) layer formed on a silicon substrate of a chip, wherein the first conductivity type layer includes silicon and a metal or semiconductor component, and the first conductivity type The layer has a first conductivity type, the silicon substrate has a second conductivity type, and the second conductivity type is opposite to the first conductivity type; a metal or semiconductor layer includes the metal or semiconductor component, wherein the first conductivity type A layer is formed between the metal or semiconductor layer and the silicon substrate; a titanium-containing metal layer is formed on the metal or semiconductor layer; a diffusion barrier layer is formed on the titanium-containing metal layer; and a reactive metal layer , Formed on the diffusion barrier layer. The back crystal film structure described in the first item of the patent application, wherein the metal or semiconductor component is a trivalent element, including boron, aluminum, indium, or any combination of the foregoing. The back crystal thin film structure as described in item 1 of the scope of patent application, wherein the metal or semiconductor component is a pentavalent element, including antimony, bismuth, or a combination of the foregoing. In the back-crystal film structure described in claim 1, wherein the first conductivity type layer directly contacts the metal or semiconductor layer and the silicon substrate. According to the back crystal film structure described in claim 1, wherein the first conductivity type layer includes: a bottom layer directly contacting the metal or semiconductor layer; and a plurality of protruding structures extending from the bottom layer to Within the silicon substrate. According to the back crystal film structure described in item 5 of the scope of patent application, the concentration of the metal or semiconductor component in the protruding structures is higher than the concentration of the metal or semiconductor component in the bottom layer. According to the back crystal film structure described in item 5 of the scope of patent application, the thickness of the bottom layer is 0.001 micron to 0.1 micron. In the back crystal film structure described in the first item of the patent application, the first conductivity type layer is a silicon aluminum alloy layer, and the metal or semiconductor layer is an aluminum layer. A semiconductor device includes: a silicon substrate having a front surface and a back surface opposite to the front surface; a gate layer formed on the front surface of the silicon substrate; a source structure formed on the gate On both sides of the electrode layer; a drain layer formed on the rear surface of the silicon substrate, wherein the drain layer includes silicon and a metal or semiconductor component; and a metal or semiconductor layer including the metal or semiconductor component, The drain layer is formed between the metal or semiconductor layer and the silicon substrate. The semiconductor device described in claim 9, wherein the silicon substrate has an N-type conductivity, and the metal or semiconductor component includes boron, aluminum, indium, or any combination thereof. According to the semiconductor device described in claim 9, wherein the silicon substrate has a P-type conductivity, and the metal or semiconductor component includes antimony, bismuth, or a combination thereof. The semiconductor device described in claim 9 further includes: a titanium-containing metal layer formed on the metal or semiconductor layer; a diffusion barrier layer formed on the titanium-containing metal layer; and a reactive metal Layer formed on the diffusion barrier layer. The semiconductor device described in item 12 of the scope of the patent application further includes: a substrate; a substrate reactive metal layer formed on the substrate, wherein the substrate reactive metal layer includes silver, copper, nickel, gold, or any of the foregoing Combination; and a bonding structure that directly contacts the reactive metal layer and the substrate reactive metal layer. A method for manufacturing a back crystal thin film structure includes: forming a metal or semiconductor layer on a silicon substrate of a wafer, wherein the metal or semiconductor layer includes a metal or semiconductor component; performing a diffusion process on the metal or semiconductor layer, The metal or semiconductor component is diffused into the silicon substrate to form a first conductivity type layer, wherein the first conductivity type layer includes silicon and the metal or semiconductor component; in the metal or semiconductor layer relative to the first conductivity A titanium-containing metal layer is formed on a surface of the type layer; a diffusion barrier layer is formed on the titanium-containing metal layer; and a reactive metal layer is formed on the diffusion barrier layer. The manufacturing method of the back crystal thin film structure as described in claim 14, wherein forming the metal or semiconductor layer on the silicon substrate of the wafer includes: evaporating the metal or semiconductor component on the surface of the silicon substrate . According to the method for manufacturing the back crystal thin film structure described in item 14 of the scope of the patent application, the purity of the metal or semiconductor layer is 3N or more before the diffusion process. According to the manufacturing method of the back crystal thin film structure described in claim 14, wherein before the diffusion process, the thickness of the metal or semiconductor layer is 0.1 micrometer to 0.5 micrometer. According to the manufacturing method of the back crystal thin film structure described in claim 14, wherein the diffusion process includes a thermal process, and the temperature of the thermal process is less than the melting point of the metal or semiconductor component.

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