TWI707364B - Memory storage apparatus and an operating method thereof - Google Patents

Abstract

A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array and a memory controller. The memory cell array includes a plurality of cells. The cells are configured to store data. Each of the cells is coupled to a corresponding word line and a corresponding bit line. The memory controller is configured to perform a read operation on the memory cell array. When the memory controller enables the word line, the memory controller simultaneously performs a pre-charge operation on a part or all of the bit lines. In addition, an operation method of a memory storage apparatus is also provided.

Description

Memory storage device and operation method thereof

The present invention relates to an electronic device and an operation method thereof, and particularly relates to a memory storage device and an operation method thereof.

For memory storage devices, such as non-volatile memory, the signal transmission interface between the memory controller and the memory controller is mainly clock-based for signal transmission. Therefore, the signal transfer operation between the memory storage device and the memory controller can be more coordinated by using the clock dependency. In addition, in order to reduce costs, the chip package has a less pin count, and the memory storage device also needs to perform signal transmission operations with the controller based on the clock pulse.

With the development of memory storage devices and user requirements, the clock rate is getting faster and faster. However, if the reading speed of the memory storage device cannot be increased relatively, the development of the clock speed will encounter a bottleneck. In the prior art, in order to complete the read operation, it takes more time to precharge the bit line. Therefore, the read speed cannot be increased, thereby limiting the clock speed.

The present invention provides a memory storage device and an operating method of the memory storage device, which have a fast reading speed and can be operated at a higher clock speed.

The memory storage device of the present invention includes a plurality of word lines, a plurality of bit lines, a memory cell array and a memory controller. The memory cell array includes a plurality of memory cells. The memory cell is used to store data. Each memory cell is coupled to the corresponding word line and bit line. The memory controller is used for reading the memory cell array. While the memory controller enables the word lines, the memory controller performs a precharge operation on part or all of the bit lines.

The operating method of the memory storage device of the present invention includes: receiving and decoding segment signals to perform read operations on the segments in the memory cell array; and enabling word lines, and between the enabling word lines At the same time, a precharge operation is performed on a part or all of the bit lines.

Based on the above, in the exemplary embodiment of the present invention, while the memory controller enables the word lines, the memory controller precharges part or all of the bit lines to speed up the reading of the memory storage device. Take the speed.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Several embodiments are presented below to illustrate the present invention, but the present invention is not limited to the exemplified embodiments. The embodiments also allow proper combination. The term "coupled" used in the entire specification of this application (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if the text describes that the first device is coupled to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Indirectly connected to the second device. In addition, the term "signal" can refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic circuit diagram of the combination of the bit line and the channel gate transistor of the embodiment of FIG. 1, which includes a plurality of precharge paths. 1 and 2, the memory storage device 100 of this embodiment includes a plurality of word lines WL, a plurality of bit lines BL, a memory cell array 110, a memory controller 120, and a word line decoder 130 and bit line decoder 140. In this embodiment, the memory cell array 110 includes a plurality of memory cell 112. The memory cell 112 is used to store data. Each memory cell 112 is coupled to the corresponding word line WL and bit line BL. The memory controller 120 is used to perform a read operation on the memory cell array 110. In this embodiment, the memory controller 120 receives and decodes the sector signal S to select a target sector in the memory cell array 110 to perform a read operation accordingly.

In this embodiment, the memory storage device 100 may include other suitable circuits for cooperatively controlling data access, such as a segment decoder and a sense amplifier circuit. In this embodiment, the various circuits in the memory storage device 100 can be implemented by any suitable circuit structure in the technical field. The present invention is not limited. The circuit structure and operation method can be implemented by the technical field. The general knowledge of the students is sufficient to teach, suggest and implement.

Generally speaking, when the memory controller 120 performs a read operation on the memory cell array 110, it can usually be divided into multiple stages, such as command input, word line address input, and bit line address input, etc. stage. After the memory controller 120 performs a read operation on the memory cell array 110, the data stored in the memory cell 112 can be sequentially read. The phase of bit line address input usually includes precharge operation, sensing operation, and data output operation.

Please refer to FIG. 2, in this embodiment, when the memory controller 120 performs a precharge operation on the memory cell array 110, the memory controller 120 controls the bit line decoder 140 to perform the bit line address signal YSC <3:0>, YSB<3:0> and YSA<3:0> are decoded to select the target bit line for precharge operation. In this embodiment, the bit lines include multiple local bit lines LBL and multiple global bit lines GBL. The data lines include multiple regional data lines LDL and multiple global data lines GDL. Channel gate transistors 200 are provided on each element line and data line. In this embodiment, the memory controller 120 selects the channel gate transistor 200 to be conductive or non-conductive in a hierarchical manner, for example, to select the target bit line to be precharged. For example, in this embodiment, the bit line address signals YSC<3:0>, YSB<3:0> and YSA<3:0> are decoded in sequence, for example. Therefore, the channel gate transistor controlled by the bit line address signal YSC<3:0> (for example, the transistor controlled by the bit line address signal YSC[0]) may be conductive or non-conductive. Then, the channel gate transistor controlled by the bit line address signal YSB<3:0> (for example, the bit line address signal YSB[0], YSB[1], YSB[2], YSB[3] control Transistor) may be conductive or non-conductive. Then, the channel gate transistor controlled by the bit line address signal YSA<3:0> (for example, the bit line address signal YSA[0], YSA[1], YSA[2], YSA[3] The controlled transistor) may be conducting or not conducting. Therefore, through the above decoding sequence, the corresponding channel gate transistor will be turned on, so that a precharge path including the global data line GDL, the regional data line LDL, the global bit line GBL, and the regional bit line LBL can be established, and The target bit line to be precharged can be selected. The target bit line is, for example, any one of the regional bit lines LBL. In one embodiment, another layering method is that the bit line address signals YSA<3:0>, YSB<3:0> and YSC<3:0> are decoded in sequence. Therefore, the channel gate transistor 200 is sequentially turned on from the regional bit line LBL, the global bit line GBL, and the regional data line LDL, thereby establishing a precharge path. After the precharge path is established, the target bit line is charged. Therefore, when data is read, the cell current can establish a preset voltage at the input terminal of the sense amplifier circuit (not shown) to compare with the reference voltage, so that the sense amplifier circuit can determine the location of the cell The stored data is bit 0 or bit 1.

In FIG. 1 and FIG. 2, the number of word lines, bit lines, data lines, memory cells, and channel gate transistors and their arrangement manners are only used for illustration and not to limit the present invention.

Generally speaking, no matter which layering method is adopted, the precharging operation will take a lot of time when decoding the bit line address signal, which limits the reading speed of the memory storage device 100. Therefore, in the present embodiment, while the memory controller 120 enables the word line WL, or while the memory controller 120 decodes the segment signal, the memory controller 120 performs a part of the bit line Or all the bit lines are precharged first, so as to reduce the precharge time of the bit lines when decoding the bit line address signals, thereby increasing the reading speed of the memory storage device 100. A number of exemplary embodiments will be given below to illustrate the operating method of the memory storage device of the present invention.

3 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to an embodiment of the present invention. Please refer to FIGS. 1 to 3. The signals shown in FIG. 3 include a clock signal CLK, an input signal DI, and an output signal DO. In this embodiment, the memory controller 120 receives a read command to perform a read operation on the memory cell array 110.

In this embodiment, during the decoding period T1, the memory controller 120 decodes the segment signal S (for example, including the segment addresses Aa and Ab) to obtain the address of the target segment, thereby selecting the memory cell array 110 The target section to be read in. During the decoding period T2, the memory controller 120 controls the word line decoder 130 to decode the word line addresses Ac and Ad to select the target word line. The decoding period T3 includes decoding periods T4 and T5. During the decoding period T4, the memory controller 120 controls the bit line decoder 140 to decode the bit line addresses Ae and Af to select the target bit line. During the decoding period T5, the memory controller 120 decodes the sensor address Ag to select the target sensor to sense the cell current to determine the data bit state stored in the cell.

In this embodiment, the memory controller 120 starts the precharge operation on all bit lines at the start time t_Y-Line, and completes the precharge operation when the decoding period T2 ends, so the first precharge period tPRE_1 includes the decoding periods T1 and T2. In other words, in this embodiment, the memory controller 120 simultaneously decodes the segment signal S and enables the word line WL, and simultaneously performs the processing of the local bit line LBL, the global bit line GBL, The regional data line LDL and the global data line GDL perform a precharge operation. Then, in the second precharge period tPRE_2, according to the decoding results of the bit line addresses Ae and Af, the unselected bit lines and data lines are discharged, and the selected bit lines (for example, the target area bit lines) The voltage of is maintained and driven before the sensing period. Therefore, during the decoding period T1 and T2, all the bit lines are precharged first. Compared with the prior art, the time length of the second precharge period tPRE_2 can be reduced, and the reading speed can be increased.

In this embodiment, the memory controller 120 performs precharging operations on all bit lines at the same time while decoding the segment signal S and at the same time as enabling the word lines WL. However, the present invention does not Limited to this. In one embodiment, during the first precharge period tPRE_1, the memory controller 120 performs a precharge operation on a part of the bit lines, for example. For example, the memory controller 120 simultaneously precharges the global bit line GBL, the regional data line LDL, and the global data line GDL while decoding the segment signal S and enabling the word line WL. . That is, in addition to the regional bit line LBL, the global bit line GBL, the regional data line LDL, and the global data line GDL are all precharged during the first precharge period tPRE_1. Therefore, during the decoding period T1 and T2, the precharge operation is performed on a part of the bit lines except the regional bit line LBL. Compared with the prior art, the time length of the second precharge period tPRE_2 can be reduced and the reading can be accelerated Take the speed.

4 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. Please refer to FIG. 1, FIG. 2 and FIG. 4. The precharge operation method of this embodiment is similar to the precharge operation method of the embodiment of FIG. 3, but the main difference between the two is that, for example, the memory controller 120 is enabled The word line WL performs a precharge operation on all bit lines at the same time.

Specifically, in this embodiment, the memory controller 120 starts the precharging operation on all bit lines at the start time t_Y-Line, and completes the precharging operation when the decoding period T2 ends, so the first The precharge period tPRE_1 includes the decoding period T2. In other words, in this embodiment, the memory controller 120 enables the word line WL while simultaneously presetting the local bit line LBL, the global bit line GBL, the local data line LDL, and the global data line GDL. Charging operation. Then, in the second precharge period tPRE_2, according to the decoding results of the bit line addresses Ae and Af, the unselected bit lines and data lines are discharged, and the selected bit lines (for example, the target area bit lines) The voltage of is maintained and driven before the sensing period. Therefore, when the word line WL is enabled (decoding period T2), all bit lines are precharged first. Compared with the prior art, the time length of the second precharge period tPRE_2 can be reduced and the reading speed can be increased.

In this embodiment, the memory controller 120 simultaneously precharges all bit lines while enabling the word lines WL, but the invention is not limited to this. In one embodiment, during the first precharge period tPRE_1, the memory controller 120 performs a precharge operation on a part of the bit lines, for example. For example, the memory controller 120 simultaneously precharges the global bit line GBL, the regional data line LDL, and the global data line GDL while enabling the word line WL. That is, in addition to the regional bit line LBL, the global bit line GBL, the regional data line LDL, and the global data line GDL are all precharged during the first precharge period tPRE_1. Therefore, when the word line WL is enabled (decoding period T2), a part of the bit lines except the local bit line LBL is precharged. Compared with the prior art, the second precharge can be reduced. During the time length of tPRE_2, speed up the reading speed.

5 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. Please refer to FIG. 1, FIG. 2 and FIG. 5. In this embodiment, in addition to the regional bit line LBL, the global bit line GBL, the regional data line LDL, and the global data line GDL are all preset during the decoding period T1 and T2. Recharge. In addition, during the decoding period T2, the local bit line LBL is isolated. For example, in this embodiment, at the same time that the word line WL is enabled (decoding period T2), the channel gate transistor controlled by the bit line address signal YSA<3:0> is for example not conducting, so that Isolate the regional bit line LBL from the global bit line GBL and other signal lines. Then, in the third precharge period tPRE_3, the unselected bit lines and data lines are discharged, and in the fourth precharge period tPRE_4, the selected bit lines (for example, the target area bit lines) are precharged.

Therefore, in this embodiment, during the decoding periods T1 and T2, a part of the bit lines except for the regional bit line LBL is precharged. Compared with the prior art, the third precharge period tPRE_3 can be reduced. The sum of the time length of the fourth pre-charge period tPRE_4 speeds up the reading speed.

6 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. Please refer to FIG. 1, FIG. 2 and FIG. 6, the precharge operation method of this embodiment is similar to the precharge operation method of the embodiment of FIG. 5, but the main difference between the two is that the memory controller 120 is in the first During the precharge period tPRE_1, a part of the bit lines are precharged. In addition, in this embodiment, the first precharge period tPRE_1 includes a decoding period T1 and a part of the decoding period T2 adjacent thereto.

Specifically, in this embodiment, in addition to the regional bit line LBL, the global bit line GBL, the regional data line LDL, and the global data line GDL are all precharged during the first precharge period tPRE_1. In addition, during the second precharge period tPRE_2, the regional bit line LBL is isolated. The second precharge period tPRE_2 includes another part of the decoding period T2. For example, in this embodiment, while the word line WL is enabled (the second precharge period tPRE_2), the channel gate transistor controlled by the bit line address signal YSA<3:0> is not Turn on to isolate signal lines such as the regional bit line LBL from the global bit line GBL. Then, in the third precharge period tPRE_3, the unselected bit lines and data lines are discharged, and in the fourth precharge period tPRE_4, the selected bit lines (for example, the target area bit lines) are precharged.

Therefore, in this embodiment, during the first precharge period tPRE_1, a part of the bit lines except the local bit line LBL is precharged. Compared with the prior art, the third precharge period can be reduced. The sum of the time length of tPRE_3 and the fourth precharge period tPRE_4, speeds up the reading speed.

FIG. 7 is a schematic diagram of a precharge circuit according to an embodiment of the invention. 2 and 7, in this embodiment, the pre-charge circuit 700 includes a plurality of channel gate transistor circuits 710_1, 710_2 to 710_N, a plurality of sense amplifier circuits 720_1, 720_2 to 720_N, and a pre-charge transistor circuit 730 , Where N is a positive integer greater than 2. In this embodiment, each channel gate transistor circuit is controlled by address signals YSA, YSB, YSC, and includes a plurality of channel gate transistors 200. When the transistor in the channel gate transistor circuit is turned on, a precharge path can be established. Therefore, the unit cell current can flow from the precharge path to the corresponding regional bit line.

In this embodiment, the pre-charge transistor circuit 730 includes a first transistor 731 and a second transistor 732. The first terminal of the first transistor 731 is coupled to the system voltage VCC. The second end of the first transistor 731 is coupled to the second end of the second transistor 732. The control terminal of the first transistor 731 is coupled to the precharge signal Vpre. The second end of the second transistor 732 is coupled to the corresponding channel gate transistor circuit. The control terminal of the second transistor 732 is coupled to the voltage signal. In this embodiment, during the decoding period T3, the precharge signal Vpre is used to cut off the precharge path. The voltage signal Vb is a specific voltage used to limit the source terminal of the second transistor 732 to the charging potential of the bit line. In one embodiment, the pre-charge transistor circuit 730 can also be implemented in the sense amplifier circuit, and the invention is not limited thereto.

FIG. 8 shows a flowchart of steps of a method of operating a memory storage device according to an embodiment of the present invention. Please refer to FIG. 1, FIG. 2 and FIG. 8. The operation method of the memory storage device of this embodiment is at least applicable to the memory storage device 100 of FIG. 1 and FIG. 2, but the present invention is not limited. Taking the memory storage device 100 of FIGS. 1 and 2 as an example, in step S100, the memory storage device 100 receives and decodes the segment signal S to perform a read operation on the target segment in the memory cell array 110 . In step S110, the memory storage device 100 enables the word line WL, and while enabling the word line WL, a part or all of the bit lines are precharged. In addition, the operation method of the memory storage device of the embodiment of the present invention can obtain sufficient teaching, suggestion, and implementation description from the description of the embodiment in FIG. 1 to FIG. 7, so it will not be repeated.

To sum up, in the exemplary embodiment of the present invention, the memory controller will simultaneously activate part or all of the bit lines and data lines while enabling the word lines and/or while decoding the segment signals. Perform a pre-charge operation to speed up the reading speed of the memory storage device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧Memory storage device 110‧‧‧Memory cell array 120‧‧‧Memory controller 130‧‧‧Character line decoder 140‧‧‧Bitline decoder 200‧‧‧Channel gate Crystal 700‧‧‧Precharge circuit 710_1, 710_2, 710_N‧‧‧Channel gate transistor circuit 720_1, 720_2, 720_N‧‧‧Sense amplifier circuit 730‧‧‧Precharge transistor circuit 731,732‧‧‧Transistor WL‧‧‧Character line BL‧‧‧Bit line LBL‧‧‧Regional bit line GBL‧‧‧Global bit line LDL‧‧‧Regional data line GDL‧‧‧Global data line S‧‧‧Segment Signal YSA, YSA<3 0>, YSA[0], YSA[1], YSA[2], YSA[3], YSB, YSB<3 0>, YSB[0], YSB[1], YSB[2 ], YSB[3], YSC, YSC<3 0>, YSC[0]‧‧‧Bit line address signal CLK‧‧‧Clock signal DI‧‧‧Input signal DO‧‧‧Output signal D0, D1 ,D2‧‧‧Output data Vb‧‧‧Voltage signal Vpre‧‧‧Precharge signal Vref‧‧‧Reference voltage VCC‧‧‧System voltage Aa, Ab‧‧‧Segment address Ac, Ad‧‧‧Character line Address Ae, Af‧‧‧Bit line address Ag‧‧‧Sensor address t_Y-Line‧‧‧Start time

T1, T2, T3, T4, T5: during decoding

tPRE_1: The first precharge period

tPRE_2: The second precharge period

tPRE_3: The third precharge period

tPRE_4: The fourth precharge period

S100, S110: method steps

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of the combination of the bit line and the channel gate transistor in the embodiment of FIG. 1. FIG. 3 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to an embodiment of the present invention. 4 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. 5 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. 6 is a schematic diagram showing the timing of each signal during a read operation of the memory storage device according to another embodiment of the present invention. FIG. 7 is a schematic diagram of a precharge circuit according to an embodiment of the invention. FIG. 8 shows a flowchart of steps of a method of operating a memory storage device according to an embodiment of the present invention.

S100, S110‧‧‧Method steps

Claims (11)

A memory storage device includes: a plurality of character lines, a plurality of data lines, and a plurality of bit lines, wherein the data lines are coupled to the bit lines; a memory cell array includes a plurality of memories Volume cells for storing data, wherein each of the memory cells is coupled to a corresponding word line and bit line; and a memory controller for performing a read operation on the memory cell array , Wherein while the memory controller decodes the word line address to select the target word line, and before the memory controller decodes the bit line address to select the target bit line, the memory The body controller performs a precharge operation on part or all of the bit lines, where the bit lines include multiple regional bit lines and multiple global bit lines, and the data lines include Multiple regional data lines and multiple global data lines, and when the memory controller performs the precharge operation on a part of the bit lines, the global bit lines, the regional data lines, and These global data lines are pre-charged. The memory storage device described in the first item of the patent application, wherein the memory controller receives and decodes a segment signal, and while the memory controller decodes the segment signal, the memory controls The processor performs the precharge operation on part or all of the bit lines. For the memory storage device described in item 1 of the scope of patent application, when the memory controller performs the precharge operation on all bit lines of the bit lines, the The regional bit lines, the global bit lines, the regional data lines, and the global data lines are precharged. The memory storage device described in claim 1, wherein after the memory controller enables the word lines, the unselected bit lines among the bit lines are discharged. The memory storage device according to claim 1, wherein after the memory controller enables the word lines, the voltage of the selected bit line among the bit lines is in a sensing period It was kept before. The memory storage device described in claim 1, wherein the memory controller enables the word lines at the same time, and the memory controller decodes the bit line address to select Before the target bit line, the memory controller performs the precharge operation on the bit lines of the part of the bit lines, wherein after the memory controller enables the word lines, the bit lines The selected bit line among the cell lines is precharged, and the selected bit line is not the part of the bit line. In the memory storage device described in the first item of the patent application, the regional bit lines are isolated while the memory controller enables the word lines. The memory storage device described in claim 1, wherein the memory controller decodes a segment signal during a first decoding period, and during a second decoding period, the memory controller The word line address is decoded, and during the first decoding period and a part of the second decoding period, the memory controller performs the precharge operation on a part of the bit lines of the bit lines. The memory storage device according to claim 1, wherein the memory storage device further includes: a precharge circuit for performing the precharge operation on part or all of the bit lines , Wherein the precharge circuit includes a plurality of channel gate transistor circuits, a plurality of sense amplifier circuits and a precharge transistor circuit, wherein each of the channel gate transistor circuits is coupled to the corresponding bit line and the corresponding bit line Between the sense amplifier circuits and controlled by an address signal, and when the address signal turns on the corresponding channel gate transistor circuit, the precharge transistor circuit establishes a precharge path, and a cell current Flow from the precharge path to the corresponding bit line. The memory storage device according to claim 9, wherein the pre-charge transistor circuit includes: a first transistor having a first terminal, a second terminal and a control terminal, wherein the first transistor The first end of the crystal is coupled to a system voltage, and the control end of the first transistor is coupled to a precharge signal; and a second transistor having a first end, a second end, and a Control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the corresponding channel gate transistor circuit, And the control terminal of the second transistor is coupled to a voltage signal, wherein in a third decoding period, the precharge signal cuts off the precharge path. A memory storage device includes: multiple character lines and multiple bit lines; A memory cell array includes a plurality of memory cells for storing data, wherein each of the memory cells is coupled to a corresponding word line and bit line; and a memory controller for receiving And decode a segment signal, and perform a read operation on the memory cell array. In a first decoding period, the memory controller decodes the segment signal, and in a second decoding period, The memory controller decodes the word line address, and during the first decoding period and a part of the second decoding period, the memory controller decodes a part of the bit lines of the bit lines Perform a precharge operation.

Images