TWI706434B - Method for processing interconnection structure to minimize sidewall recess of barrier layer - Google Patents

Abstract

The present invention provides a method for processing an interconnection structure for minimizing barrier sidewall recess. The method comprises the following steps:Step 1, remove a metal layer to generate a uniform dishing value inside the recessed area, the uniform dishing value is generated to make sure that the top surface of the metal layer in the recessed area is aligned with the bottom surface of the hard mask layer. Step 2, introduce noble-gas-halogen compound gas to remove a first barrier layer on top surface and at least a portion of a second barrier layer on sidewall by a gas phase chemical reaction process, the top surface of the second barrier layer on sidewall is aligned with the bottom surface of the hard mask layer. Step 3, introduce oxidizing gas to generate a barrier surface oxide on the top surface of the second barrier layer on sidewall, a metal surface oxide is generated at the same time. Step 4, introduce noble-gas-halogen compound gas to remove hard mask layer by a gas phase chemical reaction process. Step 5, reduce or remove the metal surface oxide.

Description

Method for processing interconnection structure to minimize sidewall recess of barrier layer

The present invention relates to semiconductor manufacturing, and more particularly to a method for processing interconnect structures to minimize the recesses in the sidewall of the barrier layer.

In the semiconductor manufacturing process, with the improvement of integrated circuit manufacturing process and the increase of wafer integration, copper interconnects have replaced aluminum interconnects as the main three-dimensional interconnects in super-large integrated circuits.

As the density of transistors increases, copper and low-k dielectric materials have gradually become mainstream technologies for interconnect structures. However, the integration of copper and low-k dielectric materials has many technical problems to be solved in practical applications, such as the problem of recessed sidewalls of the barrier layer. Figure 1 shows a cross-sectional view of a typical interconnect structure. The metal layer on the barrier layer has been removed and the same depression value has been produced. As shown in FIG. 1, from bottom to top, the interconnection structure includes a substrate 101, an insulating layer 102, a first dielectric layer 103, a second dielectric layer 104, a hard mask layer 105, and a barrier layer. The interconnect structure also includes a metal layer 108 in the recessed area 109. The first dielectric layer 103 is a low-k dielectric layer, and the barrier layer is used to prevent metal from diffusing into the low-k dielectric material. The barrier layer can be defined as the first barrier layer 106 on the top surface and the second barrier layer 107 on the sidewalls. The top surface of the metal layer 108 divides the second barrier layer 107 on the sidewall into two parts: an upper part and a lower part. The top first barrier layer 106 The upper part of the second barrier layer 107 on the sidewall and the sidewall is exposed, and the lower part of the second barrier layer 107 on the sidewall is non-exposed. The exposed barrier layer in the interconnect structure will be removed in a subsequent step.

At present, the CMP (Chemical Mechanical Polishing) process is a conventional method for removing the barrier layer. However, the CMP process has many harmful effects on the underlying structure of the interconnect structure due to relatively strong mechanical forces. Especially when the k value of the dielectric material becomes smaller and smaller, the mechanical force may cause permanent damage to the dielectric material, and the dielectric material may be scratched by the CMP process.

In order to overcome the shortcomings of the CMP process, a more advanced technology-vapor phase etching technology is used to remove the barrier layer. The vapor phase etching technology uses chemical gases to react with the barrier layer at a specific temperature and pressure. For more details about the vapor phase etching, please refer to the patent application No. PCT/CN2008/072059. Since no mechanical stress is generated during the entire etching process, there is no damage to low-k dielectric materials. However, as the line width continues to decrease, new barrier materials such as cobalt and ruthenium are used to replace traditional barrier materials, such as tantalum, tantalum nitride, titanium, and titanium nitride, and the thickness of the barrier layer becomes more It becomes thinner and thinner, which increases the difficulty of vapor phase etching. As shown in Figure 2, in the chemical reaction process of vapor phase etching, if the end point is not accurately controlled, the second barrier layer 107 on the sidewall may be overetched, and undesired sidewalls may be generated between the dielectric layer and the metal layer 108. The recess 110, once the second barrier layer 107 on the sidewall is over-etched, the metal in the recessed area 109 diffuses to the low-k dielectric layer.

As shown in FIG. 2, generally, the barrier layer is a tantalum and tantalum nitride layer, and the hard mask layer 105 is a titanium nitride layer. The bare barrier layer and the hard mask layer 105 are all subjected to a chemical vapor phase at a specific temperature. It is removed during the reaction process. by The chemical reaction process in the gas phase is isotropic. The etching speed of titanium nitride is lower than that of tantalum nitride at the operating temperature. If the hard mask layer 105 is completely removed, the second barrier layer 107 on the sidewall will be Was overshot. When the gas phase chemical reaction process is over, the result shows that the top surface of the second barrier layer 107 on the sidewall is much lower than the top surface of the metal layer 108, so a sidewall recess 110 is formed, which may cause leakage, and the service life of the device will be reduced. shorten.

The present invention proposes a method for processing an interconnect structure to minimize the sidewall recesses of the barrier layer. The method includes the following steps: Step 1, removing the metal layer to produce the same recess value in the recessed area so that the top of the metal layer in the recessed area The surface is aligned with the bottom surface of the hard mask layer; step 2, the introduction of halogen-noble element compound gas, the use of a gas phase chemical reaction process to remove the first barrier layer on the top surface and at least a portion of the second barrier layer on the sidewall, so that the sidewall The top surface of the second barrier layer is aligned with the bottom surface of the hard mask layer; step 3, oxidizing gas is introduced to oxidize the surface of the barrier layer on the top surface of the second barrier layer on the sidewall, and the metal layer in the recessed area Oxidation of the surface of the metal layer is generated on the top surface; step 4, introducing halogen-noble element compound gas, and removing the hard mask layer by a gas phase chemical reaction process; step 5, reducing or removing the surface oxidation of the metal layer.

In summary, the present invention introduces oxidizing gas to produce surface oxidation of the barrier layer on the top surface of the second barrier layer on the sidewalls to prevent the second barrier layer on the sidewalls from being overetched, thereby improving or even overcoming the sidewall depression of the barrier layer. The problem of progress.

101: Substrate

102: insulating layer

103: The first dielectric layer

104: second dielectric layer

105: hard mask layer

106: first barrier layer

107: second barrier layer

108: metal layer

109: recessed area

110: Sidewall recessed

401: Substrate

402: Insulation layer

403: first dielectric layer

404: second dielectric layer

405: Hard mask layer

406: first barrier

407: second barrier

408: Metal layer

409: recessed area

411: Surface oxidation of barrier layer

412: Surface oxidation of metal layer

601: Substrate

602: insulating layer

603: first dielectric layer

604: second dielectric layer

605: hard mask layer

606: first barrier

607: second barrier

608: Metal layer

609: recessed area

611: Surface oxidation of barrier layer

612: Surface oxidation of metal layer

In order to make the present invention more comprehensible to those skilled in the art, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which: FIG. 1 is a cross-sectional view of the interconnection structure of the prior art; FIG. 2 is the interconnection shown in FIG. A cross-sectional view of the barrier layer on the sidewall of the interconnection structure being over-etched and producing a recessed sidewall of the barrier layer; FIG. 3 is a flowchart of a method for processing an interconnect structure to minimize the sidewall recession of the barrier layer according to an embodiment of the present invention; 4 is a cross-sectional view of the interconnect structure of an embodiment of the present invention; FIG. 5 is a cross-sectional view of the interconnect structure of an embodiment of the present invention after the same depression value is generated; FIG. 6 is a bare barrier of the interconnect structure of an embodiment of the present invention Figure 7 is a cross-sectional view of the interconnect structure of an embodiment of the present invention after introducing oxidizing gas; Figure 8 is a cross-sectional view of the interconnect structure of an embodiment of the present invention after the hard mask layer is removed; Figure 9 It is a cross-sectional view of the interconnect structure of an embodiment of the present invention after reducing gas is introduced; FIG. 10 is a flowchart of a method for processing the interconnect structure to minimize the sidewall recess of the barrier layer according to another embodiment of the present invention; FIG. 11 is the present invention A cross-sectional view of an interconnection structure according to another embodiment of the invention; 12 is a cross-sectional view of the interconnect structure of another embodiment of the present invention after the same depression value is generated; FIG. 13 is a cross-sectional view of the interconnect structure of another embodiment of the present invention after the exposed barrier layer is removed; FIG. 14 is another of the present invention A cross-sectional view of the interconnect structure of an embodiment after introducing oxidizing gas; FIG. 15 is a cross-sectional view of the interconnect structure of another embodiment of the present invention after the hard mask layer is removed; FIG. 16 is an interconnection of another embodiment of the present invention A cross-sectional view of the surface of the metal layer of the structure after oxidation is removed; FIG. 17 is a flowchart of a method for processing the interconnect structure to minimize the sidewall recess of the barrier layer.

In order to solve the technical problems of the prior art, the present invention proposes a method for processing the interconnection structure to minimize the sidewall recess of the barrier layer. The method is operated in a process chamber and the interconnection structure is located on the surface of the wafer.

FIGS. 3 to 9 illustrate a method of processing an interconnect structure to minimize recesses in the sidewall of the barrier layer according to an embodiment of the present invention.

FIG. 3 is a flowchart of a method for processing an interconnect structure to minimize recesses in the sidewall of the barrier layer. The method includes the following steps: Step 301: Remove the metal layer 408 to produce the same recess value in the recessed area 409 to make the recess The top surface of the metal layer 408 in the entrance area 409 is aligned with the bottom surface of the hard mask layer 405; Step 302: Introduce a halogen-noble element compound gas, and use a gas phase chemical reaction process to remove the first barrier layer 406 on the top surface and the second barrier layer 407 on at least a part of the sidewalls so that the top of the second barrier layer 407 on the sidewalls The surface is aligned with the bottom surface of the hard mask layer 405; Step 303: Introduce oxidizing gas to cause the top surface of the second barrier layer 407 on the sidewall to oxidize the surface of the barrier layer 411, while recessing the top surface of the metal layer 408 in the region 409 Generate metal layer surface oxidation 412; step 304: introduce halogen-noble element compound gas, and use gas phase chemical reaction process to remove hard mask layer 405; step 305: reduce metal layer surface oxidation 412.

FIG. 4 is a cross-sectional view of an interconnection structure according to an embodiment of the invention. As shown in FIG. 4, from bottom to top, the interconnection structure includes a substrate 401, an insulating layer 402, a first dielectric layer 403, a second dielectric layer 404, a hard mask layer 405, and a barrier layer. The interconnect structure also includes a metal layer 408 above the barrier layer and in the recessed area 409. The first dielectric layer 403 is a low-k dielectric layer, and the second dielectric layer 404 is a TEOS layer. The barrier layer may be defined as the first barrier layer 406 on the top surface and the second barrier layer 407 on the sidewalls. It is well known that the barrier layer is used to prevent metal from diffusing into the low-k dielectric material of the interconnect structure. The material of the first barrier layer 406 on the top surface and the second barrier layer 407 on the sidewalls is ruthenium. In other specific embodiments, the barrier layer may be one or two layers, and its material is tantalum, tantalum nitride, ruthenium, cobalt, tungsten, tungsten nitride, hafnium, or the like. The hard mask layer 405 is a titanium nitride layer. The metal layer 408 above the barrier layer and located in the recessed area is copper.

，取決於阻擋層和硬掩膜層的厚度。凹進區域409內的金屬層408的頂面最好與硬掩膜層405的底面齊平。在本實施例中，每個凹進區域409內的凹陷值為400

，並且凹進區域409內的金屬層408的頂面與硬掩膜層405的底面齊平。換言之，凹進區域409內的金屬層408的頂面與第二介質層404的頂面齊平。由於產生了相同的凹陷，側壁上的第二阻擋層407被剩餘的金屬層408的頂面分為兩部分：上部和下部。SFP工藝完成後，側壁上的第二阻擋層407的上部是裸露的，側壁上的第二阻擋層407的下部是非裸露的，因此，頂面上裸露的第一阻擋層406和側壁上裸露的第二阻擋層407需要在後續步驟中去除。 Figure 5 shows a cross-sectional view of the interconnect structure after the same depression value is generated. In step 301, the metal layer 408 in the recessed area 409 is removed by a stress-free polishing (SFP) process. The SFP process is a stress-free polishing process that uses electrolytic polishing to remove copper, so there is no damage to the low-k dielectric layer. The metal layer 408 in the recessed area is removed through the SFP process, but the barrier layer is not removed. Therefore, the same recess value is generated in the recessed area 409, and the recess value can be 0-1000

, Depends on the thickness of the barrier layer and the hard mask layer. The top surface of the metal layer 408 in the recessed area 409 is preferably flush with the bottom surface of the hard mask layer 405. In this embodiment, the recess value in each recessed area 409 is 400

, And the top surface of the metal layer 408 in the recessed area 409 is flush with the bottom surface of the hard mask layer 405. In other words, the top surface of the metal layer 408 in the recessed area 409 is flush with the top surface of the second dielectric layer 404. Due to the same depression, the second barrier layer 407 on the sidewall is divided into two parts by the top surface of the remaining metal layer 408: an upper part and a lower part. After the SFP process is completed, the upper part of the second barrier layer 407 on the sidewall is exposed, and the lower part of the second barrier layer 407 on the sidewall is non-exposed. Therefore, the exposed first barrier layer 406 on the top surface and the exposed sidewall The second barrier layer 407 needs to be removed in a subsequent step.

FIG. 6 shows that the second barrier layer 407 exposed on the sidewall and the first barrier layer 406 exposed on the top surface are removed by a gas phase chemical reaction process in step 302. In this embodiment, the thickness of the second barrier layer 407 on the sidewall is the same as the thickness of the first barrier layer 406 on the top surface. In addition, the gas phase chemical reaction process is isotropic, so after introducing the halogen-noble element compound gas into the process chamber, the upper part of the second barrier layer 407 on the sidewall will be removed, and the first barrier layer 406 on the top surface will also be removed. Is removed. After the gas phase chemical reaction process is completed, the first barrier layer 406 on the top surface is completely removed, so no barrier layer remains on the top surface of the hard mask layer 405, and after the gas phase chemical reaction process, the hard mask layer 405 is exposed. In order to solve the problem of recessed sidewalls of the barrier layer, the gas phase chemical reaction process in step 302 needs to be precisely controlled by the end point control mechanism to remove the exposed second barrier layer 407 on the sidewalls and the non-exposed second barrier layer 407 on the sidewalls. It is flush with the bottom surface of the hard mask layer 405. The endpoint control mechanism controls the gas phase chemical reaction process through the length of time.

The process conditions of the gas phase chemical reaction process in step 302 are set as follows: the operating temperature is from room temperature to 400° C., the gas flow rate of the halogen-noble element compound gas is from 2 sccm to 100 sccm, and the operating pressure is from 5 mTorr to 20 Torr. The halogen-noble element compound gas in step 302 can be any of the following: XeF ₂ , XeF ₄ , XeF ₆ or KrF ₂ . Inert gases, such as neon and argon, can also be used as carrier gas to be introduced into the process chamber together with halogen-noble element compound gas.

In this embodiment, the process conditions of the gas phase chemical reaction process in step 302 are as follows: the operating temperature is 110°C, the gas flow rate of the halogen-noble element compound gas is 6 sccm, the operating pressure is 4 Torr, and the halogen-noble element compound gas is XeF ₂ . Under these conditions, the time to complete the gas phase chemical reaction process is 50s. Since XeF _2. does not react with copper and low-k materials, the low-k materials will not be damaged, and the electrical performance and life of integrated circuit devices will be improved.

FIG. 7 is a cross-sectional view of the interconnect structure after the oxidizing gas is introduced in step 303. In this embodiment, the oxidizing gas is O ₂ . In step 303, after O _{2 is} introduced into the process chamber, the top surface of the second barrier layer 407 on the sidewall and the top surface of the remaining metal layer 408 in the recessed area 409 will be oxidized, so the second barrier on the sidewall The top surface of the layer 407 will generate surface oxidation 411 of the barrier layer, while the top surface of the metal layer 408 in the recessed area 409 will generate surface oxidation 412 of the metal layer. The surface oxide 411 of the barrier layer and the surface oxide 412 of the metal layer are both very thick. The surface oxide 411 of the barrier layer helps prevent the second barrier layer 407 on the sidewall from being further etched in the next step, so no sidewall recess of the barrier layer will be generated. The surface oxide 412 of the metal layer is an undesirable copper surface oxide layer, so it needs to be processed in a subsequent process.

In step 303, O ₂ can be introduced under the following conditions: the operating temperature is 150° C.-400° C., the O ₂ gas flow rate is 0.1-20 slm, and the operating pressure is 200 Torr-800 Torr. The operating temperature is very important. If the operating temperature is lower than 150°C, no significant oxidation will occur on the barrier layer. In addition, if the operating temperature is higher than 400°C, the interconnect structure will be damaged by thermal stress. At the same time, the oxidation threshold temperature of titanium nitride is 800° C., so the hard mask layer 405 will not be oxidized at the current temperature. In step 303 of this embodiment, O ₂ is introduced under the following conditions: the operating temperature is 180° C., the gas flow rate of O ₂ is 20 slm, the operating pressure is 1 atm, and the process time is 60 s.

FIG. 8 shows a cross-sectional view of the interconnect structure after the hard mask layer is removed in step 304 according to an embodiment of the present invention. In step 304, a halogen-noble element compound gas is introduced into the process chamber to remove the hard mask layer 405. The halogen-noble element compound gas is XeF ₂ . Since the top surface of the second barrier layer 407 on the sidewall is protected by the barrier layer surface oxidation 411, and the hard mask layer 405 of titanium nitride is not oxidized, at the end of the gas phase chemical reaction process in step 304, only the hard mask The film 405 is removed by XeF ₂ . The second barrier layer 407 on the sidewall is not further etched in the gas phase chemical reaction process in step 304, which avoids the problem of recessed sidewalls of the barrier layer.

According to experimental data, there is a positive correlation between the etching rate and temperature of titanium nitride. Therefore, in order to obtain better effects and etching efficiency, the process conditions of the gas phase chemical reaction process in step 304 are slightly different from the process conditions of the gas phase chemical reaction process in step 302. The process conditions of the gas phase chemical reaction process in step 304 are as follows: the operating temperature is 150°C-400°C, the gas flow rate of the halogen-noble element compound gas is 2 sccm-100 sccm, and the operating pressure is 5 mTorr-20 Torr. Inert gas, such as neon or argon, can also be used as a carrier gas to be introduced into the process chamber together with halogen-noble element compound gas.

FIG. 9 is a cross-sectional view of the interconnection structure after introduction of reducing gas in step 305 according to an embodiment of the present invention. The top surface of the metal layer 408 should be copper instead of copper surface oxide, so the surface oxide 412 of the metal layer needs to be processed. In step 305, a reducing gas is introduced into the process chamber to reduce the surface oxidation 412 of the metal layer. The reducing gas is a mixture of nitrogen and hydrogen, and the proportion of hydrogen is less than 4%, which is safer. After introducing the reducing gas into the process chamber, the surface oxide 412 of the metal layer is reduced to copper. After the reducing gas is introduced, the top surface of the second barrier layer 407 on the sidewall still has the surface oxidation 411 of the barrier layer, but it has little effect on subsequent processes.

FIGS. 10 to 16 disclose a method for processing an interconnect structure to minimize recesses in the sidewall of the barrier layer and an interconnect structure according to another embodiment of the present invention.

Fig. 10 is a flow chart of a method for processing an interconnect structure to minimize the sidewall recesses of the barrier layer. The method includes the following steps: Step 501: Remove the metal layer 608 to produce the same depression value in the recessed area 609, so that the top surface of the metal layer 608 in the recessed area 609 is aligned with the bottom surface of the hard mask layer 605; Step 502: Introduce halogen-noble elements The compound gas is used to remove the first barrier layer 606 on the top surface and the second barrier layer 607 on at least a part of the sidewalls by a gas phase chemical reaction process, so that the top surface of the second barrier layer 607 on the sidewalls and the hard mask layer 605 Align the bottom surface; Step 503: Introduce an oxidizing gas to cause the top surface of the second barrier layer 607 on the sidewall to produce the surface oxidation 611 of the barrier layer, while the top surface of the metal layer 608 in the recessed area 609 produces the surface oxidation 612 of the metal layer; Step 504: Introduce a halogen-noble element compound gas, and remove the hard mask layer 605 by a gas phase chemical reaction process; step 505: remove the surface oxide 612 of the metal layer.

FIG. 11 is a cross-sectional view of an interconnection structure according to another embodiment of the present invention. As shown in FIG. 11, from bottom to top, the interconnect structure includes a substrate 601, an insulating layer 602, a first dielectric layer 603, a second dielectric layer 604, a hard mask layer 605, and a barrier layer. The interconnect structure also includes a metal layer 608 above the barrier layer and in the recessed area 609. The first dielectric layer 603 is a low-k dielectric layer, and the second dielectric layer 604 is a TEOS layer. The barrier layer may be defined as the first barrier layer 606 on the top surface and the second barrier layer 607 on the sidewalls. It is well known that the barrier layer is used to prevent metal from diffusing into the low-k dielectric material of the interconnect structure. The first barrier layer 606 on the top surface and the second barrier layer 607 on the sidewalls are tantalum and tantalum nitride layers. In other specific embodiments, the barrier layer material may be ruthenium, cobalt, or the like. The hard mask layer 605 is a titanium nitride layer. Above the barrier and in the recessed area The metal layer 608 is copper.

，取決於阻擋層和硬掩膜層的厚度。凹進區域609內的金屬層608的頂面最好與硬掩膜層605的底面齊平。在本實施例中，每個凹進區域609內的凹陷值為100

，並且凹進區域609內的金屬層608的頂面與硬掩膜層605的底面齊平。換言之，凹進區域609內的金屬層608的頂面與第二介質層604的頂面齊平。由於產生相同的凹陷，側壁上的第二阻擋層607被剩餘的金屬層608的頂面分為兩部分：上部和下部。CMP工藝完成後，側壁上的第二阻擋層607的上部是裸露的，側壁上的第二阻擋層607的下部是非裸露的，因此，頂面上裸露的第一阻擋層606和側壁上裸露的第二阻擋層607需要在後續步驟中去除。 FIG. 12 shows a cross-sectional view of the interconnect structure according to another embodiment of the present invention after the same depression value is generated. Since the recess value in this embodiment is not very large, in step 501, the metal layer 608 in the recessed region 609 can also be removed by a CMP process. The metal layer 608 in the recessed area 609 is removed by the CMP process, but the barrier layer will not be removed. Therefore, the same recess value is generated in the recessed area 609, and the recess value can be 0-100

, Depends on the thickness of the barrier layer and the hard mask layer. The top surface of the metal layer 608 in the recessed area 609 is preferably flush with the bottom surface of the hard mask layer 605. In this embodiment, the recess value in each recessed area 609 is 100

, And the top surface of the metal layer 608 in the recessed area 609 is flush with the bottom surface of the hard mask layer 605. In other words, the top surface of the metal layer 608 in the recessed area 609 is flush with the top surface of the second dielectric layer 604. Due to the same depression, the second barrier layer 607 on the sidewall is divided into two parts by the top surface of the remaining metal layer 608: an upper part and a lower part. After the CMP process is completed, the upper part of the second barrier layer 607 on the sidewall is exposed, and the lower part of the second barrier layer 607 on the sidewall is not exposed. Therefore, the exposed first barrier layer 606 on the top surface and the exposed sidewall The second barrier layer 607 needs to be removed in a subsequent step.

FIG. 13 shows a cross-sectional view of the second barrier layer 607 exposed on the sidewall and the first barrier layer 606 exposed on the top surface after being removed by the gas phase chemical reaction process in step 502. In this embodiment, the thickness of the second barrier layer 607 on the sidewall is thicker than the thickness of the first barrier layer 606 on the top surface. In addition, the gas phase chemical reaction process is isotropic, so after introducing the halogen-noble element compound gas into the process chamber, the upper part of the second barrier layer 607 on the sidewall Will be removed, but only a part of the first barrier layer 606 on the top surface is removed. The first barrier layer 606 on the top surface is not completely removed, so there is still a barrier layer remaining on the top surface of the hard mask layer 605. Therefore, the hard mask layer 605 on the top surface is not exposed while the hard mask layer 605 on the sidewalls is exposed. In order to solve the problem of the recessed side wall of the barrier layer, the gas phase chemical reaction process in step 502 needs to be precisely controlled by the end point control mechanism to remove the exposed second barrier layer 607 on the sidewall and the non-exposed second barrier layer 607 on the sidewall. It is flush with the bottom surface of the hard mask layer 605. The endpoint control mechanism controls the gas phase chemical reaction process by detecting changes in reflectivity.

The process conditions of the gas phase chemical reaction process in step 502 can be set as follows: the operating temperature is room temperature to 400° C., the gas flow rate of the halogen-noble element compound gas is 2 sccm to 100 sccm, and the operating pressure is 5 mTorr to 10 Torr. The halogen-noble element compound gas in step 502 may be a mixture of at least two of the following gases: XeF ₂ , XeF ₄ , XeF ₆ or KrF ₂ . Inert gases, such as neon and argon, can also be used as carrier gas to be introduced into the process chamber together with halogen-noble element compound gas.

In this embodiment, the process conditions of the gas phase chemical reaction process in step 502 are as follows: the operating temperature is 400°C, the gas flow rate of the halogen-noble element compound gas is 100 sccm, the operating pressure is 20 Torr, and the halogen-noble element compound gas is XeF ₂ and KrF ₂ . Under these conditions, the time to complete the gas phase chemical reaction process in step 502 is 40 seconds. Since XeF ₂ and KrF ₂ do not react with copper and low-k materials, the low-k materials will not be damaged, and the electrical performance and lifetime of the integrated circuit device will be improved.

FIG. 14 is a cross-sectional view of the interconnection structure after the oxidizing gas is introduced in step 503. In this embodiment, the oxidizing gas is O ₃ . In step 503, after O _{3 is} introduced into the process chamber, the top surface of the second barrier layer 607 on the sidewall and the top surface of the remaining metal layer 608 in the recessed area 609 will be oxidized. In addition, the remaining barrier layer on the top surface of the hard mask layer 605 is also oxidized. The top surface of the second barrier layer 607 on the sidewall will generate surface oxidation 611 of the barrier layer, and meanwhile, the top surface of the metal layer 608 in the recessed area 609 will generate surface oxidation 612 of the metal layer. The surface oxide 611 of the barrier layer and the surface oxide 612 of the metal layer are both very thick. The surface oxide 611 of the barrier layer helps prevent the second barrier layer 607 on the sidewall from being further etched in the next step, so that no sidewall recess of the barrier layer is generated. The surface oxide 612 of the metal layer is an undesirable copper surface oxide layer, so subsequent processing is required.

In step 503, O ₃ is introduced under the following conditions: the operating temperature is 150° C.-400° C., the O ₃ gas flow rate is 0-20 slm, and the operating pressure is 200 Torr-800 Torr. The operating temperature is very important. If the operating temperature is lower than 150°C, no significant oxidation will occur on the barrier layer. In addition, if the operating temperature is higher than 400°C, the interconnect structure will be damaged by thermal stress. At the same time, the oxidation threshold temperature of titanium nitride is 800° C., so under the current conditions, the hard mask layer 605 will not be oxidized. In step 503 of this embodiment, O ₃ is introduced under the following conditions: the operating temperature is 150° C., the gas flow rate of O ₃ is 10 slm, and the operating pressure is 200 Torr.

FIG. 15 shows a cross-sectional view of the interconnect structure after the hard mask layer 605 is removed in step 504 according to another embodiment of the present invention. In step 504, a halogen-noble element compound gas is introduced into the process chamber to remove the hard mask layer 605. The halogen-noble element compound gas is a mixture of at least two of the following gases: XeF ₂ , XeF ₄ , XeF ₆ or KrF ₂ . An inert gas, such as neon or argon, can also be used as a carrier gas and introduced into the process chamber along with the halogen-noble element compound gas. Since the top surface of the second barrier layer 607 on the sidewall is protected by the surface oxidation 611 of the barrier layer, and the hard mask layer 605 of titanium nitride is not oxidized, at the end of the gas phase chemical reaction process in step 504, the hard mask The film layer 605 will be removed from the sidewall by the halogen-noble element compound gas, and the oxidized barrier layer residue is removed along with the hard mask layer 605. The second barrier layer 607 is not further etched in the gas phase chemical reaction process in step 504, which avoids the problem of recessed sidewalls of the barrier layer.

According to experimental data, there is a positive correlation between the etching rate and temperature of titanium nitride. Therefore, in order to obtain better effects and etching efficiency, the process conditions of the gas phase chemical reaction process in step 504 are slightly different from the process conditions of the gas phase chemical reaction process in step 502. The process conditions of the gas phase chemical reaction process in step 504 are as follows: the operating temperature is 150° C.-400° C., the gas flow rate of the halogen-noble element compound gas is 2 sccm-100 sccm, and the operating pressure is 5 mTorr-20 Torr.

FIG. 16 is a cross-sectional view of the interconnect structure after the surface oxide 612 of the metal layer is removed in step 505 according to another embodiment of the present invention. The top surface of the metal layer 608 should be copper instead of copper surface oxide, so the surface oxide 612 of the metal layer needs to be processed. In step 505, the oxidation 612 on the surface of the metal layer is removed by washing with a citric acid solution, the citric acid is diluted with deionized water, and the concentration of the citric acid solution is 1%-2%. After the citric acid solution is cleaned, the surface oxidation 612 of the metal layer is removed. The surface oxide 611 of the barrier layer still exists on the top surface of the second barrier layer 607 on the sidewall, but it has a very significant impact on subsequent processes. small.

In summary, the present invention discloses a method for processing an interconnect structure to minimize the sidewall recess of the barrier layer. As shown in FIG. 17, the method includes: Step 1: Remove the metal layer to produce the same in the recessed area The recess value aligns the top surface of the metal layer in the recessed area with the bottom surface of the hard mask layer; Step 2: Introduce halogen-noble element compound gas, and use a gas phase chemical reaction process to remove the first barrier layer and the bottom surface of the hard mask layer. At least a part of the second barrier layer on the sidewall is aligned with the top surface of the second barrier layer on the sidewall and the bottom surface of the hard mask layer; Step 3: Introduce oxidizing gas to make the top surface of the second barrier layer on the sidewall The surface of the barrier layer is oxidized, and the top surface of the metal layer in the recessed area is oxidized; Step 4: Introduce halogen-noble element compound gas, and use a gas phase chemical reaction process to remove the hard mask layer; Step 5: Reduce or remove the surface oxidation of the metal layer.

The above are only the preferred embodiments of the present invention, and do not limit the present invention in any form. Anyone familiar with the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

401: Substrate

402: Insulation layer

403: first dielectric layer

404: second dielectric layer

405: Hard mask layer

407: second barrier

408: Metal layer

409: recessed area

411: Surface oxidation of barrier layer

412: Surface oxidation of metal layer

Claims (14)

A method for processing an interconnection structure to minimize recesses in the sidewalls of a barrier layer is characterized in that it includes: step 1, removing the metal layer to produce the same recess value in the recessed area so that the top of the metal layer located in the recessed area The surface is aligned with the bottom surface of the hard mask layer; step 2, the halogen-noble element compound gas is introduced, and the first barrier layer on the top surface and at least a part of the second barrier layer on the sidewall are removed by a gas phase chemical reaction process to make The top surface of the second barrier layer on the sidewall is aligned with the bottom surface of the hard mask layer; step 3, the introduction of oxidizing gas causes the top surface of the second barrier layer on the sidewall to oxidize the surface of the barrier layer, and the recessed area The top surface of the metal layer generates surface oxidation of the metal layer; step 4, introduces halogen-noble element compound gas, and uses a gas phase chemical reaction process to remove the hard mask layer; step 5, reduces or removes the surface oxidation of the metal layer. The method according to claim 1, wherein the oxidizing gas is O ₂ or O ₃ . The method according to claim 1, wherein the halogen-noble element compound gas is any one of the following: XeF ₂ , XeF ₄ , XeF ₆ or KrF ₂ . The method according to claim 1, characterized in that the halogen-noble element compound gas is a mixture of at least two of the following gases: XeF ₂ , XeF ₄ , XeF ₆ or KrF ₂ . The method according to claim 1, characterized in that the barrier layer is one or two layers, and its material is tantalum, tantalum nitride, ruthenium, cobalt, tungsten, tungsten nitride or hafnium. The method according to claim 1, wherein the material of the hard mask layer is titanium nitride. The method according to claim 1, wherein the gas phase chemical reaction process is controlled by an endpoint control mechanism. The method according to claim 1, wherein the range of the depression value is 0

-1000

. The method according to claim 2, characterized in that the conditions for introducing O ₂ or O ₃ in step 3 are as follows: operating temperature is 150°C-400°C, gas flow rate is 0-20 slm, and operating pressure is 200 Torr-800 Torr. The method according to claim 1, characterized in that the process conditions of the gas phase chemical reaction process in step 2 are as follows: the operating temperature is from room temperature to 400°C, the gas flow rate of the halogen-noble element compound gas is 2sccm-100sccm, and the operation The pressure is 5mTorr-20Torr. The method according to claim 1, characterized in that the process conditions of the gas phase chemical reaction process in step 4 are as follows: the operating temperature is 150°C-400°C, the gas flow rate of the halogen-noble element compound gas is 2sccm-100sccm, and the operation The pressure is 5mTorr-20Torr. The method according to claim 1, wherein in step 5, the surface oxidation of the metal layer is reduced by a reducing gas. The method according to claim 1, wherein in step 5, the surface oxidation of the metal layer is cleaned and removed with a citric acid solution. The method according to claim 13, wherein in step 5, the citric acid is diluted with deionized water, and the concentration of the citric acid solution is 1%-2%.

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