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TWI706206B - Pixel structure - Google Patents

Pixel structure Download PDF

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Publication number
TWI706206B
TWI706206B TW108108964A TW108108964A TWI706206B TW I706206 B TWI706206 B TW I706206B TW 108108964 A TW108108964 A TW 108108964A TW 108108964 A TW108108964 A TW 108108964A TW I706206 B TWI706206 B TW I706206B
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layer
electrode
auxiliary
substrate
contact hole
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TW108108964A
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Chinese (zh)
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TW202036129A (en
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黃勝揚
陳鵬聿
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友達光電股份有限公司
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Priority to TW108108964A priority Critical patent/TWI706206B/en
Priority to CN201910996056.XA priority patent/CN110718573B/en
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Publication of TWI706206B publication Critical patent/TWI706206B/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/805Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/122Pixel-defining structures or layers, e.g. banks

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

A pixel structure includes an active device, a first planarization layer, an auxiliary electrode, a second planarization layer, and a light emitting device. The active device is on a substrate. The active device includes a drain and a source. The first planarization layer is on the active device. The auxiliary electrode is on the first planarization layer. The second planarization layer is on the auxiliary electrode and the first planarization layer. The light emitting device includes a first electrode layer, an active layer, and a second electrode layer sequentially disposed on the substrate. The first electrode layer is on the second planarization layer and is electrically connected to the drain or the source through the first through hole. The second electrode layer is electrically connected to the auxiliary electrode the through the second through hole.

Description

畫素結構 Pixel structure

本揭露是關於一種畫素結構。 This disclosure is about a pixel structure.

有機電致發光裝置是一種自發光性(Emissive)之顯示器。由於有機電致發光裝置具有廣視角、高應答速度(約為液晶的百倍以上)、重量輕、可隨硬體設備小型化及薄型化、高發光效率、高演色性(Color rendering index)以及面光源等特性。因此,有機電致發光裝置具有極大的發展潛力,可望成為下一世代的新穎平面顯示器。 The organic electroluminescence device is a self-luminous (Emissive) display. Because organic electroluminescence devices have wide viewing angles, high response speeds (about a hundred times that of liquid crystals), light weight, miniaturization and thinning with hardware equipment, high luminous efficiency, high color rendering index and surface Light source and other characteristics. Therefore, organic electroluminescent devices have great development potential and are expected to become the next generation of novel flat panel displays.

上發光(top emission)顯示為目前普遍應用在有機電致發光裝置的顯示技術之一,以提高畫素的開口率。然而,傳統的上發光顯示技術具有薄電極厚度的製作難度高、電極阻值高以及當有機電致發光裝置朝向大尺寸發展時有嚴重電源電壓降(IR drop)等問題,這將會造成主動矩陣有機發光二極體(AMOLED)面板用的發光元件陣列的亮度不均。為了有效降低電源電壓降,增設輔助電極則成為解決問題之另一個選擇,但是輔助電極的增設往往會使元件佈局面積大幅度的增加,而導致開口率的損失。 Top emission display is currently one of the display technologies commonly used in organic electroluminescence devices to increase the aperture ratio of pixels. However, the traditional top-emitting display technology has high difficulty in manufacturing thin electrode thickness, high electrode resistance, and serious power supply voltage drop (IR drop) when organic electroluminescent devices are developed toward large sizes, which will cause active The brightness of the array of light-emitting elements for matrix organic light-emitting diode (AMOLED) panels is uneven. In order to effectively reduce the power supply voltage drop, the addition of auxiliary electrodes has become another option to solve the problem. However, the addition of auxiliary electrodes will often greatly increase the layout area of the device, resulting in a loss of aperture ratio.

本揭露之實施例提供一種畫素結構,畫素結構具有第二平坦層,如此一來,使第一電極層在具有良好平坦度的表面上形成,從而提升發光元件之發光均勻度。第一電極層鄰近輔助電極的一部分藉由第二平坦層墊高而比輔助電極更遠離基板,而有利於製程時斷開第一電極層及輔助電極之間的電性連接,解決第一電極層及輔助電極間短路的問題,從而提升製程的良率及穩定性,並因此可縮短第一電極層及輔助電極沿第一方向之水平距離以及沿第二方向之水平距離,藉此提升開口率。畫素結構更具有位於輔助洞中的畫素電極之第一部,藉此可縮短第一電極層及輔助電極沿第一方向之水平距離以及沿第二方向之水平距離,藉此提升開口率。 The embodiment of the present disclosure provides a pixel structure, which has a second flat layer, so that the first electrode layer is formed on a surface with good flatness, thereby improving the uniformity of light emission of the light-emitting element. A part of the first electrode layer adjacent to the auxiliary electrode is further away from the substrate than the auxiliary electrode due to the height of the second flat layer, which facilitates the disconnection of the electrical connection between the first electrode layer and the auxiliary electrode during the manufacturing process, thereby solving the problem of the first electrode The problem of short-circuit between the layer and the auxiliary electrode, thereby improving the yield and stability of the process, and thus shortening the horizontal distance between the first electrode layer and the auxiliary electrode in the first direction and the horizontal distance in the second direction, thereby increasing the opening rate. The pixel structure further has the first part of the pixel electrode located in the auxiliary hole, thereby shortening the horizontal distance between the first electrode layer and the auxiliary electrode in the first direction and the horizontal distance in the second direction, thereby increasing the aperture ratio .

於一實施例中,一種畫素結構包括主動元件、第一平坦層、輔助電極、第二平坦層以及發光元件。主動元件位於基板上,其中主動元件包括汲極與源極。第一平坦層位於主動元件上。輔助電極位於第一平坦層上。第二平坦層位於輔助電極與第一平坦層上。發光元件包括依序設置於基板上的第一電極層、主動層與第二電極層,第一電極層位於第二平坦層上,並透過第一接觸洞電性連接汲極或源極,第二電極層透過第二接觸洞電性連接輔助電極。 In one embodiment, a pixel structure includes an active element, a first flat layer, an auxiliary electrode, a second flat layer, and a light-emitting element. The active device is located on the substrate, and the active device includes a drain and a source. The first flat layer is located on the active element. The auxiliary electrode is located on the first flat layer. The second flat layer is located on the auxiliary electrode and the first flat layer. The light-emitting element includes a first electrode layer, an active layer, and a second electrode layer sequentially disposed on a substrate. The first electrode layer is located on the second flat layer and is electrically connected to the drain or source through the first contact hole. The two electrode layers are electrically connected to the auxiliary electrode through the second contact hole.

於一實施例中,一種畫素結構包括主動元件、第一平坦層、輔助電極、發光元件以及畫素定義層(PDL)。主動元件位於基板上,主動元件包括汲極。第一平坦層位於主動元件上。輔助電極位於第一平坦層上。發光元件包括依序設置於 基板上的第一電極層、主動層與第二電極層,其中第一電極層透過第一接觸洞與汲極電性連接。畫素定義層位於第一電極層上,並具有第一部位於輔助洞內,輔助洞與第一接觸洞彼此間隔一距離。 In one embodiment, a pixel structure includes an active device, a first flat layer, an auxiliary electrode, a light emitting device, and a pixel definition layer (PDL). The active element is located on the substrate, and the active element includes a drain. The first flat layer is located on the active element. The auxiliary electrode is located on the first flat layer. The light-emitting elements include The first electrode layer, the active layer and the second electrode layer on the substrate, wherein the first electrode layer is electrically connected to the drain through the first contact hole. The pixel definition layer is located on the first electrode layer, and has a first part located in the auxiliary hole, and the auxiliary hole and the first contact hole are separated by a distance.

10、10a、10b‧‧‧畫素結構 10, 10a, 10b‧‧‧Pixel structure

100‧‧‧基板 100‧‧‧Substrate

102‧‧‧輔助電極 102‧‧‧Auxiliary electrode

104‧‧‧畫素定義層 104‧‧‧Pixel definition layer

106‧‧‧發光元件 106‧‧‧Light-emitting element

108‧‧‧第一電極層 108‧‧‧First electrode layer

108P‧‧‧部分 108P‧‧‧Part

110‧‧‧畫素開口區 110‧‧‧Pixel opening area

112‧‧‧主動元件 112‧‧‧Active Components

114‧‧‧第一平坦層 114‧‧‧First flat layer

116‧‧‧第二平坦層 116‧‧‧Second flat layer

118‧‧‧閘極 118‧‧‧Gate

120‧‧‧閘極絕緣層 120‧‧‧Gate insulation layer

122‧‧‧半導體層 122‧‧‧Semiconductor layer

124‧‧‧層間介電層 124‧‧‧Interlayer dielectric layer

126‧‧‧汲極 126‧‧‧Dip pole

128‧‧‧源極 128‧‧‧Source

130‧‧‧汲極區 130‧‧‧Dip pole area

132‧‧‧源極區 132‧‧‧Source Region

134‧‧‧通道區 134‧‧‧Access area

136‧‧‧無機絕緣層 136‧‧‧Inorganic insulating layer

138‧‧‧主動層 138‧‧‧Active layer

140‧‧‧第二電極層 140‧‧‧Second electrode layer

142‧‧‧容置空間 142‧‧‧Accommodation space

144‧‧‧電子傳輸層 144‧‧‧Electron transport layer

146‧‧‧電洞傳輸層 146‧‧‧Hole Transmission Layer

148‧‧‧電洞注入層 148‧‧‧hole injection layer

150‧‧‧電子注入層 150‧‧‧Electron injection layer

152‧‧‧第一子層 152‧‧‧First sub-layer

154‧‧‧第二子層 154‧‧‧Second sub-layer

1040‧‧‧第一部 1040‧‧‧Part 1

1040a‧‧‧頂部 1040a‧‧‧Top

1040b‧‧‧底部 1040b‧‧‧Bottom

1042‧‧‧第二部 1042‧‧‧Part 2

AH‧‧‧輔助洞 AH‧‧‧Auxiliary hole

D1‧‧‧第一方向 D1‧‧‧First direction

D2‧‧‧第二方向 D2‧‧‧Second direction

H‧‧‧段差 H‧‧‧Segment difference

HS1、HS2、HS3、HS4‧‧‧水平距離 HS1, HS2, HS3, HS4‧‧‧Horizontal distance

L1‧‧‧長度 L1‧‧‧Length

L2‧‧‧延伸長度 L2‧‧‧Extended length

L3‧‧‧延伸長度 L3‧‧‧Extended length

O‧‧‧開口 O‧‧‧Open

T1、T2‧‧‧厚度 T1, T2‧‧‧Thickness

TH1‧‧‧第一接觸洞 TH1‧‧‧First contact hole

TH2‧‧‧第二接觸洞 TH2‧‧‧Second contact hole

W1、W2、W3、W4、W5、W6、W7‧‧‧寬度 W1, W2, W3, W4, W5, W6, W7‧‧‧Width

閱讀以下詳細敘述並搭配對應之圖式,可了解本揭露之多個樣態。需留意的是,圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上,所述之特徵的尺寸可以任意的增加或減少以利於討論的清晰性。 Read the following detailed description and match the corresponding drawings to understand many aspects of this disclosure. It should be noted that many of the features in the drawing are not drawn in actual proportions according to the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion.

第1A圖為根據一實施例之畫素結構的俯視圖;第1B圖為沿第1A圖的線段Y-Y’的剖面示意圖;第1C圖為沿第1A圖的線段X-X’的剖面示意圖;第2A圖為根據另一實施例之畫素結構的俯視圖;第2B圖為沿第2A圖的線段Y-Y’的剖面示意圖;第2C圖為沿第2A圖的線段X-X’的剖面示意圖;第3A圖為根據另一實施例之畫素結構的俯視圖;第3B圖為沿第3A圖的線段Y-Y’的剖面示意圖;以及第3C圖為沿第3A圖的線段X-X’的剖面示意圖。 Figure 1A is a top view of a pixel structure according to an embodiment; Figure 1B is a schematic cross-sectional view along the line Y-Y' of Figure 1A; Figure 1C is a schematic cross-sectional view along the line X-X' of Figure 1A Figure 2A is a top view of a pixel structure according to another embodiment; Figure 2B is a schematic cross-sectional view along the line Y-Y' of Figure 2A; Figure 2C is a cross-sectional view along the line X-X' of Figure 2A Fig. 3A is a top view of a pixel structure according to another embodiment; Fig. 3B is a schematic cross-sectional view along the line Y-Y' in Fig. 3A; and Fig. 3C is a schematic view along the line X- of Fig. 3A Schematic cross-section of X'.

以下將以圖式及詳細說明清楚說明本揭露之精神,任何所屬技術領域中具有通常知識者在瞭解本揭露之實施例後,當可由本揭露所教示之技術,加以改變及修飾,其並不 脫離本揭露之精神與範圍。舉例而言,敘述「第一特徵形成於第二特徵上方或上」,於實施例中將包含第一特徵及第二特徵具有直接接觸;且也將包含第一特徵和第二特徵為非直接接觸,具有額外的特徵形成於第一特徵和第二特徵之間。此外,本揭露在多個範例中將重複使用元件標號以和/或文字。重複的目的在於簡化與釐清,而其本身並不會決定多個實施例以和/或所討論的配置之間的關係。 The following will clearly illustrate the spirit of the present disclosure with drawings and detailed descriptions. Anyone with ordinary knowledge in the relevant technical field can change and modify the techniques taught in the present disclosure after understanding the embodiments of the present disclosure. Depart from the spirit and scope of this disclosure. For example, the statement that "the first feature is formed on or on the second feature" will include the first feature and the second feature having direct contact; and will also include the first feature and the second feature being indirect The contact has an additional feature formed between the first feature and the second feature. In addition, the present disclosure will reuse component numbers and/or text in multiple examples. The purpose of repetition is to simplify and clarify, and it does not determine the relationship between multiple embodiments and/or the discussed configurations.

此外,方位相對詞彙,如「在...之下」、「下面」、「下」、「上方」或「上」或類似詞彙,在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外,其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位),本文所用的方位相對詞彙同樣可以相應地進行解釋。 In addition, relative terms such as "below", "below", "below", "above" or "up" or similar terms are used in this article to facilitate the description of the words shown in the diagram The relationship of one element or feature to another element or feature. In addition to describing the position of the device in the diagram, the relative position vocabulary includes the different positions of the device under use or operation. When the device is additionally set (rotated by 90 degrees or other facing orientation), the relative terms of the orientation used in this article can also be explained accordingly.

第1A圖為根據一實施例之畫素結構10的俯視圖。請參照第1A圖,畫素結構10包括基板100、輔助電極102、畫素定義層(PDL)104以及發光元件106(未繪示)之第一電極層108。為方便解說,圖上省略其他元件。第一電極層108與輔助電極102配置於基板100上,其中第一電極層108與輔助電極102彼此相隔一距離且彼此電性絕緣,換句話說,第一電極層108在基板100的垂直投影與輔助電極102在基板100的垂直投影相隔一距離。畫素定義層104位於第一電極層108及輔助電極102上,畫素定義層104定義複數畫素開口區110,畫素開口區110具有長軸與短軸,長軸平行於第一方向D1,短軸平行於第 二方向D2,第一方向D1及第二方向D2正交,但本揭露不以此為限。基板100之材質例如是玻璃、石英、有機聚合物或是金屬等等,但不以此為限。 FIG. 1A is a top view of a pixel structure 10 according to an embodiment. Referring to FIG. 1A, the pixel structure 10 includes a substrate 100, an auxiliary electrode 102, a pixel definition layer (PDL) 104, and a first electrode layer 108 of a light emitting element 106 (not shown). For the convenience of explanation, other components are omitted from the figure. The first electrode layer 108 and the auxiliary electrode 102 are disposed on the substrate 100. The first electrode layer 108 and the auxiliary electrode 102 are separated from each other by a distance and are electrically insulated from each other. In other words, the vertical projection of the first electrode layer 108 on the substrate 100 It is separated from the vertical projection of the auxiliary electrode 102 on the substrate 100 by a distance. The pixel defining layer 104 is located on the first electrode layer 108 and the auxiliary electrode 102. The pixel defining layer 104 defines a plurality of pixel opening regions 110. The pixel opening regions 110 have a long axis and a short axis, and the long axis is parallel to the first direction D1 , The minor axis is parallel to the first The two directions D2, the first direction D1 and the second direction D2 are orthogonal, but the disclosure is not limited to this. The material of the substrate 100 is, for example, glass, quartz, organic polymer, metal, etc., but not limited thereto.

第1B圖為沿第1A圖的線段Y-Y’的剖面示意圖。第1C圖為沿第1A圖的線段X-X’的剖面示意圖。一併參照第1A圖至第1C圖,畫素結構10更包括依序配置於基板100上之主動元件112、第一平坦層114、第二平坦層116以及發光元件106。第一平坦層114位於主動元件112上,輔助電極102位於第一平坦層114上,第一平坦層114具有平整的表面,可使形成於其上的膜層(例如輔助電極102)具有低的粗糙度。舉例來說,第一平坦層114為具有絕緣性質的膜層,可例如為介電材料。第一平坦層114的材質可為無機材料、有機材料或其組合,無機材料例如是氧化矽、氮化矽、氮氧化矽、或上述至少二種材料的堆疊層。有機材料例如是聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂等高分子材料。 Figure 1B is a schematic cross-sectional view along the line Y-Y' of Figure 1A. Figure 1C is a schematic cross-sectional view taken along the line X-X' of Figure 1A. Referring to FIGS. 1A to 1C together, the pixel structure 10 further includes an active device 112, a first planar layer 114, a second planar layer 116 and a light emitting device 106 which are sequentially arranged on the substrate 100. The first flat layer 114 is located on the active device 112, and the auxiliary electrode 102 is located on the first flat layer 114. The first flat layer 114 has a flat surface, so that the film layer (such as the auxiliary electrode 102) formed thereon has a low Roughness. For example, the first flat layer 114 is a film layer with insulating properties, such as a dielectric material. The material of the first flat layer 114 can be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. The organic material is, for example, a polymer material such as polyimide resin, epoxy resin, or acrylic resin.

具體來說,主動元件112包括閘極118、閘極絕緣層120、半導體層122、層間介電層124、汲極126以及源極128。閘極118位於基板100上,閘極絕緣層120位於閘極118上,半導體層122位於閘極絕緣層120上,層間介電層124位於半導體層122上,半導體層122具有汲極區130、源極區132以及通道區134,且通道區134位於汲極區130以及源極區132之間。汲極126及源極128則位於層間介電層124上,並經由開口O而與汲極區130及源極區132連接。半導體層122的材質例如是非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導 體材料(例如:銦鋅氧化物、銦鍺鋅氧化物、或是其它合適的材料、或上述之組合)、或其它合適的材料、或含有摻雜物(dopant)於上述材料中、或上述之組合。第一電極層108位於第二平坦層116上,並透過第一接觸洞TH1電性連接源極128,從而,發光元件106受到主動元件112的控制。 Specifically, the active device 112 includes a gate electrode 118, a gate insulating layer 120, a semiconductor layer 122, an interlayer dielectric layer 124, a drain electrode 126, and a source electrode 128. The gate electrode 118 is located on the substrate 100, the gate insulating layer 120 is located on the gate electrode 118, the semiconductor layer 122 is located on the gate insulating layer 120, and the interlayer dielectric layer 124 is located on the semiconductor layer 122. The semiconductor layer 122 has a drain region 130, The source region 132 and the channel region 134 are located between the drain region 130 and the source region 132. The drain 126 and the source 128 are located on the interlayer dielectric layer 124 and are connected to the drain region 130 and the source region 132 through the opening O. The material of the semiconductor layer 122 is, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, and oxide semiconductor materials. Bulk materials (for example: indium zinc oxide, indium germanium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials, or containing dopants in the above materials, or the above的组合。 The combination. The first electrode layer 108 is located on the second flat layer 116 and is electrically connected to the source 128 through the first contact hole TH1, so that the light-emitting element 106 is controlled by the active element 112.

閘極118可為單層或多層,且其材料例如是金屬、金屬氧化物、有機導電材料或上述之組合。閘極絕緣層120可為單層或多層,且其材料包括氧化矽、氮化矽、氮氧化矽、其它合適的材料、或上述之組合。層間介電層124可為單層或多層結構,且材質可包括無機材料、有機材料、或其它合適的材料,其中無機材料例如包括(但不限於):氧化矽、氮化矽或氮氧化矽;有機材料例如包括(但不限於):聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂。在本實施例中,主動元件112例如為薄膜電晶體(thin film transistor,TFT),例如但不限於是頂閘極型薄膜電晶體、底閘極型薄膜電晶體或其它合適型式的薄膜電晶體。 The gate electrode 118 can be a single layer or multiple layers, and its material is, for example, a metal, a metal oxide, an organic conductive material, or a combination of the foregoing. The gate insulating layer 120 can be a single layer or multiple layers, and its material includes silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof. The interlayer dielectric layer 124 can be a single-layer or multi-layer structure, and the material can include inorganic materials, organic materials, or other suitable materials. The inorganic materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride. ; Organic materials for example include (but are not limited to): polyimide resins, epoxy resins or acrylic resins. In this embodiment, the active element 112 is, for example, a thin film transistor (TFT), such as but not limited to a top gate type thin film transistor, a bottom gate type thin film transistor or other suitable types of thin film transistors. .

於一實施例中,畫素結構10更包括無機絕緣層136位於層間介電層124及第一平坦層114之間,例如包括氮化矽、氧化矽或氧化鋁。 In one embodiment, the pixel structure 10 further includes an inorganic insulating layer 136 located between the interlayer dielectric layer 124 and the first planar layer 114, such as silicon nitride, silicon oxide, or aluminum oxide.

發光元件106還包括依序設置於基板100上的主動層138與第二電極層140,進一步而言,主動層138會經由第一電極層108與第二電極層140間產生的電壓差驅動而發出光。畫素定義層104具有容置空間142,其中主動層138之至少一部分位於容置空間142內。 The light-emitting element 106 further includes an active layer 138 and a second electrode layer 140 sequentially disposed on the substrate 100. Furthermore, the active layer 138 is driven by the voltage difference generated between the first electrode layer 108 and the second electrode layer 140. Emit light. The pixel definition layer 104 has an accommodation space 142, wherein at least a part of the active layer 138 is located in the accommodation space 142.

在本實施例中,發光元件106為上發光型有機發光顯示器,在此情況下,第一電極層108例如是反射電極。第二電極層140例如是穿透電極。第一電極層108可包括反射材料,所述反射材料例如是金屬、合金、透明金屬氧化物等導電材質、或是金屬與透明金屬氧化物導電材料之堆疊層,上述金屬例如是金、銀、鋁、鉬、銅、鈦、鉻、鎢或其它合適的金屬,然本揭露不限於此。第二電極層140亦可包括金屬、合金、透明金屬氧化物導電材料、或是金屬與透明金屬氧化物導電材料之堆疊層。上述透明金屬氧化物導電材料例如是銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鍺鋅氧化物或其它合適的金屬氧化物、或是上述至少二者之堆疊層,然本揭露不限於此。第一電極層108與第二電極層140可利用蒸鍍製程並搭配金屬遮罩(metal mask)來形成,然本揭露不限於此。舉例而言,第一電極層108與第二電極層140也可使用濺鍍製程來形成,或者是化學氣相沉積製程或物理氣相沉積並配合微影蝕刻製程或金屬遮罩來形成。在本實施例中,第一電極層108例如是陽極,以及第二電極層140例如是陰極,但必需說明的,第一電極層108與第二電極層140之陰、陽極與否,就以設計上的需求,而有所變動之。 In this embodiment, the light-emitting element 106 is a top-emission type organic light-emitting display. In this case, the first electrode layer 108 is, for example, a reflective electrode. The second electrode layer 140 is, for example, a penetration electrode. The first electrode layer 108 may include a reflective material, such as a conductive material such as a metal, an alloy, a transparent metal oxide, or a stacked layer of a metal and a transparent metal oxide conductive material, such as gold, silver, Aluminum, molybdenum, copper, titanium, chromium, tungsten or other suitable metals, but the present disclosure is not limited thereto. The second electrode layer 140 may also include a metal, an alloy, a transparent metal oxide conductive material, or a stacked layer of a metal and a transparent metal oxide conductive material. The transparent metal oxide conductive material is, for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide or other suitable metal oxides, or a stack of at least two of the foregoing However, this disclosure is not limited to this. The first electrode layer 108 and the second electrode layer 140 can be formed by an evaporation process and a metal mask, but the disclosure is not limited thereto. For example, the first electrode layer 108 and the second electrode layer 140 can also be formed using a sputtering process, or a chemical vapor deposition process or physical vapor deposition combined with a photolithography process or a metal mask. In this embodiment, the first electrode layer 108 is, for example, an anode, and the second electrode layer 140 is, for example, a cathode. However, it must be noted that whether the first electrode layer 108 and the second electrode layer 140 are cathode or anode is determined by The design requirements are subject to change.

輔助電極102可包括具有較低電阻率之導電材料例如銀、鋁、銅、鎂、鉬、上述材料之複合層或上述材料之合金,但並不以此為限。第二電極層140透過第二接觸洞TH2電性連接輔助電極102,藉由具有較低電阻率之輔助電極102與第二電極層140電性相接,可改善當第二電極層140因為需維持一 定之光穿透率而使用較薄之金屬材料或阻抗較高之透明導電材料時可能發生之電源電壓降(IR drop)的現象。 The auxiliary electrode 102 may include conductive materials with relatively low resistivity, such as silver, aluminum, copper, magnesium, molybdenum, composite layers of the foregoing materials, or alloys of the foregoing materials, but it is not limited thereto. The second electrode layer 140 is electrically connected to the auxiliary electrode 102 through the second contact hole TH2. By electrically connecting the auxiliary electrode 102 with a lower resistivity to the second electrode layer 140, it can be improved when the second electrode layer 140 needs Maintain one The phenomenon of power supply voltage drop (IR drop) that may occur when thinner metal materials or transparent conductive materials with higher impedance are used for a certain light transmittance.

第二平坦層116位於輔助電極102與第一平坦層114上,第一電極層108及輔助電極102透過第二平坦層116彼此電性絕緣,並且,第一電極層108的一部分108P比輔助電極102更遠離基板100,具體而言,第一電極層108鄰近輔助電極102的一部分108P藉由第二平坦層116墊高而比輔助電極102更遠離基板100,如此一來,有利於製程時斷開第一電極層108及輔助電極102之間的電性連接,解決第一電極層108及輔助電極102間短路的問題,從而提升製程的良率及穩定性,並因此可縮短第一電極層108及輔助電極102沿第一方向D1之水平距離HS1以及沿第二方向D2之水平距離HS2,其中,第一電極層108及輔助電極102之間沿第一方向D1相距之最小水平距離HS1介於約2.5微米至約5.5微米之間,第一電極層108及輔助電極102之間沿第二方向D2相距之最小水平距離HS2介於約2.5微米至約5.5微米之間,且第一接觸洞TH1與第二接觸洞TH2沿第一方向D1相距之最小水平距離HS3為約8.5微米至約11.5微米之間,輔助電極102及第一接觸洞TH1之間沿第一方向D1相距之最小水平距離HS4為約5.5微米至約8.5微米之間,如此一來,容置空間142沿第一方向D1之長度L1(即畫素開口區110之長軸)最多可以提升約6微米,沿第二方向D2之寬度W1(即畫素開口區110之短軸)最多可以提升約6微米,藉此提升畫素結構10的開口率,提供良好顯示品質。於一實施例中,畫素結構10的開口率最多可由約40%提升至約55%。 The second flat layer 116 is located on the auxiliary electrode 102 and the first flat layer 114. The first electrode layer 108 and the auxiliary electrode 102 are electrically insulated from each other through the second flat layer 116, and a part 108P of the first electrode layer 108 is larger than the auxiliary electrode. 102 is further away from the substrate 100. Specifically, a portion 108P of the first electrode layer 108 adjacent to the auxiliary electrode 102 is further away from the substrate 100 than the auxiliary electrode 102 due to the height of the second flat layer 116. As a result, it is beneficial to the interruption during the manufacturing process. Opening the electrical connection between the first electrode layer 108 and the auxiliary electrode 102 solves the problem of short circuit between the first electrode layer 108 and the auxiliary electrode 102, thereby improving the yield and stability of the process, and thus shortening the first electrode layer The horizontal distance HS1 between 108 and the auxiliary electrode 102 along the first direction D1 and the horizontal distance HS2 along the second direction D2, wherein the minimum horizontal distance HS1 between the first electrode layer 108 and the auxiliary electrode 102 along the first direction D1 is between Between about 2.5 microns and about 5.5 microns, the minimum horizontal distance HS2 between the first electrode layer 108 and the auxiliary electrode 102 along the second direction D2 is between about 2.5 microns and about 5.5 microns, and the first contact hole The minimum horizontal distance HS3 between TH1 and the second contact hole TH2 along the first direction D1 is between about 8.5 μm and about 11.5 μm, and the minimum horizontal distance between the auxiliary electrode 102 and the first contact hole TH1 along the first direction D1 HS4 is between about 5.5 microns and about 8.5 microns. As a result, the length L1 of the accommodating space 142 along the first direction D1 (that is, the long axis of the pixel opening area 110) can be increased by about 6 microns at most, along the second direction The width W1 of D2 (ie, the short axis of the pixel opening area 110) can be increased by about 6 microns at most, thereby increasing the opening ratio of the pixel structure 10 and providing good display quality. In one embodiment, the aperture ratio of the pixel structure 10 can be increased from about 40% to about 55% at most.

並且,第二平坦層116具有平整的表面,如此一來,透過第一平坦層114及第二平坦層116所組成之疊層,可以使第一電極層108在具有良好平坦度的表面上形成,使第一電極層108具有低的粗糙度,從而提升發光元件106之發光均勻度,提供良好顯示品質。第二平坦層116之材質可類似於第一平坦層114,於此不加以贅述。於一實施例中,第二平坦層116之厚度T2實質上大於第一平坦層114之厚度T1,舉例而言,第一平坦層114之厚度T1為約1微米至約3微米之間,第二平坦層116之厚度T2大於約3微米,如此一來,可以提升第一電極層108之平坦度,從而提升發光元件106之發光均勻度,提供良好顯示品質。 In addition, the second flat layer 116 has a flat surface. In this way, the first electrode layer 108 can be formed on a surface with good flatness through the stack of the first flat layer 114 and the second flat layer 116. , So that the first electrode layer 108 has a low roughness, thereby improving the uniformity of light emission of the light emitting element 106 and providing a good display quality. The material of the second flat layer 116 can be similar to that of the first flat layer 114, and will not be repeated here. In one embodiment, the thickness T2 of the second flat layer 116 is substantially greater than the thickness T1 of the first flat layer 114. For example, the thickness T1 of the first flat layer 114 is between about 1 micrometer and about 3 micrometers. The thickness T2 of the two flat layers 116 is greater than about 3 micrometers. In this way, the flatness of the first electrode layer 108 can be improved, thereby improving the uniformity of light emission of the light-emitting element 106 and providing good display quality.

舉例而言,主動層138可為白光發光材料層或是其他特定色光(例如紅光、綠光、藍光、紫外光等)之發光材料層。主動層138的形成方法例如是蒸鍍法、塗佈法、沈積法或其它合適的方法。在本實施例中,為了進一步提升發光元件106的發光效率,更設置電子傳輸層144與電洞傳輸層146。電子傳輸層144由電子傳輸材料所構成,例如是配置於主動層138與第二電極層140之間。電洞傳輸層146由電洞傳輸材料所構成,例如是配置於主動層138與第一電極層108之間。此外,還可進一步包括電洞注入層148。電洞注入層148由電洞注入材料所構成,例如是配置於第一電極層108與電洞傳輸層146之間。在另一實施例中,可進一步配置電子注入層150於第二電極層140與電子傳輸層144之間。然而,必須一提的是,電洞注入層148、電洞傳輸層146、電子傳輸層144以及電子注入層150的配置是 可選的,其亦可不存在於發光元件106中。在本實施例中是以發光元件106為上發光型為例,但本揭露不以此為限,在其他實施例中,若上述第一電極層108與第二電極層140兩者之材質皆採用透明導電材料,那麼所形成之有機電致發光裝置為雙面發光裝置。 For example, the active layer 138 may be a white light emitting material layer or a light emitting material layer of other specific colors (such as red light, green light, blue light, ultraviolet light, etc.). The method for forming the active layer 138 is, for example, an evaporation method, a coating method, a deposition method, or other suitable methods. In this embodiment, in order to further improve the luminous efficiency of the light emitting element 106, an electron transport layer 144 and a hole transport layer 146 are further provided. The electron transport layer 144 is made of an electron transport material, for example, is disposed between the active layer 138 and the second electrode layer 140. The hole transport layer 146 is made of a hole transport material, for example, is disposed between the active layer 138 and the first electrode layer 108. In addition, a hole injection layer 148 may be further included. The hole injection layer 148 is made of a hole injection material, for example, is disposed between the first electrode layer 108 and the hole transport layer 146. In another embodiment, an electron injection layer 150 may be further disposed between the second electrode layer 140 and the electron transport layer 144. However, it must be mentioned that the configuration of the hole injection layer 148, the hole transport layer 146, the electron transport layer 144 and the electron injection layer 150 is Optionally, it may not exist in the light-emitting element 106. In this embodiment, the light-emitting element 106 is an up-emitting type as an example, but the disclosure is not limited to this. In other embodiments, if the materials of the first electrode layer 108 and the second electrode layer 140 are both Using transparent conductive materials, the formed organic electroluminescent device is a double-sided light emitting device.

第2A圖為根據另一實施例之畫素結構10a的俯視圖。第2B圖為沿第2A圖的線段Y-Y’的剖面示意圖。第2C圖為沿第2A圖的線段X-X’的剖面示意圖。必須說明的是,第2A圖至第2C圖之實施例沿用第1A圖至第1C圖之實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。 FIG. 2A is a top view of a pixel structure 10a according to another embodiment. Figure 2B is a schematic cross-sectional view taken along the line Y-Y' of Figure 2A. Figure 2C is a schematic cross-sectional view taken along the line X-X' of Figure 2A. It must be noted that the embodiments in Figures 2A to 2C follow the component numbers and part of the content of the embodiments in Figures 1A to 1C, and the same reference numbers are used to denote the same or similar components, and the same is omitted. Description of technical content. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

本實施例的畫素結構10a與第1A圖至第1C圖的實施例的畫素結構10相似,兩者的差異在於:畫素結構10a不具有第二平坦層116,畫素定義層104具有第一部1040及第二部1042,第一部1040位於輔助洞AH內,輔助電極102透過位於輔助洞AH內的畫素定義層104之第一部1040與第一電極層108電性絕緣,輔助洞AH與第一接觸洞TH1彼此間隔一距離,輔助電極102與基板100之間的距離實質上相同於位於第一平坦層114上的第一電極層108與基板100之間的距離。於部分實施例中,第一電極層108及輔助電極102例如為透過同一道微影及蝕刻製程來製作。換言之,第一電極層108及輔助電極102屬於同一層圖案化薄膜,且第一電極層108以及輔助電極102具有實質上相同之材料以及實質上相同之厚度。輔助洞AH沿 第一方向D1之寬度W2為約3微米至約5.5微米之間,輔助洞AH沿第二方向D2之寬度W3為約3微米至約5.5微米之間。如此一來,有利於蝕刻製程時斷開第一電極層108及輔助電極102之間的電性連接,不會因蝕刻不完全的殘留造成第一電極層108與輔助電極102電性連接,解決第一電極層108及輔助電極102間短路的問題,從而提升製程的良率及穩定性。並因此可縮短第一電極層108及輔助電極102沿第一方向D1之水平距離HS1以及沿第二方向D2之水平距離HS2,其中,第一電極層108及輔助電極102之間沿第一方向D1相距之最小水平距離HS1介於約3微米至約5.5微米之間,第一電極層108及輔助電極102之間沿第二方向D2相距之最小水平距離HS2介於約3微米至約5.5微米之間,且第一接觸洞TH1與第二接觸洞TH2沿第一方向D1相距之最小水平距離HS3為約9微米至約11.5微米之間,輔助電極102及第一接觸洞TH1之間沿第一方向D1相距之最小水平距離HS4為約6微米至約8.5微米之間,如此一來,容置空間142沿第一方向D1之長度L1(即畫素開口區110之長軸)最多可以提升約5微米,沿第二方向D2之寬度W1(即畫素開口區110之短軸)最多可以提升約5微米,藉此提升畫素結構10a的開口率,提供良好顯示品質。於一實施例中,畫素結構10a的開口率最多可由約40%提升至約52%。第二部1042透過第一接觸洞TH1接觸第一電極層108的側壁,且第二部1042朝著基板100的延伸長度L2大於第一部1040朝著基板100的延伸長度L3。 The pixel structure 10a of this embodiment is similar to the pixel structure 10 of the embodiment of FIG. 1A to FIG. 1C. The difference between the two is that the pixel structure 10a does not have the second flat layer 116, and the pixel definition layer 104 has The first part 1040 and the second part 1042, the first part 1040 is located in the auxiliary hole AH, the auxiliary electrode 102 is electrically insulated from the first electrode layer 108 through the first part 1040 of the pixel definition layer 104 located in the auxiliary hole AH, The auxiliary hole AH and the first contact hole TH1 are separated from each other by a distance, and the distance between the auxiliary electrode 102 and the substrate 100 is substantially the same as the distance between the first electrode layer 108 on the first flat layer 114 and the substrate 100. In some embodiments, the first electrode layer 108 and the auxiliary electrode 102 are manufactured through the same lithography and etching process, for example. In other words, the first electrode layer 108 and the auxiliary electrode 102 belong to the same patterned film, and the first electrode layer 108 and the auxiliary electrode 102 have substantially the same material and substantially the same thickness. Auxiliary hole AH along The width W2 of the first direction D1 is between about 3 μm and about 5.5 μm, and the width W3 of the auxiliary hole AH along the second direction D2 is between about 3 μm and about 5.5 μm. In this way, it is beneficial to disconnect the electrical connection between the first electrode layer 108 and the auxiliary electrode 102 during the etching process, and the first electrode layer 108 and the auxiliary electrode 102 will not be electrically connected due to the residue of incomplete etching. The problem of short circuit between the first electrode layer 108 and the auxiliary electrode 102 improves the yield and stability of the process. Therefore, the horizontal distance HS1 between the first electrode layer 108 and the auxiliary electrode 102 along the first direction D1 and the horizontal distance HS2 along the second direction D2 can be shortened, wherein the distance between the first electrode layer 108 and the auxiliary electrode 102 along the first direction The minimum horizontal distance HS1 between D1 is between about 3 μm and about 5.5 μm, and the minimum horizontal distance HS2 between the first electrode layer 108 and the auxiliary electrode 102 along the second direction D2 is between about 3 μm and about 5.5 μm. The minimum horizontal distance HS3 between the first contact hole TH1 and the second contact hole TH2 along the first direction D1 is between about 9 μm and about 11.5 μm. The auxiliary electrode 102 and the first contact hole TH1 are along the first The minimum horizontal distance HS4 from one direction D1 is between about 6 microns and about 8.5 microns. As a result, the length L1 of the accommodating space 142 along the first direction D1 (ie the long axis of the pixel opening area 110) can be increased at most About 5 microns, the width W1 along the second direction D2 (ie, the short axis of the pixel opening area 110) can be increased by about 5 microns at most, thereby increasing the aperture ratio of the pixel structure 10a and providing good display quality. In one embodiment, the aperture ratio of the pixel structure 10a can be increased from about 40% to about 52% at most. The second portion 1042 contacts the sidewall of the first electrode layer 108 through the first contact hole TH1, and the extension length L2 of the second portion 1042 toward the substrate 100 is greater than the extension length L3 of the first portion 1040 toward the substrate 100.

第3A圖為根據另一實施例之畫素結構10b的俯視圖。第3B圖為沿第3A圖的線段Y-Y’的剖面示意圖。第3C圖為 沿第3A圖的線段X-X’的剖面示意圖。此必須說明的是,第3A圖至第3C圖之實施例沿用第2A圖至第2C圖之實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。本實施例的畫素結構10b與第2A圖至第2C圖的實施例的畫素結構10a相似,兩者的差異在於:本實施例之第一平坦層114包括第一子層152與第二子層154,第二子層154位於第一子層152上,透過設置第二子層154,可以提升第一電極層108之平坦度,從而提升發光元件106之發光均勻度,提供良好顯示品質,其中第一接觸洞TH1貫穿第一子層152及第二子層154,輔助洞AH貫穿第一子層152及第二子層154。如此一來,可確保蝕刻製程時不會因蝕刻殘留可完全斷開第一電極層108及輔助電極102之間的電性連接,解決第一電極層108及輔助電極102間短路的問題,從而提升製程的良率及穩定性,並因此可縮短第一電極層108及輔助電極102沿第一方向D1之水平距離HS1以及沿第二方向D2之水平距離HS2,其中,第一電極層108及輔助電極102之間沿第一方向D1相距之最小水平距離HS1介於約3微米至約5.5微米之間,第一電極層108及輔助電極102之間沿第二方向D2相距之最小水平距離HS2介於約3微米至約5.5微米之間,且第一接觸洞TH1與第二接觸洞TH2沿第一方向D1相距之最小水平距離HS3為約9微米至約11.5微米之間,輔助電極102及第一接觸洞TH1之間沿第一方向D1相距之最小水平距離HS4為約6微米至約8.5微米之間,如此一來,容置空間142沿第一方向D1之 長度L1(即畫素開口區110之長軸)最多可以提升約5微米,沿第二方向D2之寬度W1(即畫素開口區110之短軸)最多可以提升約5微米,藉此提升畫素結構10b的開口率,提供良好顯示品質。於一實施例中,畫素結構10b的開口率最多可由約40%提升至約52%。 FIG. 3A is a top view of a pixel structure 10b according to another embodiment. Figure 3B is a schematic cross-sectional view taken along the line Y-Y' of Figure 3A. Figure 3C shows A schematic cross-sectional view along the line X-X' in Figure 3A. It must be noted that the embodiments in Figures 3A to 3C follow the component numbers and part of the content of the embodiments in Figures 2A to 2C, in which the same reference numbers are used to denote the same or similar components, and the omitted Description of the same technical content. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here. The pixel structure 10b of this embodiment is similar to the pixel structure 10a of the embodiment of FIG. 2A to FIG. 2C. The difference between the two is: the first flat layer 114 of this embodiment includes a first sublayer 152 and a second sublayer 152 The sub-layer 154 and the second sub-layer 154 are located on the first sub-layer 152. By providing the second sub-layer 154, the flatness of the first electrode layer 108 can be improved, thereby improving the light emission uniformity of the light-emitting element 106 and providing good display quality , Wherein the first contact hole TH1 penetrates the first sublayer 152 and the second sublayer 154, and the auxiliary hole AH penetrates the first sublayer 152 and the second sublayer 154. In this way, it can be ensured that the electrical connection between the first electrode layer 108 and the auxiliary electrode 102 will not be completely disconnected due to etching residue during the etching process, and the problem of the short circuit between the first electrode layer 108 and the auxiliary electrode 102 can be solved, thereby Improve the yield and stability of the process, and therefore shorten the horizontal distance HS1 between the first electrode layer 108 and the auxiliary electrode 102 along the first direction D1 and the horizontal distance HS2 along the second direction D2, where the first electrode layer 108 and The minimum horizontal distance HS1 between the auxiliary electrodes 102 along the first direction D1 is between about 3 microns and about 5.5 microns, and the minimum horizontal distance HS2 between the first electrode layer 108 and the auxiliary electrodes 102 along the second direction D2 Between about 3 microns and about 5.5 microns, and the minimum horizontal distance HS3 between the first contact hole TH1 and the second contact hole TH2 along the first direction D1 is between about 9 microns and about 11.5 microns, the auxiliary electrode 102 and The minimum horizontal distance HS4 between the first contact holes TH1 along the first direction D1 is between about 6 microns and about 8.5 microns. As a result, the accommodating space 142 along the first direction D1 The length L1 (that is, the long axis of the pixel opening area 110) can be increased by about 5 microns at most, and the width W1 (that is, the short axis of the pixel opening area 110) along the second direction D2 can be increased by about 5 microns, thereby enhancing the picture The aperture ratio of the element structure 10b provides good display quality. In one embodiment, the aperture ratio of the pixel structure 10b can be increased from about 40% to about 52% at most.

於一實施例中,第一子層152之側壁與第二子層154之側壁間具有沿第一方向D1之段差H,具體而言,位於輔助洞AH中的畫素定義層104之第一部1040具有階梯狀,舉例而言,第一部1040具有頂部1040a及底部1040b,頂部1040a位於底部1040b之上,頂部1040a夾於第二子層154之間且接觸第二子層154之側壁,底部1040b夾於第一子層152之間且接觸第一子層152之側壁。於一實施例中,頂部1040a沿第一方向D1之寬度W4以及沿第二方向D2之寬度W5為約3微米至約5.5微米之間,底部1040b沿第一方向D1之寬度W6小於或頂部1040a沿第一方向D1之寬度W4,底部1040b沿第二方向D2之寬度W7小於或頂部1040a沿第二方向D2之寬度W5,底部1040b沿第一方向D1之寬度W6以及沿第二方向D2之寬度W7為約3微米至約5.5微米之間,如此一來,藉由段差H之設計,段差H可用以容置製程時斷掉的導體層(例如第一電極層108及輔助電極102),避免第一電極層108及輔助電極102齊平而連結在一起,如此一來,可確保蝕刻製程時斷開第一電極層108及輔助電極102之間的電性連接,不會因蝕刻不完全的殘留造成第一電極層108與輔助電極102電性連接,解決第一電極層108及輔助電極102間短路的問題。於其他實施例中,底部 1040b沿第一方向D1之寬度W6可實質上等於頂部1040a沿第一方向D1之寬度W4,底部1040b沿第二方向D2之寬度W7可實質上等於頂部1040a沿第二方向D2之寬度W5。 In one embodiment, there is a step H along the first direction D1 between the sidewall of the first sublayer 152 and the sidewall of the second sublayer 154. Specifically, the first pixel definition layer 104 in the auxiliary hole AH The portion 1040 has a stepped shape. For example, the first portion 1040 has a top 1040a and a bottom 1040b, the top 1040a is located on the bottom 1040b, and the top 1040a is sandwiched between the second sublayers 154 and contacts the sidewalls of the second sublayers 154. The bottom 1040b is sandwiched between the first sublayers 152 and contacts the sidewalls of the first sublayers 152. In one embodiment, the width W4 of the top 1040a along the first direction D1 and the width W5 along the second direction D2 are between about 3 microns and about 5.5 microns, and the width W6 of the bottom 1040b along the first direction D1 is smaller than or the width W6 of the top 1040a Along the width W4 of the first direction D1, the width W7 of the bottom 1040b in the second direction D2 is smaller than or the width W5 of the top 1040a in the second direction D2, and the width W6 of the bottom 1040b in the first direction D1 and width W6 in the second direction D2 W7 is between about 3 microns and about 5.5 microns. In this way, by the design of the step H, the step H can be used to accommodate the conductor layers (such as the first electrode layer 108 and the auxiliary electrode 102) that are broken during the manufacturing process. The first electrode layer 108 and the auxiliary electrode 102 are flush and connected together. In this way, it can be ensured that the electrical connection between the first electrode layer 108 and the auxiliary electrode 102 is disconnected during the etching process and will not be damaged by incomplete etching. The residue causes the first electrode layer 108 to be electrically connected to the auxiliary electrode 102, which solves the problem of short circuit between the first electrode layer 108 and the auxiliary electrode 102. In other embodiments, the bottom The width W6 of 1040b in the first direction D1 may be substantially equal to the width W4 of the top 1040a in the first direction D1, and the width W7 of the bottom 1040b in the second direction D2 may be substantially equal to the width W5 of the top 1040a in the second direction D2.

本揭露之實施例提供一種畫素結構10、10a及10b,畫素結構10具有第二平坦層116,如此一來,使第一電極層108在具有良好平坦度的表面上形成,從而提升發光元件106之發光均勻度。第一電極層108鄰近輔助電極102的一部分108P藉由第二平坦層116墊高而比輔助電極102更遠離基板100,而有利於蝕刻製程時斷開第一電極層108及輔助電極102之間的電性連接,解決第一電極層108及輔助電極102間短路的問題,從而提升製程的良率及穩定性,並因此可縮短第一電極層108及輔助電極102沿第一方向D1之水平距離HS1以及沿第二方向D2之水平距離HS2,藉此提升開口率。畫素結構10a及10b具有位於輔助洞AH中的畫素定義層104之第一部1040,藉此可縮短第一電極層108及輔助電極102沿第一方向D1之水平距離HS1以及沿第二方向D2之水平距離HS2,藉此提升開口率。 The embodiment of the present disclosure provides a pixel structure 10, 10a, and 10b. The pixel structure 10 has a second flat layer 116. In this way, the first electrode layer 108 is formed on a surface with good flatness, thereby enhancing light emission. The uniformity of light emission of the element 106. A portion 108P of the first electrode layer 108 adjacent to the auxiliary electrode 102 is heightened by the second flat layer 116 to be further away from the substrate 100 than the auxiliary electrode 102, which facilitates the disconnection between the first electrode layer 108 and the auxiliary electrode 102 during the etching process The electrical connection solves the problem of short circuit between the first electrode layer 108 and the auxiliary electrode 102, thereby improving the yield and stability of the process, and thus shortening the level of the first electrode layer 108 and the auxiliary electrode 102 along the first direction D1 The distance HS1 and the horizontal distance HS2 along the second direction D2 increase the aperture ratio. The pixel structures 10a and 10b have the first portion 1040 of the pixel definition layer 104 in the auxiliary hole AH, thereby shortening the horizontal distance HS1 between the first electrode layer 108 and the auxiliary electrode 102 in the first direction D1 and the second The horizontal distance HS2 in the direction D2, thereby increasing the aperture ratio.

以上概述數個實施方式或實施例的特徵,使所屬領域中具有通常知識者可以從各個方面更加瞭解本揭露。本技術領域中具有通常知識者應可理解,且可輕易地以本揭露為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到在此介紹的實施方式或實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的揭露精神與範圍。在不背離本揭露的精神與範圍之前提下, 可對本揭露進行各種改變、置換或修改。 The above summarizes the characteristics of several implementations or embodiments, so that those with ordinary knowledge in the field can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on this disclosure, so as to achieve the same purpose and/or to achieve the implementation modes or embodiments introduced herein The same advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the disclosure. Without departing from the spirit and scope of this disclosure, Various changes, substitutions or modifications can be made to this disclosure.

10‧‧‧畫素結構 10‧‧‧Pixel structure

100‧‧‧基板 100‧‧‧Substrate

102‧‧‧輔助電極 102‧‧‧Auxiliary electrode

104‧‧‧畫素定義層 104‧‧‧Pixel definition layer

106‧‧‧發光元件 106‧‧‧Light-emitting element

108‧‧‧第一電極層 108‧‧‧First electrode layer

108P‧‧‧部分 108P‧‧‧Part

112‧‧‧主動元件 112‧‧‧Active Components

114‧‧‧第一平坦層 114‧‧‧First flat layer

116‧‧‧第二平坦層 116‧‧‧Second flat layer

118‧‧‧閘極 118‧‧‧Gate

120‧‧‧閘極絕緣層 120‧‧‧Gate insulation layer

122‧‧‧半導體層 122‧‧‧Semiconductor layer

124‧‧‧層間介電層 124‧‧‧Interlayer dielectric layer

126‧‧‧汲極 126‧‧‧Dip pole

128‧‧‧源極 128‧‧‧Source

130‧‧‧汲極區 130‧‧‧Dip pole area

132‧‧‧源極區 132‧‧‧Source Region

134‧‧‧通道區 134‧‧‧Access area

136‧‧‧無機絕緣層 136‧‧‧Inorganic insulating layer

138‧‧‧主動層 138‧‧‧Active layer

140‧‧‧第二電極層 140‧‧‧Second electrode layer

142‧‧‧容置空間 142‧‧‧Accommodation space

144‧‧‧電子傳輸層 144‧‧‧Electron transport layer

146‧‧‧電洞傳輸層 146‧‧‧Hole Transmission Layer

148‧‧‧電洞注入層 148‧‧‧hole injection layer

150‧‧‧電子注入層 150‧‧‧Electron injection layer

D1‧‧‧第一方向 D1‧‧‧First direction

HS1、HS3、HS4‧‧‧水平距離 HS1, HS3, HS4‧‧‧Horizontal distance

L1‧‧‧長度 L1‧‧‧Length

O‧‧‧開口 O‧‧‧Open

T1、T2‧‧‧厚度 T1, T2‧‧‧Thickness

TH1‧‧‧第一接觸洞 TH1‧‧‧First contact hole

TH2‧‧‧第二接觸洞 TH2‧‧‧Second contact hole

Claims (11)

一種畫素結構,包含:一主動元件,位於一基板上,其中該主動元件包含一汲極與一源極;一第一平坦層,位於該主動元件上;一輔助電極,位於該第一平坦層上,且該第一平坦層位於該輔助電極以及該基板之間;一第二平坦層,位於該輔助電極與該第一平坦層上;以及一發光元件,包含依序設置於該基板上的一第一電極層、一主動層與一第二電極層,該第一電極層位於該第二平坦層上,並透過一第一接觸洞電性連接該汲極或該源極,該第二電極層透過一第二接觸洞電性連接該輔助電極,且該輔助電極於該基板的一法線方向上重疊於該第二接觸洞。 A pixel structure includes: an active element located on a substrate, wherein the active element includes a drain and a source; a first flat layer on the active element; an auxiliary electrode on the first flat Layer, and the first flat layer is located between the auxiliary electrode and the substrate; a second flat layer is located on the auxiliary electrode and the first flat layer; and a light-emitting element including sequentially arranged on the substrate A first electrode layer, an active layer, and a second electrode layer of, the first electrode layer is located on the second flat layer, and is electrically connected to the drain or the source through a first contact hole, the second The two electrode layers are electrically connected to the auxiliary electrode through a second contact hole, and the auxiliary electrode overlaps the second contact hole in a normal direction of the substrate. 如請求項1所述之畫素結構,更包含:一畫素定義層(PDL),位於該第一電極層上,且具有一容置空間,其中該主動層之至少一部分位於該容置空間內。 The pixel structure according to claim 1, further comprising: a pixel definition layer (PDL) located on the first electrode layer and having an accommodation space, wherein at least a part of the active layer is located in the accommodation space Inside. 如請求項1所述之畫素結構,其中該第一電極層的一部分比該輔助電極更遠離該基板。 The pixel structure according to claim 1, wherein a part of the first electrode layer is farther from the substrate than the auxiliary electrode. 如請求項1所述之畫素結構,其中該第一接觸洞與該第二接觸洞相距一最小水平距離為約8.5微米至約11.5微米之間。 The pixel structure according to claim 1, wherein a minimum horizontal distance between the first contact hole and the second contact hole is between about 8.5 μm and about 11.5 μm. 一種畫素結構,包含:一主動元件,位於一基板上,其中該主動元件包含一汲極與一源極;一第一平坦層,位於該主動元件上;一輔助電極,位於該第一平坦層上,且該第一平坦層位於該輔助電極及該基板之間;一發光元件,包含依序設置於該基板上的一第一電極層、一主動層與一第二電極層,其中該第一電極層透過一第一接觸洞與該汲極或該源極電性連接,該第二電極層透過一第二接觸洞電性連接該輔助電極且該輔助電極於該基板的一法線方向上重疊於該第二接觸洞;以及一畫素定義層(PDL),位於該第一電極層上,並具有一第一部位於一輔助洞內,該輔助洞與該第一接觸洞彼此間隔一距離。 A pixel structure includes: an active element located on a substrate, wherein the active element includes a drain and a source; a first flat layer on the active element; an auxiliary electrode on the first flat Layer, and the first flat layer is located between the auxiliary electrode and the substrate; a light-emitting element includes a first electrode layer, an active layer and a second electrode layer sequentially disposed on the substrate, wherein the The first electrode layer is electrically connected to the drain or the source through a first contact hole, the second electrode layer is electrically connected to the auxiliary electrode through a second contact hole, and the auxiliary electrode is connected to a normal line of the substrate Overlaps the second contact hole in the direction; and a pixel definition layer (PDL) located on the first electrode layer and having a first part located in an auxiliary hole, the auxiliary hole and the first contact hole are mutually Keep a distance. 如請求項5所述之畫素結構,其中該畫素定義層還具有一第二部,其中該第二部透過該第一接觸洞接觸該第一電極層的一側壁,且該第二部朝著該基板的延伸長度大於該第一部朝著該基板的延伸長度。 The pixel structure according to claim 5, wherein the pixel definition layer further has a second part, wherein the second part contacts a side wall of the first electrode layer through the first contact hole, and the second part The extension length toward the substrate is greater than the extension length of the first portion toward the substrate. 如請求項5所述之畫素結構,其中該輔助洞之寬度為約3微米至約5.5微米之間。 The pixel structure according to claim 5, wherein the width of the auxiliary hole is between about 3 microns and about 5.5 microns. 如請求項5所述之畫素結構,其中該輔助電 極與該基板之間的距離實質上相同於位於該第一平坦層上的該第一電極層與該基板之間的距離,且該輔助電極以及該第一電極層具有相同材料。 The pixel structure according to claim 5, wherein the auxiliary electric The distance between the electrode and the substrate is substantially the same as the distance between the first electrode layer on the first flat layer and the substrate, and the auxiliary electrode and the first electrode layer have the same material. 如請求項5所述之畫素結構,其中該第一平坦層包含一第一子層與一第二子層,該第二子層位於該第一子層上,其中該第一接觸洞貫穿該第一子層及該第二子層,該輔助洞貫穿該第二子層。 The pixel structure according to claim 5, wherein the first flat layer includes a first sub-layer and a second sub-layer, the second sub-layer is located on the first sub-layer, and the first contact hole penetrates The first sub-layer and the second sub-layer, and the auxiliary hole penetrates the second sub-layer. 如請求項9所述之畫素結構,其中該輔助洞貫穿該第一子層。 The pixel structure according to claim 9, wherein the auxiliary hole penetrates the first sublayer. 一種畫素結構,包含:一主動元件,位於一基板上,其中該主動元件包含一汲極與一源極;一第一平坦層,位於該主動元件上;一輔助電極,位於該第一平坦層上,且該第一平坦層位於該輔助電極及該基板之間;一發光元件,包含依序設置於該基板上的一第一電極層、一主動層與一第二電極層,其中該第一電極層透過一第一接觸洞與該汲極或該源極電性連接,該第二電極層透過一第二接觸洞電性連接該輔助電極且該輔助電極於該基板的一法線方向上重疊於該第二接觸洞,該第一電極層及該輔助電極之間沿一第一方向相距之最小水平距離介於約3微米至約5.5微米之間,該第一電極層及該輔助電極之間沿一第二方向 相距之最小水平距離介於約3微米至約5.5微米之間,且該第一接觸洞與該第二接觸洞沿該第一方向相距之最小水平距離為約9微米至約11.5微米之間,該輔助電極及該第一接觸洞之間沿該第一方向相距之最小水平距離為約6微米至約8.5微米之間,且該第一方向及該第二方向正交;以及一畫素定義層,位於該第一電極層上,並具有一第一部位於一輔助洞內,該輔助洞與該第一接觸洞彼此間隔一距離,該畫素定義層具有一容置空間,該主動層之至少一部分位於該容置空間內。 A pixel structure includes: an active element located on a substrate, wherein the active element includes a drain and a source; a first flat layer on the active element; an auxiliary electrode on the first flat Layer, and the first flat layer is located between the auxiliary electrode and the substrate; a light-emitting element includes a first electrode layer, an active layer and a second electrode layer sequentially disposed on the substrate, wherein the The first electrode layer is electrically connected to the drain or the source through a first contact hole, the second electrode layer is electrically connected to the auxiliary electrode through a second contact hole, and the auxiliary electrode is connected to a normal line of the substrate Direction overlaps the second contact hole, the minimum horizontal distance between the first electrode layer and the auxiliary electrode along a first direction is between about 3 microns to about 5.5 microns, the first electrode layer and the A second direction between auxiliary electrodes The minimum horizontal distance between each other is between about 3 microns and about 5.5 microns, and the minimum horizontal distance between the first contact hole and the second contact hole along the first direction is between about 9 microns and about 11.5 microns, The minimum horizontal distance between the auxiliary electrode and the first contact hole along the first direction is between about 6 microns and about 8.5 microns, and the first direction and the second direction are orthogonal; and a pixel definition Layer, located on the first electrode layer, and having a first part located in an auxiliary hole, the auxiliary hole and the first contact hole are separated from each other by a distance, the pixel definition layer has an accommodating space, and the active layer At least a part of it is located in the accommodating space.
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