TWI705648B - Digital constant on-time controller adaptable to a dc-to-dc converter - Google Patents

Abstract

A digital constant on-time controller adaptable to a direct-current (DC)-to-DC converter includes a current sensing circuit that senses stored energy of the DC-to-DC converter, thereby generating a sense voltage; a semi-amplitude detector that detects half of a peak-to-peak amplitude of the sense voltage, thereby generating a semi-amplitude voltage; a DC voltage detector that detects a DC voltage across an effective series resistor of an energy storage circuit that provides the stored energy of the DC-to-DC converter, thereby generating a DC voltage; an arithmetic device that adds the sense voltage and the semi-amplitude voltage, from which the DC voltage and a predetermined reference signal are subtracted; and a pulse-width modulation (PWM) generator that generates a switch control signal according to a result of the arithmetic device.

Description

Digital fixed on-time controller for DC converter

The present invention relates to a direct current (DC-to-DC) converter, and more particularly to a direct current converter with output voltage offset cancellation.

A power converter is an electronic circuit that converts electrical energy to convert from one form to another. A direct current (DC-to-DC) converter is a type of power converter used to convert a direct current source from one voltage level to another voltage level. In a DC converter, an inductor is usually arranged between the switching circuit and the output node to store energy.

The DC converter usually uses an analog current sensing circuit to sense the inductor current, thereby controlling the switching of the switching circuit. For a constant on-time (COT) DC converter, it uses a ripple-based analog control to compare the sensed inductor current with a reference voltage, and accordingly generate a control signal to control the switching of the switching circuit. However, this mechanism will produce output voltage offset errors, thereby reducing the regulation performance of the DC converter.

Therefore, a novel DC converter is urgently needed to improve the output voltage offset.

In view of the foregoing, one of the objectives of the embodiments of the present invention is to provide a DC-to-DC converter with output voltage offset cancellation, especially a digital fixed on-time controller suitable for DC converters, which can effectively cancel The output voltage is offset.

According to an embodiment of the present invention, a digital fixed on-time controller suitable for a DC converter includes a current sensing circuit, a half-amplitude detector, a DC voltage detector, an arithmetic device, and a pulse width modulation generator. The current sensing circuit senses the stored energy of the DC converter to generate a sensed voltage. The half-amplitude detector detects the peak-to-peak half of the sensed voltage, thereby generating a half-amplitude voltage. The DC voltage detector detects the DC voltage across the effective series resistor in the energy storage circuit that provides stored energy, thereby generating the DC voltage. The arithmetic device adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and the preset reference signal. The pulse width modulation generator generates the switching control signal according to the result of the arithmetic device.

The first A shows a circuit diagram of a DC-to-DC converter 100 with output voltage offset cancellation, which is disclosed in the U.S. Application No. 16/153,467 filed by the applicant on October 5, 2018. It is US Patent No. 10,291,121, entitled "DC-TO-DC CONVERTER AND A DIGITAL CONSTANT ON-TIME CONTROLLER THEREOF". The DC converter 100 may include a switching circuit 11 for generating a switching voltage Vx. The switching circuit 11 may include a first switching device Mp and a second switching device Mn, which are connected in series between the power supply 111 and the ground. The power supply 111 provides the input voltage Vin. The switching voltage Vx is located at the switching node Vx between the first switching device Mp and the second switching device Mn.

The DC converter 100 may include an energy storage circuit 12, which receives the switching voltage Vx to generate a regulated output voltage Vo for supply to the load. The energy storage circuit 12 may include an inductor L and an effective series resistor RL, connected in series between the switching node Vx and the output node Vo; and a capacitor C and an effective series resistor RC, connected in series between the output node Vo and ground.

The DC converter 100 may include an analog-to-digital converter (ADC) 13 for generating an (analog) equivalent digital output voltage Vo[n] of the output voltage Vo. The DC converter 100 may include a driver 14 (for example, an amplifier), which generates a driving signal to drive the switching circuit 11. Wherein, the driver 14 generates a driving signal to drive the first switching device Mp, and generates an inverted driving signal to drive the second switching device Mn.

The DC converter 100 may include a digital constant on-time (DCOT) controller 15 that receives a digital output voltage Vo[n] to generate a switching control signal S, which is fed to the driver 14. The digital constant on-time controller 15 generates a constant on-time (COT) switching control signal according to the stored energy of the energy storage circuit 12 (for example, the inductor current IL flowing through the inductor L).

The first Fig. B shows a circuit diagram of a DC-to-DC converter 200 with output voltage offset cancellation, which is disclosed in the aforementioned US patent application of the applicant. The DC converter 200 in the first figure B is similar to the DC converter 100 in the first figure A, and the differences will be described below. In the first figure B, the first analog-to-digital converter 13A generates the (analog) output voltage Vo equivalent digital output voltage Vo[n], and the second analog-to-digital converter 13B generates the (analog) switching voltage Vx Equivalent digital switching voltage Vx[n]. Therefore, the digital fixed on-time controller 15 of the second embodiment generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in the first embodiment, only the digital output voltage is used. Vo[n].

The second diagram A shows a block diagram of the digital constant on-time (COT) controller 15 of the first embodiment of the present invention. In this embodiment, the constant on-time controller 15 may include a first arithmetic device 1524 for adding the sensing voltage Vs[n] (of the current sensing circuit 151) and the digital output voltage Vo[n], thereby generating the first A signal, which is fed to the first input node (for example, the positive (+) input node) of the comparator 153. The constant on-time controller 15 of this embodiment may include a valley detector 1521 for detecting the valley (or minimum) value of the sensing voltage Vs[n], thereby generating the valley voltage V _valley [n]. The second diagram B shows a detailed block diagram of the valley detector 1521 of the second diagram A. The valley detector 1521 may include a rising edge trigger latch circuit 15211, which latches (or samples) the sensed voltage Vs[n] upon the rising edge trigger of the switching control signal S, thereby generating the valley voltage V _valley [n].

The constant on-time controller 15 of this embodiment may include a second arithmetic device 1525 for adding the valley voltage V _valley [n] and the preset reference signal Vref to generate a second signal, which is fed to the second signal of the comparator 153 Input node (for example, negative (-) input node). The comparison result of the comparator 153 can be fed to a pulse width modulation (PWM) generator 154 to generate the switching control signal S. The comparator 153, the first arithmetic device 1524, and the second arithmetic device 1525 constitute the arithmetic device of this embodiment. In this embodiment, the comparison result of the comparator 153 can be expressed as follows: First signal-Second signal = (Vs[n]+Vo[n])-(Vref+V _valley [n])

The second diagram C shows a block diagram of the digital constant on-time (COT) controller 15 of the first alternative embodiment of the present invention. In this embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in the second diagram A, only the digital output voltage Vo[ n]. The low-pass filter (LPF) 1512 and valley detector 1521 of the current sensing circuit 151 in Figure 2 C are implemented based on the digital switching voltage Vx[n], but in Figure 2 A, it is based on the switching control signal. S to execute.

FIG. 3A shows a block diagram of the digital constant on-time (COT) controller 15 of the second embodiment of the present invention. The constant on-time controller 15 of this embodiment may include a semi-amplitude detector 1526 for detecting the peak-to-peak (peak-to-peak-) of the sensing voltage Vs[n] (of the current sensing circuit 151). to-peak) is half of the value, thus generating a half-amplitude voltage Vpp/2[n]. Fig. 3B shows a detailed block diagram of the half-amplitude detector 1526 of Fig. 3A. The half-amplitude detector 1526 may include a rising edge trigger latch circuit 15261, which latches (or samples) the sensing voltage Vs[n] when the rising edge of the switching control signal S is triggered, thereby generating the minimum value. The half-amplitude detector 1526 may include a falling edge trigger latch circuit 15262, which latches (or samples) the sensing voltage Vs[n] when the falling edge of the switching control signal S is triggered, thereby generating the maximum value. The half-amplitude detector 1526 may include an adder 15263 for subtracting the minimum value from the maximum value, thereby generating peak-to-peak value. The half-amplitude detector 1526 may include a divided-by-2 device 15264 for dividing the peak-to-peak value by 2, thereby generating a half-amplitude voltage Vpp/2[n].

The constant on-time controller 15 of this embodiment may include a direct current (DC) voltage detector 1527 for detecting the effective series resistor R _L across the energy storage circuit 12 (which provides the stored energy of the DC converter) The direct current voltage (that is, R _L I _L(DC) ), thus generating the direct current voltage Vdc[n]. Fig. 3C shows a detailed block diagram of the DC voltage detector 1527 of Fig. 3A. Among them, the DC voltage detector 1527 may include a rising edge trigger latch circuit 15271, which latches (or samples) the sensed voltage Vs[n] upon the rising edge trigger of the delayed switching control signal S, thereby generating intermediate The value represents the DC voltage at the node between the inductor L and the effective series resistor _RL . Among them, the delayed switching control signal S is obtained by delaying the switching control signal S by the delay element 15272 by half a conduction period. The DC voltage detector 1527 may include an adder 15273 for subtracting the digital output voltage Vo[n] from the intermediate value, thereby generating the DC voltage Vdc[n].

The fixed on-time controller 15 of this embodiment may include a first arithmetic device 1524 for adding the sensing voltage Vs[n] and the half-amplitude voltage Vpp/2[n], and subtracting the DC voltage Vdc[n], thus A first signal is generated, which is fed to the first input node (eg, positive (+) input node) of the comparator 153. The preset reference signal Vref is used as the second signal, which is fed to the second input node (eg, negative (-) input node) of the comparator 153. The comparison result of the comparator 153 can be fed to a pulse width modulation (PWM) generator 154 to generate the switching control signal S. The comparator 153 and the first arithmetic device 1524 constitute the arithmetic device of this embodiment. In this embodiment, the comparison result of the comparator 153 can be expressed as follows: The first signal-the second signal = (Vs[n]+Vpp/2[n]-Vdc[n])-Vref

The third diagram D shows a block diagram of the digital constant on-time (COT) controller 15 of the second alternative embodiment of the present invention. In this embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in Figure 3A, only the digital output voltage Vo[ n]. The low-pass filter (LPF) 1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 in the third diagram D are executed according to the digital switching voltage Vx[n], but in the third A In the figure, it is executed according to the switching control signal S.

Fig. 4A shows a block diagram of the digital constant on-time (COT) controller 15 of the third embodiment of the present invention. In this embodiment, the sensing voltage Vs[n] (of the current sensing circuit 151) is used as the first signal, which is fed to the first input node (for example, the positive (+) input node) of the comparator 153. The fixed on-time controller 15 of this embodiment may include a second arithmetic device 1525 for adding the reference signal Vref and the DC voltage (of the DC voltage detector 1527) Vdc[n], and subtracting the (half amplitude detector) The half-amplitude voltage Vpp/2[n] of 1526), thus generating a second signal, which is fed to the second input node (eg, negative (-) input node) of the comparator 153. The comparison result of the comparator 153 can be fed to a pulse width modulation (PWM) generator 154 to generate the switching control signal S. The comparator 153 and the second arithmetic device 1525 constitute the arithmetic device of this embodiment. In this embodiment, the comparison result of the comparator 153 can be expressed as follows: The first signal-the second signal = Vs[n]-(Vref-Vpp/2[n]+Vdc[n])

Fig. 4B shows a block diagram of the digital constant on-time (COT) controller 15 of the third alternative embodiment of the present invention. In this embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in Figure 4A, only the digital output voltage Vo[ n]. The low-pass filter (LPF) 1512, the half-amplitude detector 1526, and the DC voltage detector 1527 of the current sensing circuit 151 in the fourth figure B are executed according to the digital switching voltage Vx[n], but in the fourth A In the figure, it is executed according to the switching control signal S.

Fig. 5A shows a block diagram of the digital constant on-time (COT) controller 15 of the fourth embodiment of the present invention. In this embodiment, the constant on-time controller 15 may include a first arithmetic device 1524 for adding the sensing voltage Vs[n] (of the current sensing circuit 151) and the half amplitude (of the half amplitude detector 1526) The voltage Vpp/2[n] thus generates the first signal, which is fed to the first input node of the comparator 153 (for example, the positive (+) input node). The fixed on-time controller 15 of this embodiment may include a second arithmetic device 1525 for adding a reference signal Vref and a DC voltage (of the DC voltage detector 1527) Vdc[n], thereby generating a second signal, which is fed to The second input node of the comparator 153 (for example, a negative (-) input node). The comparison result of the comparator 153 can be fed to a pulse width modulation (PWM) generator 154 to generate the switching control signal S. The comparator 153, the first arithmetic device 1524, and the second arithmetic device 1525 constitute the arithmetic device of this embodiment. In this embodiment, the comparison result of the comparator 153 can be expressed as follows: The first signal-the second signal = (Vs[n]+ Vpp/2[n])-(Vref+Vdc[n])

Fig. 5B shows a block diagram of the digital constant on-time (COT) controller 15 of the fourth alternative embodiment of the present invention. In this embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in Figure 5A, only the digital output voltage Vo[ n]. The low-pass filter (LPF) 1512, the half-amplitude detector 1526, and the DC voltage detector 1527 of the current sensing circuit 151 in FIG. 5B are executed according to the digital switching voltage Vx[n], but in the fifth A In the figure, it is executed according to the switching control signal S.

Fig. 6A shows a block diagram of the digital constant on-time (COT) controller 15 of the fifth embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may include a first arithmetic device 1524 for subtracting the DC voltage (from the DC voltage detector 1527) Vdc[n] from the sensing voltage Vs[n], thereby generating The first signal is fed to the first input node (for example, the positive (+) input node) of the comparator 153. The fixed on-time controller 15 of this embodiment may include a second arithmetic device 1525 for subtracting the half-amplitude voltage Vpp/2[n] (of the half-amplitude detector 1526) from the reference signal Vref, thereby generating a second signal , Which is fed to the second input node (for example, the negative (-) input node) of the comparator 153. The comparison result of the comparator 153 can be fed to a pulse width modulation (PWM) generator 154 to generate the switching control signal S. The comparator 153, the first arithmetic device 1524, and the second arithmetic device 1525 constitute the arithmetic device of this embodiment. In this embodiment, the comparison result of the comparator 153 can be expressed as follows: The first signal-the second signal = (Vs[n]-Vdc[n])-(Vref-Vpp/2[n])

Fig. 6B shows a block diagram of the digital constant on-time (COT) controller 15 of the fifth alternative embodiment of the present invention. In this embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo[n] and the digital switching voltage Vx[n]. However, in Figure 6A, only the digital output voltage Vo[ n]. The low-pass filter (LPF) 1512, the half-amplitude detector 1526, and the DC voltage detector 1527 of the current sensing circuit 151 in Fig. 6B are executed according to the digital switching voltage Vx[n], but in the fifth A In the figure, it is executed according to the switching control signal S.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.

100: DC converter 200: DC converter 11: switching circuit 111: power supply 12: energy storage circuit 13: analog to digital converter 13A: first analog to digital converter 13B: second analog to digital converter 14: driver 15: Digital fixed on-time controller 151: Current sensing circuit 1511: High pass filter 1512: Low pass filter 1513: First adder 1521: Valley detector 15211: Rising edge trigger latch circuit 1524: First arithmetic Device 1525: Second Arithmetic Device 1526: Half Amplitude Detector 15261: Rising Edge Trigger Latch Circuit 15262: Falling Edge Trigger Latch Circuit 15263: Adder 15264: Divide by Two Device 1527: DC Voltage Detector 15271: Rising Edge Trigger latch circuit 15272: delay element 15273: adder 153: comparator 154: pulse width modulation generator Mp: first switching device Mn: second switching device L: inductor R _L : effective series resistor C: capacitor R _C : effective series resistor Vx: switching voltage/switching node Vx[n]: digital switching voltage Vo: output voltage/output node Vin: input voltage _IL : inductor current Vo[n]: digital output voltage S: switching control Signal Vref: Reference signal V _valley [n]: Valley voltage Vs[n]: Sensing voltage Vpp/2[n]: Half amplitude voltage Vdc[n]: DC voltage

Figure A shows the circuit diagram of a DC converter with output voltage offset cancellation. The first figure B shows the circuit diagram of the DC converter with output voltage offset cancellation. The second diagram A shows the block diagram of the digital constant on-time (COT) controller of the first embodiment of the present invention. Figure 2B shows a detailed block diagram of the valley detector of Figure 2A. Figure 2C shows a block diagram of the digital constant on-time (COT) controller of the first alternative embodiment of the present invention. Fig. 3A shows a block diagram of a digital constant on-time (COT) controller of the second embodiment of the present invention. Figure 3 B shows a detailed block diagram of the half-amplitude detector of Figure 3 A. Figure 3 C shows a detailed block diagram of the DC voltage detector of Figure 3 A. The third diagram D shows the block diagram of the digital constant on-time (COT) controller of the second alternative embodiment of the present invention. Fig. 4A shows a block diagram of the digital constant on-time (COT) controller of the third embodiment of the present invention. Fig. 4B shows a block diagram of the digital constant on-time (COT) controller of the third alternative embodiment of the present invention. Figure 5A shows a block diagram of the digital constant on-time (COT) controller of the fourth embodiment of the present invention. Fig. 5B shows a block diagram of the digital constant on-time (COT) controller of the fourth alternative embodiment of the present invention. Fig. 6A shows a block diagram of the digital constant on-time (COT) controller of the fifth embodiment of the present invention. Fig. 6B shows a block diagram of the digital constant on-time (COT) controller of the fifth alternative embodiment of the present invention.

15: Digital fixed on-time controller

151: current sensing circuit

1511: high pass filter

1512: low pass filter

1513: first adder

1524: First Arithmetic Device

1526: Half amplitude detector

1527: DC voltage detector

153: Comparator

154: Pulse Width Modulation Generator

Vo[n]: Digital output voltage

S: Switch control signal

Vref: reference signal

Vs[n]: Sensing voltage

Vpp/2[n]: Half amplitude voltage

Vdc[n]: DC voltage

Claims (13)

A digital fixed on-time controller suitable for DC converters includes: a current sensing circuit that senses the stored energy of the DC converter to generate a sensed voltage; a half amplitude detector that detects the sense The measured voltage is half of the peak to peak value, thus generating a half-amplitude voltage; a DC voltage detector, in the energy storage circuit that provides the stored energy, detects the DC voltage across the effective series resistor, thereby generating the DC voltage; An arithmetic device that adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a preset reference signal; and a pulse width modulation generator, which generates a switching control signal according to the result of the arithmetic device; The arithmetic device includes: a comparator having a first input node and a second input node, the comparison result of the comparator is fed to the pulse width modulation generator; and a first arithmetic device for adding the sensing Voltage and the half-amplitude voltage, and subtract the DC voltage, thereby generating a first signal, which is fed to the first input node of the comparator; wherein the preset reference signal is used as a second signal, which is fed to the comparator The second input node. The digital fixed on-time controller suitable for DC converters according to the first item of the scope of patent application, wherein the half-amplitude detector includes: a rising edge trigger latch circuit, in response to the switching control signal or the rise of the digital switching voltage Edge triggering to latch the sensing voltage, thereby generating a minimum value; a falling edge triggering latch circuit, triggering on the switching control signal or the falling edge of the digital switching voltage to latch the sensing voltage, thereby generating the maximum value; An adder is used to subtract the maximum value from the minimum value, thereby generating a peak-to-peak value; and a divide-by-two device is used to divide the peak-to-peak value by two, thereby generating the half-amplitude voltage. According to item 1 of the scope of patent application, the digital fixed on-time controller for DC converters, wherein the DC voltage detector includes: a delay element for delaying the switching control signal or the digital switching voltage by half of the conduction Cycle to obtain a delayed switching control signal or digital switching voltage; a rising edge trigger latch circuit, triggering on the rising edge of the delayed switching control signal or digital switching voltage to latch the sensing voltage, thereby generating an intermediate value; and An adder is used to subtract the digital output voltage of the DC converter from the intermediate value, thereby generating the DC voltage. According to item 1 of the scope of patent application, the digital fixed on-time controller suitable for DC converters, wherein the first input node is a positive input node, and the second input node is a negative input node. A digital fixed on-time controller suitable for DC converters includes: a current sensing circuit that senses the stored energy of the DC converter to generate a sensed voltage; a half amplitude detector that detects the sense The measured voltage is half of the peak to peak value, thus generating a half-amplitude voltage; a DC voltage detector, in the energy storage circuit that provides the stored energy, detects the DC voltage across the effective series resistor, thereby generating the DC voltage; An arithmetic device that adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a preset reference signal; and a pulse width modulation generator, which generates a switching control signal according to the result of the arithmetic device; The arithmetic device includes: a comparator having a first input node and a second input node, the comparison result of the comparator is fed to the pulse width modulation generator; and a second arithmetic device for adding the preset The reference signal and the DC voltage are subtracted from the half-amplitude voltage, thereby generating a second signal, which is fed to the second input node of the comparator; The sensing voltage is used as the first signal, which is fed to the first input node of the comparator. According to item 5 of the scope of patent application, the digital fixed on-time controller suitable for DC converters, wherein the first input node is a positive input node, and the second input node is a negative input node. A digital fixed on-time controller suitable for DC converters includes: a current sensing circuit that senses the stored energy of the DC converter to generate a sensed voltage; a half amplitude detector that detects the sense The measured voltage is half of the peak to peak value, thus generating a half-amplitude voltage; a DC voltage detector, in the energy storage circuit that provides the stored energy, detects the DC voltage across the effective series resistor, thereby generating the DC voltage; An arithmetic device that adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a preset reference signal; and a pulse width modulation generator, which generates a switching control signal according to the result of the arithmetic device; The arithmetic device includes: a comparator having a first input node and a second input node, the comparison result of the comparator is fed to the pulse width modulation generator; a first arithmetic device for adding the sensing voltage And the half-amplitude voltage, thereby generating a first signal, which is fed to the first input node of the comparator; and a second arithmetic device for adding the preset reference signal and the DC voltage, thereby generating a second signal, It is fed to the second input node of the comparator. According to item 7 of the scope of patent application, the digital fixed on-time controller suitable for DC converters, wherein the first input node is a positive input node, and the second input node is a negative input node. A digital fixed on-time controller suitable for DC converters, including: A current sensing circuit that senses the stored energy of the DC converter to generate a sense voltage; a half-amplitude detector that detects half of the peak-to-peak value of the sensed voltage, thereby generating a half-amplitude voltage; A DC voltage detector, in the energy storage circuit that provides the stored energy, detects the DC voltage across the effective series resistor, thereby generating the DC voltage; an arithmetic device that adds the sensing voltage and the half-amplitude voltage, And subtract the DC voltage and the preset reference signal; and a pulse width modulation generator, which generates a switching control signal according to the result of the arithmetic device; wherein the arithmetic device includes: a comparator with a first input node and At the second input node, the comparison result of the comparator is fed to the pulse width modulation generator; a first arithmetic device is used to subtract the DC voltage from the sensing voltage, thereby generating a first signal, which is fed to the A first input node of the comparator; and a second arithmetic device for subtracting the half-amplitude voltage from the preset reference signal, thereby generating a second signal, which is fed to the second input node of the comparator. According to item 9 of the scope of patent application, the digital fixed on-time controller suitable for DC converters, wherein the first input node is a positive input node, and the second input node is a negative input node. A digital fixed on-time controller suitable for DC converters includes: a current sensing circuit that senses the stored energy of the DC converter to generate a sensed voltage; and a valley detector for detecting the The valley value of the sensed voltage, thereby generating valley voltage; a comparator having a first input node and a second input node; a first arithmetic device for adding the sense voltage and the digital output voltage of the DC converter, Thus, a first signal is generated, which is fed to the first input node of the comparator; A second arithmetic device for adding the valley voltage and a predetermined reference signal to generate a second signal, which is fed to the second input node of the comparator; and a pulse width modulation generator, which is based on the comparator The result of the comparison to generate a switching control signal. According to item 11 of the scope of patent application, the digital constant on-time controller suitable for DC converters, wherein the valley detector includes: a rising edge trigger latch circuit, on the rising edge of the switching control signal or the digital switching voltage Triggering to latch the sensing voltage, thereby generating the valley voltage. According to item 11 of the scope of patent application, the digital fixed on-time controller suitable for DC converters, wherein the first input node is a positive input node, and the second input node is a negative input node.

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