TWI704454B - Mapping table management method applied to solid state storage device - Google Patents

Abstract

A mapping table management method applied to solid state storage device is provided. The method includes steps of: when a write command is received by a control circuit, the control circuit storing write data to a non-volatile memory and updating a mapping table in a DRAM; when a power down command is received by the control circuit, the control circuit storing the entire mapping table to the non-volatile memory; and when an update requirement is met judged by the control circuit, the control circuit storing a portion of the mapping table to the non-volatile memory.

Description

Correspondence table management method of solid storage device

The present invention relates to a processing method of a solid-state storage device, and particularly relates to a mapping table management method of a solid-state storage device.

As we all know, solid state storage devices (Solid State Storage Devices) have been widely used in various electronic products, such as SD cards, solid state drives, and so on. The solid-state storage device includes a non-volatile memory. After the data is written into the non-volatile memory, once the system power is turned off, the data is still stored in the non-volatile memory.

Please refer to Figure 1, which is a schematic diagram of a conventional solid-state storage device. The control circuit 10 of the solid state storage device 100 is connected to a host 150 via an external bus 110, where the external bus 110 can be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U.2. Bus and so on.

Furthermore, the solid-state storage device 100 includes a control circuit 10, a dynamic random access memory (DRAM) 30, and a non-volatile memory 20. Among them, the control circuit 10 is connected to the non-volatile memory 20 and the DRAM 30.

Generally, the host 150 and the control circuit 10 use a logical block address (LBA address) to access data. The control circuit 10 and the non-volatile memory 20 use a physical allocation address (hereinafter referred to as a PAA address) to access data.

Therefore, a mapping table 32 is stored in the DRAM 30 of the solid-state storage device 100 to serve as the correspondence between the LBA address and the PAA position. This mapping table 32 is also called a logical-to-physical address mapping table (Logical-to-Physical address mapping table). The following describes the operation principle of the corresponding table 32.

When the host 150 wants to write data into the solid-state storage device 100, the host 150 will issue a write command to the solid-state storage device 100. At this time, the write command includes the LBA address and write data. Then, the control circuit 10 records the correspondence between the LBA address and the PAA address in the correspondence table 32 of the DRAM 30, and stores the written data in the storage space of the PAA address in the non-volatile memory.

When the host 150 wants to read data from the solid-state storage device 100, the host 150 issues a read command, and the read command includes the LBA address. When the control circuit 10 receives the read command, it finds the PAA address in the correspondence table 32 according to the LBA address. After that, the control circuit 10 obtains the read data from the storage space of the PAA address in the non-volatile memory 20 and transmits it to the host 150.

It can be seen from the above description that when the solid-state storage device 100 is writing data, the control circuit 10 must synchronously record the correspondence table 32 so that the control circuit 10 can grasp all the written data stored in the non-volatile memory 20 and be effective Management of data in a timely manner.

Since the correspondence table 32 is stored in the DRAM 30, and once the system power is turned off, the data stored in the DRAM 30 will disappear. Therefore, when the solid-state storage device 100 receives a power down command, the control circuit 10 must first The power can be turned off only after the correspondence table 32 is stored in the non-volatile memory 20.

When the solid-state storage device 100 is powered again, the control circuit 10 must first load the corresponding table in the non-volatile memory 20 into the DRAM 30 before the solid-state storage device 100 can operate normally.

It can be seen from the above description that the correspondence table 32 in the DRAM 30 records the correspondence between the LBA address and the PAA address.

However, if the solid-state storage device 100 operates normally and accesses a lot of data, the power supplied to the solid-state storage device 100 is suddenly cut off, the data in the corresponding table 32 in the DRAM 30 will be deleted.

In this way, when the solid-state storage device 100 is powered on again, the control unit 10 can only load the old correspondence table from the non-volatile memory 20 to the DRAM 30. Then, the control circuit 10 must search all storage spaces in the non-volatile memory 20, and gradually modify and rebuild the corresponding table 32.

After the control circuit 10 has searched all the storage spaces in the non-volatile memory 20, the corresponding table 32 is rebuilt and the solid-state storage device 100 can operate normally. However, the reconstruction of the above-mentioned correspondence table 32 will take a considerable time.

The present invention relates to a corresponding table management method for a solid-state storage device. The solid-state storage device includes a control circuit, a dynamic random access memory and a non-volatile memory. The corresponding table management method includes the following steps: When the circuit receives a write command, the control circuit stores the written data in the non-volatile memory and updates a corresponding table in the dynamic random access memory; when the control circuit receives a shutdown command, the control circuit The control circuit stores the complete correspondence table in the dynamic random access memory in the non-volatile memory; and when the control circuit determines that an update condition is met, the control circuit stores a part of the dynamic random access memory The corresponding table of is stored in the non-volatile memory.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following embodiments are specifically described in conjunction with the accompanying drawings as follows:

Please refer to Figure 2, which illustrates the corresponding table management method according to the first embodiment of the present invention. Basically, the mapping table management method disclosed in the first embodiment is applied to the solid-state storage device 100 shown in FIG. 1, and the structure of the solid-state storage device is not repeated here.

When the solid-state storage device 100 is operating normally, when the control circuit 10 receives a write command from the host 150, the control circuit 10 not only stores the written data in the non-volatile memory 20, but also synchronously records it in the DRAM 30 The corresponding table 32.

According to the first embodiment of the present invention, when the solid-state storage device 100 is operating normally and the shutdown command is not received (step S210), the control circuit 10 determines whether the update condition is met (step S320). When the control circuit 10 determines that the update condition has been met (step S230), the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 in the non-volatile memory 20 (step S240). Conversely, when the control circuit 10 determines that the update condition has not been met (step S230), it returns to step S210.

For example, the control circuit 10 can preset a data amount of 10 Mbyte as a criterion for judging the update condition. Specifically, the control circuit 10 will continue to calculate the total amount of data written into the non-volatile memory 20. When the total amount of written data reaches an integer multiple of the preset data amount, it means that the update conditions are met. . At this time, the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 in the non-volatile memory 20.

In other words, when the stored write data reaches an integral multiple of 10 Mbytes (ie, 10 Mbyte, 20 Mbytes, 30 Mbytes...), the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 into the non-volatile memory 20. Conversely, when the stored write data does not reach an integral multiple of 10 Mbytes, the control circuit 10 only continues to calculate the total data amount of the write data, and does not store the correspondence table 32 in the DRAM 30 to the non-volatile memory 20.

Of course, if the solid-state storage device 100 receives a shutdown command (step S210), the control circuit 10 directly stores the complete correspondence table 32 in the DRAM 30 to the non-volatile memory (step S220). After that, the solid-state storage device 100 can be shut down.

During the normal operation of the solid-state storage device 100, the correspondence table 32 in the DRAM 30 is constantly updated. It can be seen from the above description that the solid-state storage device 100 of the present invention stores the updated correspondence table 32 in the DRAM 30 into the non-volatile memory 20 during normal operation. Therefore, when the solid-state storage device 100 is abnormally powered off, the non-volatile memory 20 may store a newer correspondence table.

In this way, when the solid-state storage device 100 is powered on again, the control unit 10 can load the latest correspondence table stored in the non-volatile memory 20 before the power failure into the DRAM 30. Then, the control circuit 10 rebuilds (rebuilds) the correct correspondence table according to the latest correspondence table 32. Since the latest correspondence table 32 needs to be modified relatively few parts, the time for rebuilding the correspondence table 32 can be effectively shortened.

It can be seen from the above description that using the correspondence table management method of the first embodiment of the present invention, when the solid-state storage device 100 is abnormally powered off and power is supplied to the solid-state storage device 100 again, the control circuit 10 can quickly rebuild the correspondence table 32, and make the solid-state storage device 100 operate normally.

However, when the host 150 continuously stores write data to the solid-state storage device 100, the use of the first embodiment of the present invention may cause the write performance of the solid-state storage device 100 to decrease. described as follows:

Basically, the size of the correspondence table 32 is related to the total capacity of the non-volatile memory 20. When the total capacity of the non-volatile memory 20 is larger, the size of the correspondence table is also larger.

When the host 150 continuously stores a large amount of written data in the solid-state storage device 100, the control circuit 10 needs to continuously store the written data in the non-volatile memory 20 according to instructions from the host 150. However, in the method disclosed in the first embodiment, when the total amount of data accumulated by the control circuit 10 reaches an integer multiple of the preset data amount, the control circuit 10 will suspend storing the written data in the non-volatile memory 20. And the complete correspondence table 32 is stored in the non-volatile memory 20.

After the complete correspondence table 32 is stored in the non-volatile memory 20, the control circuit 10 will continue to store the written data in the non-volatile memory 20.

It can be seen from the above description that in the process of the host 150 continuously storing a large amount of written data to the solid-state storage device 100, the control circuit 20 will interrupt for a period of time after storing a preset amount of written data to change the corresponding table 32 Store to non-volatile memory 20. After that, after storing the written data of the preset data amount again, there will be an interruption for a period of time to store the correspondence table 32 in the non-volatile memory 20, and continue to repeat.

Obviously, in the above-mentioned operation process, the longer the time it takes to store the corresponding table 32, the more serious the write performance of the solid-state storage device 100 decreases. In other words, when the total capacity of the non-volatile memory 20 is larger, and the size of the corresponding table 32 is also larger, the write performance of the solid-state storage device 100 decreases more severely.

Please refer to FIG. 3, which illustrates the corresponding table management method according to the second embodiment of the present invention. Similarly, the corresponding table management method disclosed in the second embodiment is applied to the solid-state storage device 100 in FIG. 1. In addition, the difference between the second embodiment and the first embodiment is only in step S340. The following only introduces this step, other steps will not be repeated.

When the control circuit 10 determines that the update condition has been met (step S230), the control circuit 10 stores part of the correspondence table 32 in the DRAM 30 in the non-volatile memory 20 (step S340).

According to the second embodiment of the present invention, the control circuit 10 divides the correspondence table 32 into M parts. When the control circuit 10 determines that the update conditions are met, the control circuit 10 only stores the content of one of the M parts in the corresponding table 32 to the non-volatile memory 20. In this way, it can take less time to store.

For example, the data amount of 10 Mbyte is preset in the control circuit 10, and the control circuit 10 divides the correspondence table 32 into M parts. Furthermore, the control circuit 10 will continue to calculate the total amount of data written into the non-volatile memory 20. When the control circuit 10 determines that the update conditions are met, the control circuit 10 stores the contents of the first part of the corresponding table 32 to Non-volatile memory 20.

Similarly, when the control circuit 10 determines that the update condition is met again, the control circuit 10 stores the content of the second part of the correspondence table 32 to the non-volatile memory 20. Furthermore, after the control circuit 10 performs the M-th storage and stores the contents of the M part of the corresponding table 32 in the non-volatile memory 20, it can be determined that the control circuit 10 has stored all the contents of the corresponding table 32 in the non-volatile memory. Sexual memory 20.

Then, when the control circuit 10 performs the (M+1)th storage, the control circuit 10 stores the content of the first part of the correspondence table 32 in the non-volatile memory 20 again. And so on. In other words, whenever the control circuit 10 determines that the update condition is met, the control circuit 10 sequentially selects one of the M parts in the corresponding table 32 in a circular manner, and stores its content in the non-volatile memory 20.

During the normal operation of the solid-state storage device 100, the correspondence table 32 in the DRAM 30 is constantly updated. It can be seen from the above description that the solid-state storage device 100 of the present invention stores the updated correspondence table 32 in the DRAM 30 into the non-volatile memory 20 during normal operation. Therefore, when an abnormal power failure occurs in the solid-state storage device 100, a newer correspondence table can be stored in the non-volatile memory 20. Therefore, when the solid-state storage device 100 is powered again, the time taken to rebuild the correct correspondence table 32 can be effectively shortened.

Furthermore, since the control circuit 10 divides the correspondence table 32 into M parts, it takes a short time to store a part of the contents of the correspondence table 32 each time. Therefore, the mapping table management method disclosed in the second embodiment can maintain the solid-state storage device 100 at a better write performance.

In the first embodiment and the second embodiment of the present invention, whether the total data amount of the stored written data reaches an integer multiple of the preset data amount is used as the judgment criterion of the update condition. Of course, the present invention is not limited to this, and those skilled in the art can use other conditions to determine whether to store the updated correspondence table 32 in the non-volatile memory 20. For example, the control circuit 10 can calculate the total time spent storing the written data, and when the accumulated total time reaches an integer multiple of the preset time, it will proceed to store the updated correspondence table 32 to the non-volatile memory. 20 moves.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10‧‧‧Control circuit 20‧‧‧Non-volatile memory 30‧‧‧DRAM32‧‧‧Correspondence table 100‧‧‧Solid state storage device 110‧‧‧External bus 150‧‧‧Host

Figure 1 is a schematic diagram of a conventional solid-state storage device. Figure 2 shows the correspondence table management method according to the first embodiment of the present invention. Figure 3 shows the correspondence table management method according to the second embodiment of the present invention.

S210~S340‧‧‧Step Process

Claims (5)

A method for managing a correspondence table of a solid-state storage device. The solid-state storage device includes a control circuit, a dynamic random access memory and a non-volatile memory. The management method for the correspondence table includes the following steps: when the control circuit receives a When writing a command, the control circuit stores the written data in the non-volatile memory, and updates a corresponding table in the dynamic random access memory; the control circuit calculates and stores it in the non-volatile memory. A total amount of data; when the total amount of data reaches an integer multiple of a preset amount of data, the control circuit stores part of the corresponding table in the dynamic random access memory in the non-volatile memory; and when When the control circuit receives a shutdown command, the control circuit stores the complete correspondence table in the dynamic random access memory in the non-volatile memory. The corresponding table management method described in item 1 of the scope of patent application, wherein the corresponding table is a logical to physical address corresponding table. A method for managing a correspondence table of a solid-state storage device. The solid-state storage device includes a control circuit, a dynamic random access memory and a non-volatile memory. The method for managing the correspondence table includes the following steps: When the control circuit receives a write command, the control circuit stores the written data in the non-volatile memory, and updates a corresponding table in the dynamic random access memory; the control circuit calculates and stores the written data A total time spent; when the total time reaches an integer multiple of a preset time, the control circuit stores part of the corresponding table in the dynamic random access memory in the non-volatile memory; and when the control When the circuit receives a shutdown command, the control circuit stores the complete correspondence table in the dynamic random access memory in the non-volatile memory. According to the corresponding table management method described in item 1 of the scope of patent application, the corresponding table is divided into M parts, and the corresponding table of a part is the content of one of the M parts in the corresponding table. For the correspondence table management method described in item 1 of the scope of patent application, the correspondence table is divided into M parts, and the correspondence table of a part of the correspondence table is the content of one of the M parts in the correspondence table, and the control circuit Select one of the M parts in the corresponding table sequentially in a circular manner, and store its content in the non-volatile memory.

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