TWI702848B - Digital double sampling circuit - Google Patents

Abstract

A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.

Description

Digital double sampling circuit

The present invention relates to a digital double-sampling (DDS), and particularly relates to a digital double-sampling circuit, which can avoid the dark-sun phenomenon and is suitable for image sensors.

The digital double sampling (DDS) mechanism is commonly used in image sensors, such as complementary metal oxide semiconductor (CMOS) image sensors. When reading the photodiode information, the offset of the reading path and the delay change of the comparator can be offset.

When capturing an image of sunlight, the sunlight partly darkens due to the overflow of electrons from the photodiode. In order to avoid this dark-sun phenomenon, a clamping mechanism is generally used to clamp the image output node of the pixel circuit to a certain level during the reset stage. However, during the reset phase, the clamping mechanism will affect the signal transmission from the photodiode to the image output node, especially in non-sunlight or low-light conditions, resulting in column fixed pattern noise (CFPN).

Since the traditional clamping mechanism cannot effectively solve the dark sun phenomenon of the digital double sampling system, it is urgent to propose a novel mechanism to overcome the shortcomings of the traditional digital double sampling system.

In view of the above, one of the objectives of the embodiments of the present invention is to provide a digital double sampling circuit, which can effectively avoid dark-sun phenomenon and line fixed image noise (CFPN).

According to an embodiment of the present invention, the digital double sampling circuit includes a pixel circuit of an image sensor, a comparator, a reset switch, an analog-to-digital converter, a digital detection subtractor, and a clamping circuit. ratio The first input node of the comparator is connected to the ramp voltage, and the second input node is connected to the image output node of the pixel circuit via a capacitor. The reset switch is connected between the first input node and the second input node for resetting the capacitor. The analog-to-digital converter receives the comparison output of the comparator. The analog-to-digital converter includes a counter. When the ramp voltage ramps up, the counter counts, thus generating a reset-ADC value during the reset phase and a signal during the signal phase -ADC value. The digital detection subtractor subtracts the signal-ADC value from the reset-ADC value to generate a difference value, which represents the sampled output. The clamping circuit generates a clamping voltage at the image output node. In the reset phase, the clamp circuit is closed after the capacitor is reset, but the clamp circuit is closed before the ramp voltage starts to slope.

100: Digital double sampling circuit

11: Pixel circuit

12: Comparator

13: Analog to digital converter

131: Counter

132: Memory

14: Digital detection subtractor

15: Clamping circuit

m1: Transmission transistor

m2: reset transistor

m3: source follower transistor

m4: column selection transistor

m5: first bias crystal

m6: clamped transistor

m7: second bias crystal

PD: photodiode

VDD: power supply

FD: Floating diffusion node

VL: image output node

Tx: transmit signal

Rx: reset signal

SEL: select signal

VB: first bias

I1: current

I2: current

VI: negative input node

Ci: Capacitor

Vramp: ramp voltage

rst_en: reset enable signal

dout: compare output

bs_en: Clamp enable signal

vbs: second bias

t0~t8: time

△V1: Clamping voltage

△V2: Decline

△V3: Decline

N1: count value

N2: count value

The first figure shows the circuit diagram of the digital double sampling circuit according to the embodiment of the present invention, which has a dark sun phenomenon avoiding mechanism and can be applied to the pixel circuit of an image sensor.

The second diagram illustrates the relative signal timing diagram of the comparator and the analog-to-digital converter in the first diagram.

The third diagram illustrates a timing diagram of related signals of the digital double sampling circuit of the embodiment of the present invention.

The fourth figure illustrates the relative signal timing diagram of the digital double sampling circuit using a mechanism different from that of the third figure.

The first figure shows a circuit diagram of a digital double-sampling (DDS) circuit 100 according to an embodiment of the present invention. It has a dark-sun phenomenon avoidance mechanism and can be applied to the pixel circuit 11 of an image sensor. For example, complementary metal oxide semiconductor (CMOS) image sensors. Although the first figure illustrates a four-transistor (4T) pixel structure, the pixel circuit 11 can also use other structures.

The pixel circuit 11 may include a transfer transistor m1, a reset transistor m2, a source follower transistor m3, and a column selection transistor m4, and may be implemented using an N-type metal oxide semiconductor (NMOS) transistor. As illustrated in the first figure, the photodiode PD is connected between the transmission transistor m1 and the ground. pass The power transmitting transistor m1 is connected between the floating diffusion node FD and the photodiode PD, and the gate of the transmitting transistor m1 is connected to the transmission signal Tx. The reset transistor m2 is connected between the power supply VDD and the floating diffusion node FD, and the gate of the reset transistor m2 is connected to the reset signal Rx. The source follower transistor m3 and the column select transistor m4 are connected in series between the power supply VDD and the image output node VL, and the gates of the source follower transistor m3 and the column select transistor m4 are respectively connected to the floating diffusion nodes FD and Select signal SEL. The first bias voltage crystal m5 is connected between the image output node VL and the ground, and the gate of the first bias voltage crystal m5 is connected to the first bias voltage VB.

The digital double sampling circuit 100 of this embodiment may include a comparator 12, which may include an operational amplifier. The first input node (such as the positive (+) input node) of the comparator 12 is connected to the ramp voltage Vramp, and the second input node (such as the positive (-) input node) of the comparator 12 is connected to the image output via the capacitor Ci Node VL. The reset switch SW is controlled by the reset enable signal rst_en and is connected between the negative input node VI and the positive (+) input node of the comparator 12 to reset the image output node VL and the comparator 12( The negative (-) input node VI) between the capacitor Ci.

The digital double sampling circuit 100 of this embodiment may include an analog-to-digital converter (ADC) 13, which receives the comparison output dout of the comparator 12 to generate a digital count signal. When the ramp voltage Vramp ramps down, the counter 131 counts to obtain a digital count signal, which represents a period during which the comparison output dout is asserted (for example, a high level). The second diagram illustrates the relative signal timing diagram of the comparator 12 and the analog-to-digital converter 13 in the first diagram. In the reset phase of the digital double sampling performed by the digital double sampling circuit 100, the counter 131 of the analog-to-digital converter 13 uses m bits to count from 0 to 2 ^m -1 (for example, the 8-bit counter starts from 0 Count to 255) and generate reset-ADC value. On the other hand, in the signal phase of the digital double sampling performed by the digital double sampling circuit 100, the counter 131 of the analog-to-digital converter 13 uses n bits (m and n are positive integers and m≦n) from 0 counts to 2 ⁿ -1 (for example, a 10-bit counter counts from 0 to 1023), and generates a signal-ADC value. The analog-to-digital converter 13 may include a memory 132 for temporarily storing the generated reset-ADC value and signal-ADC value.

The digital double sampling circuit 100 of this embodiment may include a digital-detection subtractor (subtractor with digital-detection) 14, which subtracts the reset-ADC value from the signal-ADC value to generate a difference value, which represents the photodiode signal Sample output. In this embodiment, if the reset-ADC value is equal to the maximum count value in the reset phase (ie 2 ^m -1), which is represented as a sun-light condition, the output of the digital detection subtractor 14 (also That is, the sampling output of the digital double sampling circuit 100 is set to the maximum count value of the signal phase (that is, 2 ⁿ -1), so the dark sun phenomenon can be avoided; otherwise, the difference is output as the sampling output.

The digital double sampling circuit 100 of this embodiment may include a clamp circuit 15 connected between the power supply VDD and the image output node VL. In this embodiment, the clamping circuit 15 may include a clamping transistor m6 (for example, an N-type metal oxide semiconductor (NMOS) transistor), which generates a clamping voltage at the image output node VL. The gate of the clamp transistor m6 is controlled by the clamp enable signal bs_en. For example, when the clamp enable signal bs_en is active (for example, a high level), the clamp circuit 15 is turned on to generate a clamp voltage; otherwise, no clamp voltage is generated. The clamp circuit 15 may further include a second bias voltage crystal m7 connected between the power supply VDD and the clamp transistor m6, and the gate of the second bias voltage crystal m7 is connected to the second bias voltage vbs, wherein the second bias voltage The transistor m7 and the clamping transistor m6 are connected in series between the power supply VDD and the image output node VL.

The third diagram illustrates a timing diagram of related signals of the digital double sampling circuit 100 according to an embodiment of the present invention. In order to show the characteristics of this embodiment, only the sun-light condition is displayed. During the reset phase of the digital double sampling performed by the digital double sampling circuit 100 (the period from t0 to t6), the reset signal Rx, the reset enable signal rst_en, and the clamp enable signal bs_en are first activated at time t0 (for example High level) for resetting the pixel circuit 11, resetting the comparator 12 and turning on the clamping circuit 15 respectively. At time t1, when the reset signal Rx becomes de-asserted (for example, a low level), the pixel circuit 11 is reset. Thereby, the video output node VL is clamped to the clamp voltage ΔV1 (generated by the clamp circuit 15).

At time t2, when the reset enable signal rst_en becomes inactive (such as a low level), the (reset switch SW) completes the reset of the capacitor Ci. Then, at time t3, when the clamp enable signal bs_en becomes inactive (for example, a low level), the clamp circuit 15 is turned off. Therefore, the video output node VL is no longer clamped. In addition, the image output node VL drops to 0 volts due to sunlight. Then, from time t4 to t5, when the ramp voltage Vramp decreases (its decrease is ΔV2), the counter 131 of the analog-to-digital converter 13 counts from 0 to N1 (that is, 2 ^m -1), thus (analog to The digital converter 13) generates a reset-ADC value. According to one of the features of this embodiment, in the reset phase, the capacitor Ci is reset after the closing of the clamp circuit 15 (time t3) (time t2), but before the ramp voltage Vramp starts to fall (time t4).

In the signal phase of the digital double sampling performed by the digital double sampling circuit 100 (the period from t6 to t8), the transmission transistor m1 is first turned on at time t6 to transmit the image signal of the photodiode PD to the floating diffusion node FD. Then, from time t7 to t8, when the ramp voltage Vramp decreases (its decrease is ΔV3), the counter 131 of the analog-to-digital converter 13 counts from 0 to N2 (that is, 2 ⁿ -1), thus (analog to The digital converter 13) generates a signal-ADC value. In the example of 10-bit analog to digital conversion resolution, ΔV2 is approximately 20% of ΔV3, and N1/N2 is 255/1023.

According to the above embodiment, during the reset phase (especially during t3 to t6), since the clamp circuit 15 is turned off, the clamp circuit 15 will not accidentally turn on and output the current I1 to the image output node VL. Accordingly, the current I2 output by the column selection transistor m4 will not be affected (for example, reduced), especially in non-sunlight conditions or low-light conditions. Therefore, column fixed pattern noise (CFPN) will not be generated due to the critical voltage difference between the clamp transistor m6 (of the clamp circuit 15) and the second bias transistor m7.

The fourth figure illustrates the relevant signal timing diagram of the digital double sampling circuit 100 using a mechanism different from that of the third figure, and only shows the sun-light condition. Compared with the third figure, until the end of the reset phase, the clamp circuit 15 is always turned on by the active clamp enable signal bs_en. Therefore, during the reset phase, the image output node VL is always clamped at a certain level. However, the clamping circuit 15 may be turned on slightly, and thus the output current I1 is directed to the image output node VL. This current I1 affects the current I2 output by the column selection transistor m4, and therefore affects the transmission of the photodiode PD during the reset phase. Send signals, especially in non-sunlight or low-light situations. Therefore, line fixed image noise (CFPN) may be generated due to the critical voltage difference between the clamp transistor m6 (of the clamp circuit 15) and the second bias transistor m7.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.

100: Digital double sampling circuit

11: Pixel circuit

12: Comparator

13: Analog to digital converter

131: Counter

132: Memory

14: Digital detection subtractor

15: Clamping circuit

m1: Transmission transistor

m2: reset transistor

m3: source follower transistor

m4: column selection transistor

m5: first bias crystal

m6: clamped transistor

m7: second bias crystal

PD: photodiode

VDD: power supply

FD: Floating diffusion node

VL: image output node

Tx: transmit signal

Rx: reset signal

SEL: select signal

VB: first bias

I1: current

I2: current

VI: negative input node

Ci: Capacitor

Vramp: ramp voltage

rst_en: reset enable signal

dout: compare output

bs_en: Clamp enable signal

vbs: second bias

Claims (10)

A digital double sampling circuit, comprising: a pixel circuit of an image sensor; a comparator, the first input node of which is connected to the ramp voltage, and the second input node of which is connected to the image output node of the pixel circuit via a capacitor; A set switch, connected between the first input node and the second input node, for resetting the capacitor; an analog-to-digital converter that receives the comparison output of the comparator, and the analog-to-digital converter includes a A counter, when the ramp voltage ramps, the counter counts, thus generating a reset-ADC value in the reset phase, and a signal-ADC value in the signal phase; a digital detection subtractor, which generates the signal-ADC value The reset-ADC value is subtracted to generate a difference value, which represents a sampled output; and a clamp circuit, which generates a clamp voltage at the image output node; wherein in the reset phase, the clamp circuit is turned off at the capacitor to complete the reset Later, but the clamp circuit is turned off before the ramp voltage starts to slope; wherein the digital double sampling circuit sequentially performs the following steps in the reset phase: reset the pixel circuit, reset the capacitor, and turn on the clamp circuit; stop The pixel circuit is reset, thereby clamping the image output node to the clamping voltage; stopping the reset of the capacitor; closing the clamping circuit, so the image output node is no longer clamped to the clamping voltage; and when the ramp voltage When it is tilted, the counter counts, thereby generating the reset-ADC value; wherein the digital double sampling circuit sequentially performs the following steps in the signal stage: transmitting an image signal from the photodiode of the pixel circuit to the floating of the pixel circuit Diffusion node; and when the ramp voltage ramps, the counter counts, thus generating the signal-ADC value. According to the digital double sampling circuit described in item 1 of the scope of patent application, the comparator includes an operational amplifier, the positive input node of which is used as the first input node, and the negative input node of which is used as the second input node. According to the digital double sampling circuit described in claim 1, wherein the analog-to-digital converter includes a memory for temporarily storing the reset-ADC value and the signal-ADC value. According to the digital double sampling circuit described in item 1 of the scope of patent application, if the reset-ADC value is equal to the maximum count value of the counter in the reset stage, the digital detection subtractor sets the sampling output to the The maximum count value of the counter at this signal stage. According to the digital double sampling circuit described in item 4 of the scope of patent application, if the reset-ADC value is less than the maximum count value of the counter in the reset stage, the digital detection subtractor uses the difference as the sample Output. According to the digital double sampling circuit described in item 5 of the scope of patent application, the counter counts from 0 to 2m-1 in the reset phase, and counts from 0 to 2n-1 in the signal phase, where m and n are positive An integer and m is less than or equal to n. According to the digital double sampling circuit described in claim 1, wherein the clamping circuit includes: a clamping transistor that generates a clamping voltage at the image output node; and a bias crystal connected to the power supply and the clamping circuit Between the crystals; wherein the bias crystal and the clamp transistor are connected in series between the power supply and the image output node. According to the digital double sampling circuit described in item 7 of the scope of patent application, the gate of the clamp transistor is controlled by a clamp enable signal, and the gate of the bias transistor is connected to a bias voltage. The digital double sampling circuit according to the first item of the scope of patent application, wherein the pixel circuit includes: an optical diode; a transmission transistor connected between the floating diffusion node and the optical diode, and the transmission transistor The gate of the reset transistor is connected to the transmission signal; a reset transistor is connected between the power supply and the floating diffusion node, and the gate of the reset transistor is connected to the reset signal; a source follower transistor; and a row The select transistor, the source follower transistor and the column select transistor are connected in series between the power supply and the image output node, and the source follower transistor and the gate of the column select transistor are respectively connected to the floating Diffusion nodes and selection signals. The digital double sampling circuit according to item 9 of the scope of patent application further includes: a bias crystal connected between the image output node and ground, and the gate of the bias crystal is connected to the bias voltage.

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