TWI701719B - Method for making a semiconductor device - Google Patents

Abstract

The present disclosure provides a method for making a semiconductor device. The method for making a semiconductor device comprises : providing a first semiconductor layer comprising a first area; forming a second semiconductor layer on the first area, wherein the second semiconductor layer comprising a dopant, and a doping concentration of the dopant in the second semiconductor layer is higher than a doping concentration of the dopant in the first semiconductor layer; introducing the dopant of the second semiconductor layer into the first area of the first semiconductor layer.

Description

Method of manufacturing semiconductor element

The content of this application relates to a method of manufacturing a semiconductor device, in particular to a method of introducing dopants into a semiconductor layer.

In the process of manufacturing semiconductor devices, doping is a common step. In the existing technology, if a dopant is to be doped to a desired area, a mask is used to cover the area not to be doped to expose the desired area, and the exposed area is exposed to a full dopant. In the environment of impurities, the exposed area is in contact with the dopant, and the dopant diffuses into the exposed area.

The present application provides a method of manufacturing a semiconductor device, which includes: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region, the second semiconductor layer including a dopant, and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; and the dopant of the second semiconductor layer enters the first region of the first semiconductor layer to increase the dopant The concentration in the first zone.

The present invention provides a method of manufacturing a semiconductor device, which includes: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region, the second semiconductor layer including a dopant, and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; the dopant of the second semiconductor layer enters the first semiconductor layer Area to increase the concentration of dopants in the first area; and to form a light emitting structure, which includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. Active area between conductive semiconductor layers.

The present invention provides a method of manufacturing a semiconductor light emitting element, which includes: providing a first semiconductor structure, the first semiconductor structure including a first region; forming a semiconductor layer on the first semiconductor structure, the semiconductor layer including a dopant, And the concentration of the dopant in the semiconductor layer is higher than the concentration of the dopant in the first semiconductor structure; and the dopant of the semiconductor layer is diffused into the first region of the first semiconductor structure to improve the dopant in the first semiconductor structure. The concentration in an area.

10.40: Growth substrate

401, 101: upper surface

20: The first semiconductor layer

21, 91: The first area

22, 92: second area

30: second semiconductor layer

50: epitaxial structure

60: The first mirror

70: second mirror

80: light-emitting structure

90: The first semiconductor structure

100: semiconductor layer

110: third mirror

120: Semiconductor contact layer

130: first electrode

140: second electrode

Fig. 1A to Fig. 1D are an embodiment of the method of manufacturing a semiconductor device according to the application; Fig. 2 is the dopant concentration of an embodiment of a semiconductor device manufactured by the method shown in Fig. 1A to Fig. 1D Figure 3A to Figure 3G is another embodiment of the method for manufacturing a semiconductor device according to the content of this application; Figure 4 is a diagram of the first semiconductor structure of one embodiment shown in Figure 3D The relationship between the first dopant concentration and the doping depth; and FIG. 5 is an embodiment of the semiconductor device manufactured by the method in FIG. 3A to FIG. 3G.

The following embodiments will accompany the drawings to illustrate the concept of the application. In the drawings or descriptions, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of the element Can be expanded or contracted. It should be noted that elements not shown in the figure or not described in the specification can be in the form known to those skilled in the art, and the description of the same technical features may be omitted in each embodiment in order to avoid redundancy.

In the content of this application, unless otherwise specified, the semiconductor material disclosed in this application may contain a combination of various elements. For example, the general formula AlGaAs represents Al _x Ga _(1-x) As, where 0≦x≦1; AlInP stands for Al _x In _(1-x) P, where 0≦x≦1; the general formula AlGaInP stands for (Al _y Ga _(1-y) ) _1-x In _x P, where 0≦x≦1, 0≦y ≦1; the general formula AlGaN represents Al _x Ga _(1-x) N, where 0≦x≦1; the general formula AlAsSb represents AlAs _(1-x) Sb _x , where 0≦x≦1; the general formula InGaAsP represents In _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦y≦1; the general formula AlGaAsP represents Al _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦ y ≦ 1; InGaAsN representative of the general formula _{In x Ga 1-x As 1} -y N y,, where 0 ≦ x ≦ 1,0 ≦ y ≦ 1; InGaAs on behalf of the general formula _{In x Ga 1-x As,} , wherein 0 ≦x≦1; the general formula InGaN represents In _x Ga _1-x N, where 0≦x≦1; and the general formula InGaP represents In _x Ga _1-x P, where 0≦x≦1. Adjusting the content of elements can achieve different purposes, such as adjusting the energy level or adjusting the main wavelength or peak wavelength.

FIG. 1A to FIG. 1D are an embodiment of the method for manufacturing a semiconductor device according to the application. In this embodiment, the method for manufacturing a semiconductor device includes the steps: a. As shown in FIG. 1A, a growth substrate 10 is provided, which has an upper surface 101; b. As shown in FIG. 1A, a first semiconductor is formed The layer 20 is on the upper surface 101 of the growth substrate 10. The first semiconductor layer 20 includes a first region 21 and a second region 22. The method of forming the first semiconductor layer 20 includes epitaxial growth; c. as shown in Figure 1A As shown, a second semiconductor layer 30 is formed on the first semiconductor layer 20, wherein the second semiconductor layer 30 includes a first dopant, and the concentration of the first dopant in the second semiconductor layer 30 is higher than that of the first dopant. The concentration of a dopant in the first semiconductor layer 20; in one embodiment, the concentration of the first dopant in the second semiconductor layer 30 is not less than 1×10 ¹⁸ /cm ³ , and preferably, is between 1×10 ¹⁹ /cm ³ to 1x10 ²² /cm ³ (both included), wherein the method of forming the second semiconductor layer 30 includes epitaxial growth; in one embodiment, the thickness of the second semiconductor layer 30 may be greater than that of the first semiconductor layer 30. The thickness of the semiconductor layer 20, preferably, the thickness of the second semiconductor layer 30 is not less than 300 angstroms (Å), and preferably, not more than 0.5 microns (um); in one embodiment, the thickness of the second semiconductor layer 30 The thickness may also be less than the thickness of the first semiconductor layer 20; d. As shown in Figure 1B, the second semiconductor layer 30 is patterned so that the patterned second semiconductor layer 30 is located on the first semiconductor layer 20 Right above the area 21, that is, the first area 21 of the first semiconductor layer 20 overlaps the patterned second semiconductor layer 30 in the vertical direction, and the second area 22 of the first semiconductor layer 20 is not covered with the second area The semiconductor layer 30, specifically, the vertical direction refers to the direction perpendicular to the upper surface 101 of the growth substrate 10, and the method of patterning the second semiconductor layer 30 includes, but is not limited to, photolithography, imprinting, and electron beam Or a laser beam; and e. As shown in Figure 1C, the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 to enhance the first dopant in The concentration in the first region 21, where the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 includes, but is not limited to, heat treatment and/or pressure treatment .

After step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than the concentration of the first dopant in the second region 22. In an embodiment, the concentration of the first dopant in the second region 22 may be zero or close to zero. In an embodiment, preferably, the difference between the concentration of the first dopant in the first region 21 and the concentration of the first dopant in the second region 22 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, Greater than 1x10 ¹⁸ /cm ³ . In an embodiment, preferably, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, greater than 1×10 ¹⁸ /cm ³ . In an embodiment of the foregoing step c, when the thickness of the second semiconductor layer 30 is greater than the thickness of the first semiconductor layer 20, performing step e can make the diffusion of the first dopant more efficient, thereby making it easier to make the first dopant diffuse more efficiently. The difference between the concentration of the dopant in the first region 21 and the concentration in the second region 22 is greater than 1×10 ¹⁶ /cm ³ .

Specifically, in step b, the first region 21 is a region scheduled to diffuse the first dopant into step e.

In one embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have the first conductivity type, and the second semiconductor layer 30 has a A second conductivity type different from the first conductivity type. For example, when the first semiconductor layer 20 is p-type, the second semiconductor layer 30 is n-type. In this aspect, the first dopant in the second semiconductor layer 30 is an n-type dopant, such as silicon (Si ) Or tellurium (Te). For another example, when the first semiconductor layer 20 is n-type, the second semiconductor layer 30 is p-type. In this aspect, the first dopant in the second semiconductor layer 30 is a p-type dopant, such as zinc ( Zn), magnesium (Mg) or carbon (C). Then, after step e, the first region 21 of the first semiconductor layer 20 is changed to have a third conductivity type, which can be the same as the second conductivity type and different from the first conductivity type , And the second region 22 of the first semiconductor layer 20 still has the first conductivity type. For example, after step e, the first region 21 of the first semiconductor layer 20 is n-type, and the second region 22 of the first semiconductor layer 20 is p-type. For another example, after step e, the first region 21 of the first semiconductor layer 20 is One region 21 is p-type, and the second region 22 of the first semiconductor layer 20 is n-type. In detail, since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and is in indirect or direct contact with the upper surface of the first region 21, the first semiconductor layer The second region 22 of the body layer 20 is not covered with the second semiconductor layer 30. Therefore, in step e, the first dopant of the second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20, and The second region 22 of the first semiconductor layer 20 is not substantially affected. Therefore, after step e, the conductivity type of the first region 21 of the first semiconductor layer 20 will be changed to a third conductivity type, and this third conductivity type may be the same as the second conductivity type of the second semiconductor layer 30 The second region 22 of the first semiconductor layer 20 still has the first conductivity type. The "indirect contact" in this application means that there may be one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer and enter the first region twenty one. When the embodiment in which the third conductivity type of the first region 21 is different from the first conductivity type of the second region 22 is applied to a semiconductor device, the first semiconductor layer 20 can be used as a current confinement structure to allow current to flow selectively The first area 21 or the second area 22.

In one embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have the first conductivity type, and the second semiconductor layer 30 has a The second conductivity type that is the same as the first conductivity type, for example, the first conductivity type and the second conductivity type are both p-type or both n-type. Since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and in indirect or direct contact with the upper surface of the first region 21, the second region 22 of the first semiconductor layer 20 Is not covered with the second semiconductor layer 30, so in step e, the first dopant of the second semiconductor layer 30 will enter the first region 21 of the first semiconductor layer 20, and the second region of the first semiconductor layer 20 22 has not been substantially affected. The "indirect contact" referred to in this application means that there is one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer and enter the first region 21 . Therefore, after step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 will increase, for example, the concentration is greater than 1×10 ¹⁶ /cm ³ , and the first region 21 of the first semiconductor layer 20 The concentration of the first dopant in the second region 22 is greater than the concentration of the first dopant in the second region 22, and the concentration of the first dopant in the second region 22 may be zero or close to zero, for example. Therefore, after step e, the first region 21 and the second region 22 of the first semiconductor layer 20 have different electrical resistances. When the embodiment in which the first region 21 and the second region 22 have different electrical resistance values is applied to a semiconductor device, the first semiconductor layer 20 can be used as a current distribution structure to make the flow into the first region 21 and the second region 22 The current value is different.

In one embodiment, before forming the first semiconductor layer 20 on the upper surface 101 of the growth substrate 10 in step b, the method of manufacturing the semiconductor device further includes forming a third semiconductor layer (not shown) by epitaxial growth. On the upper surface 101 of the growth substrate 10, the third semiconductor layer has a fourth conductivity type, which is the same as the second conductivity type of the second semiconductor 30 formed in step c and different from the first semiconductor layer The first conductivity type 20 has, for example, when the fourth conductivity type is n-type, the first conductivity type is p-type, and the second conductivity type is n-type.

In one embodiment, after step e, the method for manufacturing a semiconductor device may further include a step f, removing the patterned second semiconductor layer 30, as shown in FIG. 1D. For example, the patterned second semiconductor layer 30 is removed by etching, grinding, laser cutting, or the like.

Figure 2 is a diagram showing the relationship between the dopant concentration and the doping depth of an embodiment of a semiconductor device fabricated using the method shown in Figures 1A to 1D. In this embodiment, the thickness of the growth substrate 10 is about 350um. The growth substrate is an n-type conductive substrate with a dopant, and the thickness of the first semiconductor layer 20 is about 500 angstroms. The circular mark in Figure 2 shows the relationship between the dopant concentration of the growth substrate 10 and the doping depth, and the triangle mark shows the concentration and doping of the first dopant in the first region 21 of the first semiconductor layer 20 Deep relationship. The position with a depth of 0um is the upper surface of the first semiconductor layer 20. It can be seen from the figure that at least a part of the first region 21 of the first semiconductor layer 20 of this embodiment, preferably, in the first region 21 In a region adjacent to the upper surface of the first semiconductor layer 20, The concentration of the first dopant increases as the doping depth increases, that is, at least a part of the first region 21 is farther away from the upper surface of the first semiconductor layer 20, the higher the concentration of the first dopant is.

In one embodiment, after the step of removing the patterned second semiconductor layer 30, the method of manufacturing a semiconductor device further includes forming a light emitting structure (not shown) on the first semiconductor layer 20, the light emitting structure including a The first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active region located between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types. For example, the first conductivity type semiconductor layer is n-type that provides electrons, and the second conductivity type semiconductor layer is p-type that provides electron holes, and the energy gap of the first conductivity type semiconductor layer and the energy gap of the second conductivity type semiconductor layer are both larger than The energy gap of the active area.

In one embodiment, before forming the first semiconductor layer 20, the method of manufacturing a semiconductor device further includes forming a light-emitting structure (not shown) on the growth substrate 10. The light-emitting structure of this embodiment can be the same as that of the previous embodiment. The light-emitting structure is the same or similar.

The active area of the present application can emit radiation with a peak wavelength. In one embodiment, when the light-emitting element is a light-emitting diode, the radiation is non-coordinated dimming with a far field angle greater than 60 degrees, preferably greater than 80 degrees. In another embodiment, when the light-emitting element is a laser light-emitting element, the radiation is co-dimmable with a far field angle of less than 25 degrees, preferably less than 20 degrees, and more preferably, less than 15 degrees.

In one embodiment, in step c, the second semiconductor layer 30 is formed on the first semiconductor layer 20 at a first temperature. Preferably, the first temperature is not lower than 550° C. and not higher than 700 ℃, and more preferably, the first temperature is not lower than 580℃ and not higher than 670℃.

In one embodiment, the heat treatment to make the first dopant of the patterned second semiconductor layer 30 enter the first region 21 of the first semiconductor layer 20 is operated at a second temperature, which is lower than the formation temperature. The first temperature of the second semiconductor layer 30. Preferably, the difference between the first temperature and the second temperature is not more than 50°C, and not less than 5°C, and more preferably, not more than 30°C. Specifically, the heating treatment method includes, but is not limited to, putting the structure formed in step d into a furnace tube for heating treatment, or putting the structure formed in step d into metal organic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) heat treatment in the chamber of the machine.

The first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer include three-five-five semiconductor materials, for example, include intrinsic three-five five semiconductor materials or three-five five semiconductor materials with a dopant, for example, include a concentration Group ^III- V semiconductor materials with dopants greater than 1x10 ¹⁶ /cm ³ , or group ^III- V semiconductors containing dopants with a concentration between 1x10 ¹⁸ /cm ³ and 1x10 ²² /cm ³ (both included) material. For another example, the third and fifth group semiconductor material may include aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), InGaN (indium gallium nitride), or AlGaN (aluminum gallium nitride) Wait. In one embodiment, the first semiconductor layer 20 includes aluminum gallium indium phosphide (AlGaInP), the second semiconductor layer 30 includes aluminum gallium arsenide (AlGaAs), and the third semiconductor layer includes aluminum gallium arsenide (AlGaAs). The first dopant in the second semiconductor layer 30 is zinc (Zn).

The semiconductor elements of the present application may include, but are not limited to, light-emitting diodes, laser elements, light sensors, solar cells, field-effect transistors or power elements, etc. The method of the present application covers the first region 21 of the first semiconductor layer 20 by the patterned second semiconductor layer 30, and in step e, diffuses the first dopant in the patterned second semiconductor layer 30 The first region 21 of the first semiconductor layer 20 is entered, so that the first region 21 of the first semiconductor layer 20 includes the first dopant after step e. The method of the present application uses a patterned semiconductor layer as a dopant Source, steps a to c and step e can be carried out in the chamber of a metalorganic chemical vapor deposition (MOCVD) machine, which can reduce the use of additional process equipment such as vapor deposition machine and High-temperature furnaces, etc., therefore, compared with the traditional doping process, the technology of this application at least includes that it can greatly reduce the equipment cost of manufacturing semiconductor devices, while reducing the transfer time of the doping process between different process equipment, increasing the convenience of the process and the unit time. Yield and so on.

3A to 3G are an embodiment of the method of manufacturing a semiconductor device according to the application. In this embodiment, the semiconductor device is a semiconductor light emitting device, for example, a laser light emitting device. The method of manufacturing a semiconductor light emitting device includes the steps: a. As shown in FIG. 3A, a growth substrate 40 is provided, which has an upper surface 401; b. As shown in FIG. 3A, an epitaxial structure is formed on the upper surface 401 50, which includes a first reflector 60, a second reflector 70, and a light emitting structure 80 located between the first reflector 60 and the second reflector 70, wherein the light emitting structure 80 can be substantially the same as previously described in this application. The light-emitting structures mentioned in the above embodiments are the same or similar. The first reflecting mirror 60 and the second reflecting mirror 70 each have a conductivity type, and the conductivity type of the first reflecting mirror 60 is different from the conductivity type of the second reflecting mirror 70, for example, the first reflecting mirror 60 is an n-type, The second mirror 70 is p-type; c. As shown in FIG. 3A, a first semiconductor structure 90 is formed. The first semiconductor structure 90 includes a first region 91 and a second region 92, in which the first semiconductor structure is formed The method 90 includes epitaxial growth; preferably, before performing the subsequent doping step f, the conductivity type of the first semiconductor structure 90 is different from the conductivity type of the second mirror 70, for example, the second mirror 70 is p-type, the conductivity type of the first semiconductor structure 90 is n-type, that is, the conductivity types of the first region 91 and the second region 92 of the first semiconductor structure 90 are both n-type; d. as shown in Figure 3A , Forming a semiconductor layer 100 on the first semiconductor structure 90, the semiconductor layer 100 includes a first dopant, and the concentration of the first dopant in the semiconductor layer 100 is higher than that of the first dopant in the first semiconductor structure Concentration within 90. In an embodiment, the concentration of the first dopant in the semiconductor layer 100 is not less than 1x10 ¹⁸ /cm ³ , and preferably, it is between 1x10 ¹⁹ /cm ³ and 1x10 ²² /cm ³ (both are Including), wherein the method of forming the semiconductor layer 100 includes epitaxial growth; in one embodiment, the thickness of the semiconductor layer 100 may be greater than the thickness of the first semiconductor structure 90, preferably, the thickness of the semiconductor layer 100 is not less than 300 angstroms ( Å), and more preferably, the thickness of the semiconductor layer 100 is not greater than 0.5 micrometer (um); in one embodiment, the thickness of the second semiconductor layer 30 may also be less than the thickness of the first semiconductor layer 20; e. such as section 3B As shown in the figure, the semiconductor layer 100 is patterned so that the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90, that is, the first region 91 of the first semiconductor structure 90 is in the vertical direction It overlaps with the patterned semiconductor layer 100, and the second region 92 of the first semiconductor structure 90 is not covered with the semiconductor layer 100. Specifically, the vertical direction refers to the direction perpendicular to the upper surface 401 of the growth substrate 40, where The method of patterning the first semiconductor layer 100 includes, but is not limited to, lithography, imprinting, electron beam or laser beam; f. As shown in Figure 3C, the first patterned semiconductor layer 100 The dopant diffuses into the first region 91 of the first semiconductor structure 90 to increase the concentration of the first dopant in the first region 91, wherein the first dopant of the patterned semiconductor layer 100 enters the first semiconductor The method of the first region 91 of the layer includes, but is not limited to, heat treatment and/or pressure treatment; g. As shown in FIG. 3D, selectively, but preferably, removing the patterned semiconductor layer 100, for example , The patterned semiconductor layer 100 is removed by etching, grinding or laser cutting, etc.; h. As shown in Figure 3E, a third mirror 110 is formed on the first semiconductor structure 90, the third mirror 110 has a conductivity type, which is the same as the conductivity type of the second mirror 70. For example, in this embodiment, the third mirror 110 is p-type and the second mirror 70 is p-type; i. As shown in FIG. 3F, optionally, but preferably, a semiconductor contact layer 120 is formed on the third mirror 110, wherein the method of forming the semiconductor contact layer 120 includes epitaxial growth; and j. As shown in FIG. 3G Optionally, but preferably, a first electrode 130 is formed on the semiconductor contact layer 120 and a second electrode 140 is formed on the other side of the growth substrate 40 opposite to the epitaxial structure 50, wherein the first electrode is formed The method of 130 and the second electrode 140 includes vapor deposition.

After step f, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than the concentration of the first dopant in the second region 92 of the first semiconductor structure 90. In an embodiment, the concentration of the first dopant in the second region 92 may be zero or close to zero. In an embodiment, preferably, the difference between the concentration of the first dopant in the first region 91 and the concentration of the first dopant in the second region 92 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, Greater than 1x10 ¹⁸ /cm ³ . In an embodiment, preferably, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, greater than 1×10 ¹⁸ /cm ³ .

Specifically, in step c, the first region 91 is a region scheduled to diffuse the first dopant into step f.

FIG. 4 is a diagram showing the relationship between the concentration of the first dopant and the depth in the first semiconductor structure 90 of the embodiment shown in FIG. 3D. The position with a depth of 0um is the upper surface of the first semiconductor structure 90, as shown in Figure 4, at least a part of the first region 91, preferably, the first region 91 is adjacent to the first semiconductor structure 90 In the surface area, the concentration of the first dopant increases with the depth of doping As the degree increases, the concentration of the first dopant increases, that is, at least a part of the first region 91 is farther away from the upper surface of the first semiconductor structure 90, the higher the concentration of the first dopant is.

In one embodiment, before step f, the conductivity type of the patterned semiconductor layer 100 is different from the conductivity type of the first semiconductor structure 90, for example, the conductivity type of the patterned semiconductor layer 100 is p-type , The first semiconductor structure 90 is n-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is a p-type dopant, such as zinc (Zn), magnesium (Mg), carbon (C ) Or beryllium (Be). In this example, the first dopant is zinc (Zn). For another example, the conductivity type of the patterned semiconductor layer 100 is n-type, and the first semiconductor structure 90 is p-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is n-type doping. Materials such as silicon (Si), tellurium (Te) or germanium (Ge). Next, in step f, since the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90 and in indirect or direct contact with the upper surface of the first region 91, the first semiconductor structure 90 The second region 92 is not covered with the semiconductor layer 100. Therefore, the first dopant in the patterned semiconductor layer 100 will enter the first region 91 of the first semiconductor structure 90, and the second region of the first semiconductor structure 90 Area 92 is not substantially affected. The “indirect contact” in this application means that there may be one or more buffer layers between the upper surface of the first region 91 and the semiconductor layer 100, but the first dopant can still pass through the buffer layer and enter the first region 91. Therefore, after step f, the conductivity type of the first region 91 of the first semiconductor structure 90 will be changed to be the same as the conductivity type of the second mirror 70, and the conductivity of the second region 92 of the first semiconductor structure 90 will be changed. The type is still different from the conductivity type of the second mirror 70. Specifically, after step e, the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as that of the second reflector 70, and the conductivity type of the first region 91 is different from that of the second region 92 Conductivity type. For example, after step e, the conductivity type of the second mirror 70 is p-type, the conductivity type of the first region 91 of the first semiconductor structure 90 is p-type, but the first semiconductor structure The conductivity type of the second region 92 of the body structure 90 is n-type. For another example, the conductivity type of the second reflector 70 is n type, the conductivity type of the first region 91 of the first semiconductor structure 90 is n type, but the conductivity type of the second region 92 of the first semiconductor structure 90 is p-type.

In one embodiment, in step d, the semiconductor layer 100 is formed on the first semiconductor structure 90 at a first temperature. Preferably, the first temperature is not lower than 550°C and not higher than 700°C, More preferably, the first temperature is not lower than 580°C and not higher than 670°C.

In one embodiment, the heat treatment to cause the first dopant of the patterned semiconductor layer 100 to enter the first region 91 of the first semiconductor structure 90 is operated at a second temperature, which is lower than the formation of the semiconductor layer The first temperature of 100. Preferably, the difference between the first temperature and the second temperature is not more than 50°C, and not less than 5°C, and more preferably, not more than 30°C. Specifically, the heating treatment method includes, but is not limited to, putting the structure formed in step e into a furnace tube for heating treatment, or putting the structure formed in step d into metal organic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) heat treatment in the chamber of the machine.

In one embodiment, the light-emitting structure may further include a spacer layer (not shown) located between the active area and the first conductivity type semiconductor layer and/or between the active area and the second conductivity type semiconductor layer, so as to adjust the light emission. The thickness of the structure is substantially close to or equal to a thickness of nλ/2, where λ is the peak wavelength of radiation emitted by the active region, and n is a positive integer. The material of the spacer layer includes a Group III, Group 5 semiconductor material, such as aluminum gallium arsenide (AlGaAs).

Fig. 5 is an embodiment of a semiconductor device manufactured by the method shown in Fig. 3A to Fig. 3G. When driving the laser light emitting element as shown in Figure 5, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as that of the second mirror 70 and the third mirror 70 located on both sides of the first semiconductor structure 90, respectively. The conductivity type of the reflector 110, while the conductivity type of the second region 92 of the first semiconductor structure 90 is not Same as the conductivity type of the second mirror 70 and the third mirror 110 located on both sides of the first semiconductor structure 90, so the current will be restricted by the second region 92 of the first semiconductor structure 90 and cannot pass through, and then concentrated by The first region 91 of the first semiconductor structure 90 passes and flows into the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow current to pass through the predetermined first region 91.

The first reflector 60, the second reflector 70, and the third reflector 110 respectively include a plurality of alternating first refractive index semiconductor layers (not shown) and second refractive index semiconductor layers (not shown). The first refractive index The semiconductor layer has a first refractive index, and the second refractive index semiconductor layer has a second refractive index, wherein the first refractive index is higher than the second refractive index. The materials of the first reflector 60, the second reflector 70, and the third reflector 110 include a group-three-five semiconductor material, such as aluminum gallium arsenide Al _x Ga _(1-x) As/Al _y Ga _(1-y) As, where x is not equal to y, and the content of aluminum and gallium can be adjusted to reflect a wavelength range to be reflected. The first refractive index semiconductor layer and the second refractive index semiconductor layer have a thickness close to or equal to λ/4n, where λ is the peak wavelength of the radiation emitted by the active region 22, and n is the refractive index of the layer. The first mirror 60 has a reflectivity exceeding 99% at the peak wavelength. The second reflecting mirror 70 and the third reflecting mirror 110 have a reflectivity exceeding 98% at the peak wavelength. Preferably, for the peak wavelength, the reflectivity of the first reflector 60 is greater than the reflectivity of the second reflector 70 and the third reflector 110. The logarithm of the first mirror 60 is greater than the sum of the logarithms of the second mirror 70 and the third mirror 110, wherein a first refractive index semiconductor layer and a second refractive index semiconductor layer adjacent to the first refractive index semiconductor layer are regarded as A pair. In an embodiment, preferably, the logarithm of the first mirror 60 is greater than 15, and more preferably, greater than 30 and less than 80. In an embodiment, preferably, the sum of the logarithms of the second mirror 70 and the third mirror 110 is greater than 15, and more preferably, greater than 20 and less than 80.

In one embodiment, the first semiconductor structure 90 and the semiconductor layer 100 include Group III and V semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), InGaN ( Indium gallium nitride) or AlGaN (aluminum gallium nitride). In one embodiment, the first semiconductor structure 90 includes aluminum gallium indium phosphide (AlGaInP), and the semiconductor layer 100 includes aluminum gallium arsenide (AlGaAs). More preferably, in one embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.4≦x≦1 and 0≦y≦1. In another embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.49≦x≦0.51, 0≦y≦0.6. In one embodiment, the first dopant in the semiconductor layer 100 is zinc (Zn). In one embodiment, the first semiconductor structure 90 has a thickness close to or equal to λ/4n, where λ is the peak wavelength of the radiation emitted by the active region 22, and n is the refractive index of the layer. In one embodiment, the first semiconductor structure 90 can replace one of the first refractive index semiconductor layer or the second refractive index semiconductor layer of the second mirror 70 or the third mirror 110.

In one embodiment, the first refractive index semiconductor layer in one pair of the second mirror 70 is an aluminum-containing semiconductor layer, and its aluminum content is compared with the aluminum in the first refractive index semiconductor layer in other pairs. High content. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9≦x≦1.0. In this embodiment, before step j, the method for manufacturing a semiconductor light-emitting element further includes oxidizing the aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidizes to the inside to make the aluminum-containing semiconductor layer. The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than zero. Specifically, the oxidation method includes wet thermal oxidation (wet thermal oxidation). When driving the laser light emitting element of this embodiment, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as the conductivity type of the second mirror 70 and the third mirror 110 located on both sides, The conductivity type of the second region 92 of the first semiconductor structure 90 is different from the conductivity type of the second mirror 70 and the third mirror 110 on both sides, so the current will be absorbed by the second region 92 of the first semiconductor structure 90 It is restricted and cannot pass, and then enters the second mirror 70 through the first region 91 of the first semiconductor structure 90. Further, since the oxide part is an insulating material, the current entering the second reflector 70 will be restricted by the oxide part and cannot pass, and then passes through the semiconductor part in the aluminum-containing semiconductor layer and enters the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow current to pass through the predetermined first region 91.

In one embodiment, the first refractive index semiconductor layer of one pair of the third mirror 110 is an aluminum-containing semiconductor layer, and its aluminum content is compared with the aluminum content of the first refractive index semiconductor layer of the other pairs high. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9≦x≦1.0. In this embodiment, before step j, the method of manufacturing a semiconductor light-emitting element further includes oxidizing the aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidizes to the inside to make the aluminum-containing semiconductor layer. The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than zero. Specifically, the oxidation method includes wet thermal oxidation (wet thermal oxidation). When the laser light emitting element of this embodiment is driven, since the oxide part is an insulating material, the current entering the third mirror 110 is restricted by the oxide part and cannot pass, and then passes through the semiconductor part in the aluminum-containing semiconductor layer Into the first semiconductor structure 90, further, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as the conductivity type of the second mirror 70 and the third mirror 110 on both sides, The conductivity type of the second region 92 of a semiconductor structure 90 is different from the conductivity types of the second mirror 70 and the third mirror 110 on both sides, so the current will be limited by the second region 92 of the first semiconductor structure 90 It cannot pass, and then enters the light emitting structure 80 through the first region 91 of the first semiconductor structure 90.

The active region includes single heterostructure (SH), double heterostructure (DH) or multiple quantum well (MQW). Preferably, the active region includes a multiple quantum well (MQW), which includes alternating well layers and barrier layers. The energy level of each barrier layer is greater than the energy level of one of the well layers. The peak wavelength emitted by the active region can be changed by changing the thickness or material of the well layer. Preferably, the material of the well layer includes a group III-V semiconductor material, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), or InGaN (indium gallium nitride). The barrier layer includes three-five group semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), or AlGaN (aluminum gallium nitride).

In one embodiment, the growth substrate 10 or 40 has a sufficient thickness to support the layer or structure to be grown on the substrate 10 or 40 later. Preferably, the thickness of the growth substrate 10 or 40 is not less than 100 microns, and preferably, it does not exceed 250 microns. The growth substrate 10 or 40 is a single crystal and includes a semiconductor material, for example, includes a group three or five semiconductor material or a group four semiconductor material. In one embodiment, the growth substrate 10 or 40 includes a group III-V semiconductor material having an n-type or p-type. For example, the third and fifth group semiconductor materials include n-type gallium arsenide (GaAs), and the n-type dopant is silicon (Si).

The first electrode 130 and the second electrode 140 are used to connect to an external power source and conduct a current between them. The material of the first electrode 130 and the second electrode 140 includes a transparent conductive material or a metal material. Transparent conductive materials include transparent conductive oxides, metal materials include gold (Au), platinum (Pt), germanium gold nickel (GeAuNi), titanium (Ti), beryllium gold (BeAu), germanium gold (GeAu), aluminum (Al) , Zinc gold (ZnAu) or nickel.

The first electrode 130 forms a low-resistance contact or ohmic contact with the third mirror 110 through the semiconductor contact layer 120, wherein the resistance between the first electrode 130 and the third mirror 110 is lower than 10 ^-2 ohm-cm. The conductivity type of the semiconductor contact layer 120 is the same as the conductivity type of the third mirror 110. In one embodiment, the semiconductor contact layer 120 is p-type and has a high p-type doping concentration, for example, higher than 1x10 ¹⁸ /cm ³ , and preferably, higher than 1x10 ¹⁹ /cm ³ , and more preferably, Between 1x10 ¹⁹ /cm ³ and 5x10 ²² /cm ³ (both included). The material of the semiconductor contact layer 120 includes a group III-V semiconductor material, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs).

Methods of epitaxy growth include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (molecular beam epitaxy). beam epitaxy, MBE) or liquid-phase epitaxy (LPE).

It should be noted that the embodiments listed in this application are only used to illustrate the application, and are not used to limit the scope of the application. Any obvious modification or alteration of this application by anyone does not depart from the spirit and scope of this application. The same or similar components in different embodiments, or components with the same number in different embodiments have the same physical or chemical properties. In addition, the above-mentioned embodiments in this application can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between specific components and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the protection of the rights of this application as follows.

40‧‧‧Growth substrate

50‧‧‧Epitaxial structure

60‧‧‧First reflector

92‧‧‧Second area

70‧‧‧Second mirror

80‧‧‧Light-emitting structure

90‧‧‧First semiconductor structure

91‧‧‧First area

100‧‧‧Semiconductor layer

Claims (10)

A method of manufacturing semiconductor components, including: Provide an active area; Forming a first reflecting mirror and a second reflecting mirror, respectively located on both sides of the active area; Forming a first semiconductor structure including a first region and a second region; Forming a second semiconductor layer on the first semiconductor structure; Allowing a dopant to enter the first semiconductor structure; and The second semiconductor layer is completely removed. According to the method of manufacturing a semiconductor device described in the first item of the scope of the patent application, the second semiconductor layer is formed on the first region. The method of manufacturing a semiconductor device as described in the second item of the scope of the patent application further includes heat treatment and/or pressure treatment of the second semiconductor layer so that the dopant enters the first semiconductor structure from the second semiconductor. area. According to the method of manufacturing a semiconductor device as described in item 3 of the scope of patent application, the conductivity type of the first region is the same as the conductivity type of the first mirror or the second mirror. The method for manufacturing a semiconductor device as described in claim 1, wherein the concentration of the dopant in the first region is greater than the concentration of the dopant in the second region, and the concentration of the dopant in the first region The difference between the concentration of the dopant and the concentration of the dopant in the second region is greater than 1´10 ¹⁶ /cm ³ . According to the method for manufacturing a semiconductor device as described in item 1 of the scope of the patent application, the concentration of the dopant in the first region is greater than 1´10 ¹⁸ /cm ³ . The method of manufacturing a semiconductor device as described in the first item of the scope of the patent application further includes forming a third mirror on the first semiconductor structure. The method for manufacturing a semiconductor device as described in the first item of the patent application, wherein the dopant contains zinc (Zn), magnesium (Mg) or carbon (C). According to the method for manufacturing a semiconductor device as described in claim 1, wherein the first semiconductor structure includes Group III or V semiconductor materials. According to the method of manufacturing a semiconductor device described in the first item of the scope of the patent application, the semiconductor device can emit non-coherent dimming with a far field angle greater than 60 degrees or co-dimming with a far field angle less than 25 degrees.

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