TWI799073B - Data serializer, latch data device using the same and controlling method thereof - Google Patents

Abstract

A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

Description

Data serializer, latch data device using it and its control method

The present disclosure relates to an electronic component, an electronic device using the same and a control method thereof, and in particular to a data serializer, a latch data device using the same and a control method thereof.

With the development of semiconductor technology, various electronic components are constantly being introduced. For example, data buffers have been widely used in latch data devices. When a control signal of "1" is applied to the enable port of the data buffer, the data buffer outputs "0" or "1". When a control signal of "0" is applied to the enable port of the data buffer, the data buffer turns off the output (or outputs "Hi-Z").

In the data buffer, the output signal can rise to "1" or fall to "0". When the output signal is rising or falling, the data content cannot be read correctly. When the rise time is longer than the fall time and the control signal has a fixed period In the case of "1", the time length of "1" will be shorter than the time length of "0". In the case where the rise time is shorter than the fall time and the control signal has a fixed cycle time, the duration of "1" will be longer than the duration of "0".

In order to accurately read the "0" or "1" of the output signal, you can use the data valid window (data valid window), which excludes the combination of rising time and falling time. The "0" or "1" read in the data valid window is the accurate content. The difference between rise time and fall time can greatly affect the size of the valid data window.

The disclosure relates to a data serializer, a latch data device using the same and a control method thereof, which utilize a de-skew buffer to receive a complementary output signal to speed up Or slow down the formation of an output signal. Therefore, the rise time and fall time of the output signal become substantially the same. Since the difference between the rise time and the fall time has been greatly reduced, the data valid window (data valid window) can be greatly expanded.

According to an aspect of the present disclosure, a data serializer (data serializer) is proposed. The data serializer includes at least a data buffer and a de-skew buffer. The data buffer receives at least one input data and one control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is opposite to the input signal. The deskew buffer is used to receive the complementary output signal to speed up or slow down the formation of the output signal.

According to another aspect of the present disclosure, a latch data device is provided. The latch data device includes a latch circuit and an output transmitter. The output transmitter is connected to the latch circuit. The output transmitter includes a data serializer. The data serializer includes at least a data buffer and a de-skew buffer. The data buffer receives at least one input data and one control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is the opposite of the output signal. The de-skew buffer is used to receive the complementary output signal to speed up or slow down the formation of the output signal.

According to another aspect of the present disclosure, a method for controlling a data serializer is proposed, wherein the data serializer includes at least one data buffer and a de-skew buffer ). The control method includes the following steps. The data buffer receives an input data and a control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is the opposite of the output signal. The deskew buffer receives the complementary output signal to speed up or slow down the formation of the output signal.

In order to have a better understanding of the above and other aspects of the present disclosure, the following specific embodiments are described in detail in conjunction with the attached drawings as follows:

100: Latch data device

110: Latch circuit

120: output transmitter

C, CA, CB, CC, CD: control signal

C#: Complementary Control Signals

DA, DB, DC, DD: input data

DAB, DBB, DCB, DDB: complementary input data

Dout: output signal

Doutb: Complementary output signal

DB2: Deskew Buffer

DS2,DS3,DS4,DS5,DS6,DS7: data serializer

EN: enable port

I,IB: input ports

Ip1,Ip2,Ip3,Ip4,In1,In2,In3,In4: Current

IV11, IV12, IV21, IV22, IV23, IV24, IV25: inverter

L211,L212,L215,L216,L221,L222,L225,L226: dotted line

L213,L214,L217,L218,L223,L224,L227,L228: solid line

NM11, NM12, NM21, NM22, NM23, NM24, NM25, NM26: NMOS transistors

O, OB: output port

PG: buffer gate

PM11, PM12, PM21, PM22, PM23, PM24, PM25, PM26: PMOS transistor

t0, t1: time interval

T21, T22, T23, T24: time points

TB1, TB2, TB3, TB4, TB5, TB6, TB7, TB8, TB9, TB10, TB11, TB12, TB13, TB14: data buffer

tDV, tDV1, tDV3: data valid window

tF, tF1, tF2, tF3, tF4: fall time

tR, tR1, tR2, tR3, tR4: rise time

V1: first voltage

V2: second voltage

FIG. 1 shows a schematic diagram of a data buffer according to an embodiment.

Figure 2 shows the logic table of the data buffer.

FIG. 3 shows a circuit diagram of a data buffer according to an embodiment.

FIG. 4A is a schematic diagram of the control signal, input data and output signal voltage curves of the data buffer under the condition that the PMOS transistor operates slower than the NMOS transistor.

FIG. 4B is a schematic diagram of the control signal, input data and output signal voltage curves of the data buffer under the condition that the PMOS transistor operates faster than the NMOS transistor.

FIG. 5 shows a schematic diagram of a data serializer according to an embodiment.

Figure 6 shows the logic table of the data serializer.

FIG. 7 shows a circuit diagram of a data serializer according to an embodiment.

FIG. 8A shows the voltage curves of the control signal, input data, output signal and complementary output signal of the data serializer under the condition that the PMOS transistor operates slower than the NMOS transistor.

FIG. 8B shows the voltage curves of the control signal, input data, output signal and complementary output signal of the data serializer under the condition that the PMOS transistor operates faster than the NMOS transistor.

FIG. 9 shows a schematic diagram of a data serializer according to an embodiment.

FIG. 10 shows a circuit diagram of a data serializer according to an embodiment.

FIG. 11 shows a schematic diagram of a latched data device according to an embodiment.

FIG. 12 shows a schematic diagram of a data serializer according to another embodiment.

Figure 13 illustrates the output signal of Figure 12.

Fig. 14 shows a schematic diagram of a data serializer according to another embodiment.

FIG. 15 shows a schematic diagram of a data serializer according to another embodiment.

Figure 16 illustrates the output signal of Figure 15.

Fig. 17 shows a schematic diagram of a data serializer according to another embodiment.

Please refer to FIG. 1 , which shows a schematic diagram of a data buffer (data buffer) TB1 according to an embodiment. The data buffer TB1 is, for example, a tri-state buffer. The data buffer TB1 has an input port I, an enable port EN and an output port O. A control signal C is input to the enable port EN. An input data DA is input to the input port I. An output signal Dout is output from the output port O.

Please refer to FIG. 2, which shows the logic table of the data buffer TB1. When the control signal C input to the enable port EN is at a predetermined level, its value is "1"; when the control signal C input to the enable port EN is lower than the predetermined level, its value is "0". When the control signal C input to the enable port EN is "1", according to the content of the input data DA input from the input port I, the output port O of the data buffer TB1 outputs "0" or "1". Output signal Dout. When the control signal C input to the enable port EN is "0", the data buffer TB1 does not output (or outputs "Hi-Z").

Please refer to FIG. 3 , which shows a circuit diagram of a data buffer TB1 according to an embodiment. The data buffer TB1 includes a PMOS transistor PM11, a PMOS transistor PM12, an NMOS transistor NM11, an NMOS transistor NM12, an inverter IV11, and an inverter IV12. The PMOS transistor PM11 , the PMOS transistor PM12 , the NMOS transistor NM11 and the NMOS transistor NM12 are connected in series. The drain (or source) of the PMOS transistor PM11 is applied with a first voltage V1. The first voltage V1 is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM12 is applied with a second voltage V2. The inverter IV11 is connected to the input port I. The gate of the PMOS transistor PM12 and the gate of the NMOS transistor NM11 are connected to the inverter IV11. The inverter IV12 is connected between the enable port EN and the gate of the PMOS transistor PM11. The source (or drain) of the PMOS transistor PM12 and the drain of the NMOS transistor NM11 are connected to the output port O.

When the control signal C input to the enable port EN is "0", the PMOS transistor PM11 and the NMOS transistor NM12 are turned off, so the current Ip1 or the current In1 will not be formed, and the data buffer TB1 will not output (or output " Hi-Z").

When the control signal C input to the enable port EN is "1" and the input data DA input to the input port I is "1", the PMOS transistor PM11 and the PMOS transistor PM12 will be turned on, and the NMOS transistor NM11 will be turned off , so the current Ip1 will be formed, and the output signal Dout output from the output port O will rise to "1", which has the same value as the input data DA.

When the control signal input to the enable port EN is "1" and the input data DA input to the input port I is "0", the NMOS transistor NM11 and the NMOS transistor NM12 will be turned on and the PMOS transistor PM12 will be turned off. Therefore, the current In1 will be formed, and the output signal Dout output from the output port O will drop to "0", which is the same as the input data DA.

Please refer to Figure 4A, which shows the voltage curves of the control signal C, input data DA and output signal Dout of the data buffer TB1 under the condition that the PMOS transistors PM11 and PM12 operate slower than the NMOS transistors NM11 and NM12 schematic diagram. As shown in FIG. 4A, the rising time tR of the output signal Dout is longer than the falling time tF of the output signal Dout, so the time interval t1 of "1" is shorter than the time interval t0 of "0".

In order to accurately read the content of "0" or "1" of the output signal Dout, the data valid window tDV can be used, and the data valid window tDV excludes the combination of the rising time tR and the falling time tF. The "0" or "1" read in the data valid window tDV is the accurate content. The difference between the rising time tR and the falling time tF will greatly affect the size of the effective data window tDV.

Please refer to Figure 4B, which shows the voltage curves of the control signal C, input data DA, and output signal Dout of the data buffer TB1 under the condition that the PMOS transistors PM11 and PM12 operate faster than the NMOS transistors NM11 and NM12 schematic diagram. As shown in FIG. 4B , the rising time tR of the output signal Dout is shorter than the falling time tF of the output signal Dout, so the time interval t1 of "1" is longer than the time interval t0 of "0".

In order to accurately read the content of "0" or "1" of the output signal Dout, the data valid window tDV can be used, and the data valid window tDV excludes the combination of the rising time tR and the falling time tF. The "0" or "1" read in the data valid window tDV2 is the accurate content. The difference between the rising time tR and the falling time tF will greatly affect the size of the effective data window tDV.

The data buffer TB1 is widely used in electronic devices and latch data devices. For example, one or more data buffers may be used in a data serializer.

Please refer to FIG. 5 , which shows a schematic diagram of a data serializer DS2 according to an embodiment. The data serializer DS2 includes a data buffer and a de-skew buffer (de-skew buffer) DB2. The operation and control method of the data serializer DS2 are as follows. The data buffer TB2 at least receives the input data DA and the control signal C. When the control signal C is at a predetermined level (that is, "1"), the data buffer TB2 forms an output signal Dout and a complementary output signal Doutb (the value of which is opposite to the output signal Dout). The de-skew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

Please refer to Figure 6, which shows the logic table of the data serializer DS2. When the control signal C input to the enable port EN is at a predetermined level, the value is "1"; when the control signal C input to the enable port EN is lower than the predetermined level, the value is "0". When the control signal C input to the enable port EN is “1”, according to the input data DA input to the input port I, the output port O of the data buffer TB2 outputs an output signal Dout of “0” or “1”. When the control signal C input to the enable port EN is "1", according to the input to The input data DA of the input port I, the output port OB of the data buffer TB2 outputs a complementary output signal Doutb of "1" or "0". When the control signal C input to the enable port EN is "0", the data buffer TB2 does not output (or outputs "Hi-Z").

Please refer to FIG. 7, which shows a circuit diagram of a data serializer DS2 according to an embodiment. The data buffer TB2 includes a PMOS transistor PM21, a PMOS transistor PM22, an NMOS transistor NM21, an NMOS transistor NM22, an inverter IV21, a buffer gate PG, an inverter IV22, and a PMOS transistor PM23, a PMOS transistor PM24, an NMOS transistor NM23, an NMOS transistor NM24, an inverter IV23, an inverter IV24, and an inverter IV25. The PMOS transistor PM21, the PMOS transistor PM22, the NMOS transistor NM21 and the NMOS transistor NM22 are connected in series. The drain (or source) of the PMOS transistor PM21 is applied with a first voltage V1. The first voltage V1 is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM22 is applied with the second voltage V2. The inverter IV21 is connected to the input port I. Buffer gate PG is connected to inverter IV21. The buffer gate PG is used to offset the delay of the inverter IV23. The main function of the buffer gate PG is to make the input data DA enter the gate of the PMOS transistor PM22/NMOS transistor NM21 at the same time as the gate of the PMOS transistor PM24/NMOS transistor NM23. The gate of the PMOS transistor PM22 and the gate of the NMOS transistor NM21 are connected to the buffer gate PG. The inverter IV22 is connected to the enable port EN and the gate of the PMOS transistor PM21. The source (or drain) of the PMOS transistor PM22 and the drain of the NMOS transistor NM21 are connected to the output port O.

The PMOS transistor PM23 , the PMOS transistor PM24 , the NMOS transistor NM23 and the NMOS transistor NM24 are connected in series. The drain (or source) of the PMOS transistor PM23 is applied with the first voltage V1. The first voltage V1 is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM24 is applied with the second voltage V2. The inverter IV25 is connected to the input port I. The inverter IV23 is connected to the inverter IV25. The gate of the PMOS transistor PM24 and the gate of the NMOS transistor NM23 are connected to the inverter IV23. The inverter IV24 is connected to the enable port EN and the gate of the PMOS transistor PM23. The source (or drain) of the PMOS transistor PM24 and the drain of the NMOS transistor NM23 are connected to the output port OB.

When the control signal C input to the enable port EN is "0", the PMOS transistor PM21 and the NMOS transistor NM22 will be turned off, so no current Ip1 or current In1 will be formed.

When the control signal C input to the enable port EN is "0", the PMOS transistor PM23 and the NMOS transistor NM24 will be turned off, so no current Ip2 or current In2 will be formed.

When the control signal C input to the enable port EN is "1" and the input data DA input to the input port I is "1", the PMOS transistor PM21 and the PMOS transistor PM22 will be turned on and the NMOS transistor NM21 will be turned on. Turn off, so the current Ip1 will be formed, and the output signal Dout output from the output port O will rise to "1", which has the same value as the input data DA.

When the control signal C input to the enable port EN is "1" and the input data DA input to the input port I is "1", the NMOS transistor NM23 and the NMOS transistor The crystal NM24 will be turned on, and the PMOS transistor PM24 will be turned off, so a current In2 will be formed, and the complementary output signal Doub output from the output port OB will drop to "0", which is opposite to the input data DA.

When the control signal C input to the enable port EN is "1" and the input data DA input to the input port I is "0", the NMOS transistor NM21 and the NMOS transistor NM22 will be turned on and the PMOS transistor PM22 will be turned on. Turn off, so the current In1 will be formed, and the output signal Dout output from the output port O will drop to "0", and its value is the same as the input data DA.

When the control signal C input to the enable port EN is "1" and the input data DA input to the input port I is "0", the PMOS transistor PM23 and the PMOS transistor PM24 will be turned on, and the NMOS transistor NM23 will be turned on. is turned off, so a current Ip2 will be formed, and the complementary output signal Doutb output from the output port OB will rise to "1", whose value is opposite to that of the input data DA.

The de-skew buffer DB2 includes a PMOS transistor PM25 , an NMOS transistor NM25 , a PMOS transistor PM26 and an NMOS transistor NM26 . The PMOS transistor PM25 and the NMOS transistor NM25 are connected in series. The drain (or source) of the PMOS transistor PM25 is applied with the first voltage V1. The first voltage V1 is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM25 is applied with the second voltage V2. The gate of the PMOS transistor PM25 and the gate of the NMOS transistor NM25 are connected to the output port OB. The source (or drain) of the PMOS transistor PM25 and the drain of the NMOS transistor NM25 are connected to the output port O.

The PMOS transistor PM26 and the NMOS transistor NM26 are connected in series. The drain (or source) of the PMOS transistor PM26 is applied with the first voltage V1. The first voltage V1 is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM26 is applied with the second voltage V2. The source (or drain) of the PMOS transistor PM26 and the drain of the NMOS transistor NM26 are connected to the output port OB. The gate of the PMOS transistor PM26 and the gate of the NMOS transistor NM26 are connected to the output port O.

Please refer to FIG. 8A, which shows the data sequence when the PMOS transistors PM21, PM22, PM23, PM24, PM25, and PM26 operate slower than the NMOS transistors NM21, NM22, NM23, NM24, NM25, and NM26. Voltage curves of control signal C, input data DA, output signal Dout and complementary output signal Doutb of converter DS2.

Please refer to the dotted lines L211 and L215 in FIG. 8A, the rise of the output signal Dout is slower than the fall of the output signal Dout. The output signal Dout rises slowly, while the complementary output signal Doutb falls rapidly. At the time point T21, the complementary output signal Doutb reaches “0” first, so the PMOS transistor PM25 of the de-skew buffer DB2 is turned on by the complementary output signal Doutb. Moreover, at the time point T21, the output signal Dout is still "0", so the PMOS transistor PM26 of the de-skew buffer DB2 is turned on by the output signal Dout. After the PMOS transistor PM25 is turned on, a current Ip3 is formed to pull up the output signal Dout; after the PMOS transistor PM26 is turned on, a current Ip4 is formed to suppress the complementary output signal Doutb (pull up the complementary output signal Doutb). Therefore, please refer to the solid lines L213, L214, The formation of the output signal Dout is accelerated and the formation of the complementary output signal is slowed down.

Please refer to the dotted lines L215 and L216 in FIG. 8A, the output signal D out falls rapidly, while the complementary output signal Doutb rises slowly. At the time point T22, the complementary output signal Doutb is still at "0", so the PMOS transistor PM25 of the de-skew buffer DB2 is turned on by the complementary output signal Doutb. Moreover, at the time point T22, the output signal Dout reaches "0" first, so the PMOS transistor PM26 of the de-skew buffer DB2 is turned on by the output signal Dout. After the PMOS transistor PM25 is turned on, a current Ip3 is formed to pull up the output signal Dout; after the PMOS transistor PM26 is turned on, a current Ip4 is formed to suppress the complementary output signal Doutb (pull up the complementary output signal Doutb). Therefore, please refer to the solid lines L217, L218, the formation of the output signal Dout will be slowed down, and the formation of the complementary output signal Doutb will be accelerated.

In this way, the rising time tR1 and falling time tF1 of the output signal Dout are substantially equal to the rising time tR2 and falling time tF2 of the complementary output signal Doutb. Since the difference between the rising time tR1 and the falling time tF1 is greatly reduced, the effective data window tDV1 can be greatly enlarged.

Please refer to Figure 8B, which shows the data sequence when the PMOS transistors PM21, PM22, PM23, PM24, PM25, and PM26 operate faster than the NMOS transistors NM21, NM22, NM23, NM24, NM25, and NM26. Voltage curves of control signal C, input data DA, output signal Dout and complementary output signal Doutb of converter DS2.

Please refer to the dotted lines L221 and L225 in FIG. 8B, the rise of the output signal Dout is faster than the fall of the output signal Dout. The output signal Dout rises rapidly, while the complementary output signal Doutb falls slowly. At the time point T23, the complementary output signal Doutb is still at "1", so the NMOS transistor NM25 of the de-skew buffer DB2 is turned on by the complementary output signal Doutb. Furthermore, at the time point T23, the output signal Dout reaches “1” first, so the NMOS transistor NM26 of the de-skew buffer DB2 is turned on by the output signal Dout. After the NMOS transistor NM25 is turned on, a current In3 is formed to pull down the output signal Dout; after the NMOS transistor NM26 is turned on, a current In4 is formed to suppress the complementary output signal Doutb (pull down the complementary output signal Doutb). Therefore, please refer to the solid lines L223, L224, the formation of the output signal Dout will be slowed down, and the formation of the complementary output signal Doutb will be accelerated.

Please refer to the dotted lines L225 and L226 in FIG. 8B, the output signal Dout falls slowly, and the complementary output signal Doutb rises rapidly. At the time point T24, the complementary output signal Doutb reaches “1” first, so the NMOS transistor NM25 of the de-skew buffer DB2 is turned on by the complementary output signal Doutb. Furthermore, at the time point T24, the output signal Dout is still "1", so the NMOS transistor NM26 of the de-skew buffer DB25 is turned on by the output signal Dout. After the NMOS transistor NM25 is turned on, a current In3 is formed to pull down the output signal Dout; after the NMOS transistor NM26 is turned on, a current In4 is formed to suppress the complementary output signal Doutb (to pull down the complementary output signal Doutb). Therefore, please refer to the solid line L227, L228, the formation of the output signal Dout is accelerated, and the formation of the complementary output signal Doutb is slowed down.

In this way, the rising time tR3 and falling time tF3 of the output signal Dout are substantially the same as the rising time tR4 and falling time tF4 of the complementary output signal Doutb. Since the difference between the rising time tR3 and the falling time tF3 is greatly reduced, the valid data window tDV3 can be greatly enlarged.

Please refer to FIG. 9 , which shows a schematic diagram of a data serializer DS3 according to an embodiment. In this embodiment, the data serializer DS3 includes a data buffer TB3 and a de-skew buffer DB2. The structure of the data buffer TB3 is similar to that of the data buffer TB2, and the similarities will not be repeated. Compared with the data buffer TB2, the data buffer TB3 further includes an input port IB. The input data DA is input to the input port I, and the complementary input data DAB is input to the input port IB. The complementary input data DAB is the inverse of the input data DA.

Please refer to FIG. 10 , which shows a circuit diagram of a data serializer DS3 according to an embodiment. In this embodiment, the complementary output signal Doutb can be provided without the inverter IV25 of FIG. 7 .

The above-mentioned data serializers DS2 and DS3 are widely used in electronic devices and latch data devices. For example, please refer to FIG. 11 , which shows a schematic diagram of a latch data device 100 according to an embodiment. The latch data device 100 includes a latch circuit 110 and an output transmitter 120 . The output transmitter 120 is connected to the latch circuit 110 . The data stored in the latch circuit 110 is output through the The transmitter 120 transmits. The output sender 120 includes a data serializer DS2 or a data serializer DS3.

In other embodiments, the data serializer may include two, four or more data buffers. These examples are illustrated below.

Please refer to FIG. 12 , which shows a schematic diagram of a data serializer DS4 according to another embodiment. In Figure 12, the data serializer DS4 includes two data buffers TB3, TB4 and one de-skew buffer DB2. The structure of each data buffer TB3, TB4 is similar to that of the data buffer TB2. Similarities will not be repeated. The data buffer TB3 receives the input data DA and the control signal C. The data buffer TB4 receives an input data DB and a complementary control signal C#. The complementary control signal C# is opposite to the control signal C.

When the control signal C is at a predetermined level (that is, "1"), the data buffer TB3 forms an output signal Dout and a complementary output signal Doutb (the value of which is opposite to the output signal Dout). When the complementary control signal C is at a predetermined level (that is, "1"), the data buffer TB4 forms an output signal Dout and a complementary output signal Doutb (the value of which is opposite to the output signal Dout). The de-skew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

Please refer to FIG. 13, which illustrates the output signal Dout of FIG. 12. The contents of the input data DA are "DA0", "DA1", "DA2", and so on. The contents of the input data DB are "DB0", "DB1", and so on. First, when the control signal C is “1” and the complementary control signal C# is “0”, the content of the output signal Dout is “DA0”. Then, when the control signal C is "0" and the complementary control signal C# is "1" When , the content of the output signal Dout is "DB0". Then, when the control signal C is "1" and the complementary control signal C# is "0", the content of the output signal Dout is "DA1". In the case that the PMOS transistor operates slower than the NMOS transistor, if the de-skew buffer DB2 is not used to speed up or slow down the formation of the output signal Dout, the fall time tF of the output signal Dout will be much shorter than the output signal The rising time tR of Dout.

In this example, the de-skew buffer DB2 receives the complementary output signal Doutb to speed up the rising of the output signal Dout and slow down the falling of the output signal Dout. Therefore, the rising time tR is shortened to the rising time tR1, and the falling time tF is lengthened to the falling time tF1. In this way, the effective data window tDV1 can be greatly enlarged.

Please refer to FIG. 14 , which shows a schematic diagram of a data serializer DS5 according to another embodiment. In Figure 14, the data serializer DS5 includes two data buffers TB5, TB6 and one de-skew buffer DB2. The structure of each data buffer TB5, TB6 is similar to that of the data buffer TB3. Similarities will not be repeated. The data buffer TB5 receives the input data DA, the complementary input data DAB and the control signal C. The data buffer TB6 receives the input data DB, the complementary input data DBB and the complementary control signal C#. The complementary control signal C# is opposite to the control signal C.

When the control signal C is at a predetermined level (that is, "1"), the data buffer TB5 forms an output signal Dout and a complementary output signal Doutb (the value of which is opposite to the output signal Dout). When the complementary control signal C# is at a predetermined level (ie "1"), the data buffer TB6 forms the output signal Dout and the complementary output signal Doutb. The de-skew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

Please refer to FIG. 15 , which shows a schematic diagram of a data serializer DS6 according to another embodiment. In Fig. 15, the data serializer DS6 includes four data buffers TB7, TB8, TB9, TB10 and one de-skew buffer DB2. The structure of each data buffer TB7, TB8, TB9, TB10 is similar to that of the data buffer TB2. Similarities will not be repeated. The data buffer TB7 receives the input data DA and the control signal CA. The data buffer TB8 receives the input data DB and the control signal CB. The data buffer TB9 receives the input data DC and the control signal CC. The data buffer TB10 receives the input data DD and the control signal CD. The control signals CA, CB, CC, and CD are "1" alternately within one cycle.

When the control signal CA is "1", the output signal Dout and the complementary output signal Doutb are formed by the data buffer TB7. When the control signal CB is "1", the output signal Dout and the complementary output signal Doutb are formed by the data buffer TB8. When the control signal CC is "1", the output signal Dout and the complementary output signal Doutb are formed by the data buffer TB9. When the control signal CD is “1”, the data buffer TB10 forms the output signal Dout and the complementary output signal Doutb. The de-skew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

Please refer to FIG. 16, which illustrates the output signal Dout of FIG. 15. The contents of the input data DA are "DA0", "DA1", "DA2", and so on. The contents of the input data DB are "DB0", "DB1", "DB2", and so on. The contents of the input data DC are "DC0", "DC1", and so on. The contents of the input data DD are "DD0", "DD1", and so on. First, when the control signal CA is "1" And when the control signals CB, CC, CD are "0", the content of the output signal Dout is "DA0". Then, when the control signal CB is “1” and the control signals CA, CC, CD are “0”, the content of the output signal Dout is “DB0”. Then, when the control signal CC is “1” and the control signals CA, CB, CD are “0”, the content of the output signal Dout is “DC0”. Then, when the control signal CD is “1” and the control signals CA, CB, CC are “0”, the content of the output signal Dout is “DD0”. In the case that the PMOS transistor operates faster than the NMOS transistor, if the de-skew buffer DB2 is not used to speed up or slow down the formation of the output signal Dout, the fall time Tf of the output signal Dout is much shorter than the output signal Dout The rise time tR.

In this embodiment, the deskew buffer DB2 receives the complementary output signal Doutb to speed up the output signal Dout and slow down the output signal Dout. Therefore, the rising time tR is shortened to the rising time tR1, and the falling time tF is lengthened to the falling time tF1. Therefore, the valid data window tDV1 can be greatly lengthened.

Please refer to FIG. 17 , which shows a schematic diagram of a data serializer DS7 according to another embodiment. In Fig. 17, the data serializer DS7 includes four data buffers TB11, TB12, TB13, TB14 and one de-skew buffer DB2. The structure of each data buffer TB11, TB12, TB13, TB14 is similar to that of the data buffer TB3. The similarities no longer weigh heavily on the narrative. The data buffer TB11 receives the input data DA, the complementary input data DAB and the control signal CA. The data buffer TB12 receives the input data DB, the complementary input data DBB and the control signal CB. Data buffer TB13 receives input data DC, complementary input data DCB, and control signals CC. The data buffer TB14 receives the input data DD, the complementary input data DDB and the control signal CD.

When the control signal CA is “1”, the data buffer TB11 forms the output signal Dout and the complementary output signal Doutb. When the control signal CB is “1”, the data buffer TB12 forms the output signal Dout and the complementary output signal Doutb. When the control signal CC is “1”, the data buffer TB13 forms the output signal Dout and the complementary output signal Doutb. When the control signal CD is “1”, the data buffer TB14 forms the output signal Dout and the complementary output signal Doutb. The de-skew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

As mentioned above, the present disclosure utilizes the de-skew buffer DB2 to receive the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout. Therefore, the rising time tR1 and falling time tF1 of the output signal Dout are substantially equal to the rising time tR2 and falling time tF2 of the complementary output signal Doutb. Since the difference between the rising time tR1 and the falling time tF1 is greatly reduced, the valid data window tDV1 can be greatly enlarged.

To sum up, although the present disclosure has been disclosed above with embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs may make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be defined by the scope of the appended patent application.

C: Control signal

DA: input data

Dout: output signal

Doutb: Complementary output signal

DB2: Deskew Buffer

DS2: Data Serializer

EN: enable port

I: input port

Ip1,Ip2,Ip3,Ip4,In1,In2,In3,In4: Current

IV21, IV22, IV23, IV24, IV25: Inverters

NM21, NM22, NM23, NM24, NM25, NM26: NMOS transistors

O, OB: output port

PG: buffer gate

PM21, PM22, PM23, PM24, PM25, PM26: PMOS transistor

TB2: data buffer

V1: first voltage

V2: second voltage

Claims (10)

A data serializer (data serializer), including: at least one data buffer (data buffer), at least receiving an input data and a control signal, wherein when the control signal is at a predetermined level, the data buffer forms a output signal and a complementary output signal opposite to the output signal; and a de-skew buffer (de-skew buffer) for receiving the complementary output signal to speed up or slow down the formation of the output signal ; Wherein, each of the at least one data buffer at least includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, the first PMOS transistor, the The second PMOS transistor, the first NMOS transistor and the second NMOS transistor system are connected in series; wherein, when the control signal is at the predetermined level and the input data is a first value, the first NMOS transistor is connected in series; A PMOS transistor and the second PMOS transistor system are turned on, so that the output signal rises to a first level; wherein, when the control signal is at the predetermined level and the input data is a second value, the The first NMOS transistor and the second NMOS transistor system are turned on, causing the output signal to drop to a second level; wherein, the first PMOS transistor and the second PMOS transistor operate better than the first PMOS transistor. In the case where the NMOS transistor and the second NMOS transistor are slower, the deskew buffer is used to pull up the output signal and the complementary output signal, so that the formation of the output signal is accelerated, and the complementary output The formation of the signal is slowed down; Wherein, when the first PMOS transistor and the second PMOS transistor operate faster than the first NMOS transistor and the second NMOS transistor, the de-skew buffer is used to pull down The output signal and the complementary output signal cause the formation of the output signal to be slowed down and the formation of the complementary output signal to be accelerated. The data serializer as described in claim item 1, wherein the de-skew buffer includes a third PMOS transistor, the third PMOS transistor of the de-skew buffer is connected to the data buffer, when the output When the rise of the signal is slower than the fall of the output signal, the third PMOS transistor of the deflection buffer is turned on to pull up the output signal. The data serializer according to claim 2, wherein the third PMOS transistor of the de-skew buffer is turned on by the complementary output signal. The data serializer as described in claim 1, wherein the second PMOS transistor of the data buffer is connected to the de-skew buffer, and when the second PMOS transistor of the data buffer is turned on, the output signal rise. The data serializer as described in claim 1, wherein the first NMOS transistor of the data buffer is connected to the de-skew buffer, and when the first NMOS transistor of the data buffer is turned on, the output signal decline. The data serializer according to claim 1, wherein the data buffer further receives a complementary input data, the output signal is formed according to the input data, and the complementary output signal is formed according to the complementary input data. A latch data device (latch data device), including: a latch circuit (latch circuit); and an output transmitter (output transmitter), connected to the latch circuit, wherein the output transmitter includes: a data serialization A data serializer, including: at least one data buffer (data buffer), receiving at least one input data and a control signal, wherein when the control signal is at a predetermined level, the data buffer forms an output signal and a a complementary output signal, the complementary output signal being opposite to the output signal; and a de-skew buffer (de-skew buffer) for receiving the complementary output signal to speed up or slow down the formation of the output signal; wherein, the Each of the at least one data buffer at least includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, the first PMOS transistor, the second PMOS transistor The crystal, the first NMOS transistor and the second NMOS transistor system are connected in series; wherein, when the control signal is at the predetermined level and the input data is a first value, the first PMOS transistor and the second PMOS transistor system is turned on, so that the output signal rises to a first level; Wherein, when the control signal is at the predetermined level and the input data is a second value, the first NMOS transistor and the second NMOS transistor system are turned on, so that the output signal drops to a second level ; wherein, in the case where the first PMOS transistor and the second PMOS transistor operate slower than the first NMOS transistor and the second NMOS transistor, the de-skew buffer is used to pull Raising the output signal and the complementary output signal, so that the formation of the output signal is accelerated, and the formation of the complementary output signal is slowed down; wherein, the first PMOS transistor and the second PMOS transistor operate more than the In the case where the first NMOS transistor and the second NMOS transistor are faster, the deskew buffer is used to pull down the output signal and the complementary output signal so that the formation of the output signal is slowed down, and Formation of the complementary output signal is accelerated. The latch data device as claimed in item 7, wherein the de-skew buffer includes a third PMOS transistor, the third PMOS transistor of the de-skew buffer is connected to the data buffer, when the output When the rise of the signal is slower than the fall of the output signal, the third PMOS transistor of the deflection buffer is turned on to pull up the output signal. The latch data device as claimed in claim 7, wherein the data buffer further receives a complementary input data, the output signal is formed according to the input data, and the complementary output signal is formed according to the complementary input data. A control method of a data serializer (data serializer), wherein the data serializer includes at least one data buffer (data buffer) and a de-skew buffer (de-skew buffer), the control method includes: the data the buffer receives an input data and a control signal; when the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal, the complementary output signal is opposite to the output signal; and the deskew The buffer receives the complementary output signal to speed up or slow down the formation of the output signal; wherein each of the at least one data buffer at least includes a first PMOS transistor, a second PMOS transistor, a first NMOS Transistor, a second NMOS transistor, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series; wherein, when the control signal When the predetermined level and the input data are a first value, the first PMOS transistor and the second PMOS transistor system are turned on, so that the output signal rises to a first level; wherein, when the control When the signal is at the predetermined level and the input data is a second value, the first NMOS transistor and the second NMOS transistor system are turned on, so that the output signal drops to a second level; wherein, in the In case the first PMOS transistor and the second PMOS transistor operate slower than the first NMOS transistor and the second NMOS transistor, the deskew buffer pulls up the output signal and the complementary output signal, so that the formation of the output signal is accelerated, and the formation of the complementary output signal is slowed down; wherein, the first PMOS transistor and the second PMOS transistor operate better than the first NMOS transistor and the In the case where the second NMOS transistor is even faster, The deskew buffer pulls down the output signal and the complementary output signal so that the formation of the output signal is slowed down and the formation of the complementary output signal is accelerated.

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