TWI799067B - Semiconductor memory device and error detection and correction method - Google Patents

Abstract

A compatibility of error detection and correction capability and write or read performance is realized. A error detection and correction method of a flash memory of the present invention includes: a setting step of setting selection information for selecting a first error detection and correction function that performs 1-bit error detection and correction or a second error detection and correction function that performs multiple-bit error detection and correction; and an execution step of performing the first error detection and correction function or the second error detection and correction function based on the set selection information during a read operation or a write operation.

Description

Semiconductor storage device and error detection and correction method

The present invention relates to a semiconductor storage device of NAND type flash memory, and in particular relates to a switching of error detection and correction functions.

In NAND flash memory, bit errors are caused by repeated programming or erasing of data. As a countermeasure against such bit errors, an error detection and correction circuit (hereinafter referred to as an ECC (Error Correcting Code) circuit) is mounted on the flash memory (for example, patent documents: Japanese Patent No. 6744950, Japanese Patent No. 6744951).

FIG. 1 shows a schematic structure of a conventional NAND flash memory equipped with an on-chip ECC function. The flash memory 10 includes: a storage cell array 20 , a page buffer/sensing circuit 30 , an ECC circuit 40 , and an input/output circuit 50 . The ECC circuit 40 includes: a transmission circuit 42 , an ECC core 44 , an error register 46 and a writing circuit 48 .

In the read operation, the data read from the selected page of the storage cell array 20 is held in the page buffer/sensing circuit 30, and the data held in the page buffer/sensing circuit 30 is transmitted through the transmission circuit 42. to ECC core 44. The ECC core 44 performs an ECC operation on the transmitted data, and stores the error information obtained by the operation in the error register 46 . The write circuit 48 writes the corrected data back to the page buffer/sense circuit 30 based on the error information held in the error register 46 . In this way, after the ECC processing of one page is completed, the data stored in the page buffer/sensing circuit 30 is read out to the data bus 60 according to the row address, and the read data is provided to the I/O circuit 50 . The input/output circuit 50 outputs the read data to the outside from an input/output terminal not shown.

In the write operation, the data to be programmed input from the outside is held in the page buffer/sensing circuit 30, and the ECC core 44 generates a code (parity check bit) of the data transferred from the page buffer/sensing circuit 30 , the writing circuit 48 writes the generated code to a location corresponding to the spare area of the page buffer/sensing circuit 30 . After the ECC process, the data held in the page buffer/sensing circuit 30 is programmed into the memory cell array 20 .

When the data size of one page becomes larger, when multiple pages are continuously read in synchronization with the read or write timing of the page, or with an external clock signal based on the Serial Peripheral Interface (SPI) The frequency of action has a great influence. In addition, the speed-up has been achieved through pipeline processing, but this also leads to an increase in the wafer size, making it difficult to achieve both error detection and correction capability and readout performance.

The present invention focuses on such conventional problems, and an object of the present invention is to provide a semiconductor storage device and an error detection and correction method that realize coexistence of error detection and correction capability and writing or reading performance.

The error detection and correction method of a semiconductor storage device according to the present invention includes: a setting step of setting a first error detection and correction function for selectively performing m-bit error detection and correction or a second error detection and correction function for performing n-bit error detection and correction Function selection information (m and n are natural numbers, m<n); and an execution step of executing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation Two error detection and correction functions.

The semiconductor storage device of the present invention includes: a memory cell array; an error detection and correction circuit including a first error detection and correction function for performing m-bit error detection and correction and a second error detection and correction function for performing n-bit error detection and correction ( m and n are natural numbers, m<n); set the temporary register, set the selection information for selecting the first error detection and correction function or the second error detection and correction function; and the controller, in the readout action Or during a writing operation, the first error detection and correction function or the second error detection and correction function is executed based on the selection information.

According to the present invention, since the first error detection and correction function or the second error detection and correction function can be selected, for example, by switching the error detection and correction capability according to the product life cycle, it is possible to achieve coexistence with the performance of the read or write operation.

Next, embodiments of the present invention will be described in detail with reference to the drawings. The semiconductor storage device of the present invention is, for example, a NAND flash memory, or a microprocessor (micro processor), microcontroller (micro controller), logic, application specific integrated circuit (Application Specific Integrated Circuit) embedded in such a flash memory. Circuit, ASIC), a processor that processes images or sounds, and a processor that processes wireless signals.

FIG. 2 is a diagram showing an internal structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a storage cell array 110, in which a plurality of storage cells are arranged in a matrix; an input-output circuit 120, connected to an external input and output terminal, and outputs read data to the outside or imports data input from the outside ECC circuit 130, the generation of the error correction code of the data that should be programmed or the error detection and correction of the data read based on the error correction code; the address temporary register 140 receives the address data through the input and output circuit 120 ; The controller 150 controls each part based on a command (command) received via the input and output circuit 120 or a control signal applied to the control terminal; the word line selection circuit 160 is based on the column address from the address register 140 The decoding result of the information Ax is used to select a block or a word line; the page buffer/sensing circuit 170 maintains the data read from the selected page of the storage cell array 110, or maintains the data to be programmed into the selected page; The row selection circuit 180 selects a row based on the decoding result of the row address information Ay from the address register 140; and the setting register 190 sets selection information about a plurality of error detection and correction functions. Although not shown here, the flash memory 100 includes an internal voltage generating circuit that generates voltages required for reading, programming (writing) and erasing data (programming voltage Vpgm, pass voltage Vpass , read voltage Vread, erase voltage Vers). In addition, the NAND-type flash memory 100 may be equipped with an SPI for realizing operation compatibility with a NOR-type flash memory.

The memory cell array 110 has, for example, m memory blocks BLK( 0 ), BLK( 1 ), . . . , BLK(m−1) arranged in the row direction. A plurality of NAND strings are formed in one storage block, and one NAND string includes a plurality of storage cells connected in series, selection transistors on the bit line side, and selection transistors on the source line side. The drain of the selection transistor on the bit line side is connected to a corresponding global bit line, and the source of the selection transistor on the source line side is connected to a common source line. The gates of the memory cells are connected to the corresponding word lines, and the gates of the selection transistors on the bit line side and the selection transistors on the source line are respectively connected to the selection gate line SGD and the selection gate line SGS. The word line selection circuit 160 drives the bit line side selection transistor and the source line side selection transistor through the selection gate line SGD and the selection gate line SGS based on the column address information Ax to select a block or a word line. NAND strings can be formed on the substrate surface both two-dimensionally and three-dimensionally. In addition, the storage unit can be either a single level cell (Single Level Cell, SLC) type that stores 1 bit (binary data), or a type that stores multiple bits.

In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (such as 0 V) is applied to the selected word line, a pass voltage Vpass (such as 4.5 V) is applied to the non-selected word line, and a certain voltage Vpass (such as 4.5 V) is applied to the selected gate line. SGD and select gate line SGS apply a positive voltage (for example, 4.5 V), so that the select transistor on the bit line side and the select transistor on the source line side are turned on, so that the common source line SL is 0 V. In the programming action, a high-voltage programming voltage Vpgm (for example, 15 V to 20 V) is applied to the selected word line, and an intermediate potential (for example, 10 V) is applied to the non-selected word line to make the selection transistor on the bit line side When it is turned on, the select transistor on the source line side is turned off, and a potential corresponding to data "0" or "1" is supplied to the bit line. In the erase operation, 0 V is applied to the selected word line in the block, and a high voltage (for example, 20 V) is applied to the P well.

In a certain form, the ECC circuit 130 includes a first ECC unit 132 having a 1-bit error detection and correction function, and a second ECC unit 134 having an 8-bit error detection and correction function, as shown in FIG. 3 . The first ECC unit 132 encodes/decodes data using Hamming codes, and the second ECC unit 134 encodes/decodes data using BCH codes. The first enable signal EN_1 and the second enable signal EN_2 are respectively supplied from the controller 150 to the first ECC unit 132 and the second ECC unit 134 . The first ECC unit 132 is enabled when the first enable signal EN_1 is in the first logic state, and disabled when the first enable signal EN_1 is in the second logic state. The second ECC unit 134 is enabled when the second enable signal EN_2 is in the first logic state, and disabled when the second enable signal EN_2 is in the second logic state. The first ECC unit 132 and the second ECC unit 134 perform ECC processing in synchronization with the supplied internal clock signal CLK_ECC.

表1 The setting register 190 sets and holds selection information for selecting the operation of the first ECC unit 132 or the second ECC unit 134 . Table 1 shows an example of the setting register of the present invention. The selection information includes, for example, a 1-bit flag as shown in Table 1. The flag “0” specifies the selection of the first ECC unit 132 , and the flag “1” specifies the selection of the second ECC unit 134 . In one aspect, the selection information is loaded from a fuse read only memory (ROM) (fuse memory cell) during a power on sequence of the flash memory 100 . In a default state or when shipped from the factory, a flag “0” is stored in the fuse ROM as selection information. In the initial or first half of the life cycle, the memory cell deteriorates relatively less over the years, so prediction errors occur less frequently. Therefore, the first ECC unit 132 is selected as an initial setting. Therefore, in the first half of the life cycle, the ECC processing time is short, so that the read or write time is suppressed from becoming longer due to the ECC processing.

Table 1

The setting register 190 can be accessed from the outside, and the user can rewrite the selection information set in the setting register 190 by using a predetermined command. After receiving a write command and write data of the setting register from the host computer via the I/O circuit 120 , the controller 150 writes the write data into the setting register 190 . Thereby, selection information is rewritten. When the life cycle reaches the second half and the memory cells deteriorate over time, the frequency of prediction errors will increase accordingly. In order to cope with this, by selecting the second ECC unit 134, switching is performed from the single-bit error detection and correction function to the multi-bit error detection and correction function. Thus, in the second half of the life cycle, the time for reading or writing becomes longer due to ECC processing, but on the contrary, the error detection and correction capability increases and the decrease in reliability is suppressed.

The controller 150 includes a microcontroller or a state machine, and controls overall operations of the flash memory 100 such as reading, programming, erasing, and switching of error detection and correction functions based on commands or control signals received from the outside.

Next, the operation of the ECC circuit 130 will be described. During the programming operation, the data input from the I/O circuit 120 is held in the page buffer/sensing circuit 170 , and then the held data is transferred to the ECC circuit 130 . The ECC circuit 130 performs an ECC operation on the transmitted data, generates error correction codes (eg, parity check bits), and writes the generated error correction codes back to the spare area of the page buffer/sensing circuit 170 . Thereafter, the input data and error correction codes are programmed into the selected pages of the memory cell array 110 .

During the read operation, the data read from the selected page of the storage cell array 110 is transmitted to the page buffer/sensing circuit 170 and stored therein. Next, the stored data is transmitted to the ECC circuit 130, and the ECC circuit 130 detects whether there is an error based on the error correction code, and corrects the data error if an error is detected. Error correction is performed, for example, by rewriting the data held in the page buffer/sensing circuit 170 . Afterwards, the data held in the page buffer/sensing circuit 170 is output to the outside through the I/O circuit 120 .

An example of the data structure of the page buffer/sensing circuit 170 is shown in FIG. 4 . The page buffer/sensing circuit 170 includes, for example: a normal area 200 divided into 8 magnetic sectors 0 to 7; and a spare area 210 divided into spare 0, spare 1, spare 2, and spare 3 These 4 magnetic areas. The regular area is used for data storage. One magnetic sector of the regular area 200 contains 256 bytes, for example, and the 8 magnetic sectors of the regular area 200 hold about 2K bytes of data as a whole.

One sector of the spare area 210 includes, for example, 16 bytes, and the four sectors (spare 0 to spare 3) hold data of 64 bytes as a whole. The error correction codes of the magnetic zone 0 and the magnetic zone 1 of the conventional area 200 are stored in the spare 0, the error correction codes of the magnetic zone 2 and the magnetic zone 3 of the regular zone 200 are stored in the spare 1, and the error correction codes of the magnetic zone 2 and the magnetic zone 3 of the normal zone 200 are stored in the spare 2, and The error correction codes of the magnetic sector 4 and the magnetic sector 5 of the normal area 200 are stored in the spare 3, and the error correction codes of the magnetic sector 6 and the magnetic sector 7 of the normal area 200 are stored.

The ECC circuit 130 includes: a transmission circuit 136, which receives data transmitted in units of magnetic sectors, and transmits it to the ECC processing unit 135; the ECC processing unit 135 includes a first ECC unit 132 with a 1-bit error detection and correction function and a second ECC circuit 134 with an 8-bit error detection and correction function; and a writing circuit 138 for writing error correction codes into the spare area 210 or writing corrected data into the regular area 200 .

The controller 150 outputs the enable signal EN_1 and the enable signal EN_2 to the ECC circuit 130 based on the selection information (flag) set in the setting register 190, and enables the first ECC unit 132 or the second ECC unit 134 to select run aggressively. The first ECC unit 132 performs single-bit error detection and correction using Hamming codes, and the second ECC unit 134 uses BCH codes to perform 8-bit error detection and correction. The time required for the first ECC section 132 is shorter than the time required for the second ECC section 134. Therefore, when the first ECC section 132 is selected, compared with the time when the second ECC section 134 is selected, the read or write time can be shortened. In contrast to the time required for writing, when the second ECC unit 134 is selected, more error bit detection and correction can be performed than when the first ECC unit 132 is selected.

FIG. 5 is a flowchart illustrating the switching operation of the error detection and correction capability of the ECC circuit according to the first embodiment of the present invention. The initial value of the selection information of the first ECC unit 132 or the second ECC unit 134 of the ECC circuit 130 is stored in a fuse ROM different from the user-used area of the memory cell array 110 (for example, an area inaccessible to the user). The initial value of the selection information sets the selection of the first ECC unit 132 as information at the time of product shipment. When a power-up sequence is executed, the selection information stored in the fuse ROM is loaded into the setting register 190 ( S100 ).

The controller 150 refers to the selection information of the setting register 190 , enables the first ECC unit 132 through the enable signal EN_1 , and disables the second ECC unit 134 through the enable signal EN_2 . Thus, during the read or write operation, the selected first ECC unit 132 operates, and the second ECC unit 134 does not operate ( S110 ).

Afterwards, the user rewrites the selection information in the setting register 190 according to the usage status of the flash memory, so as to select the second ECC unit 134 ( S120 ). After rewriting the selection information, the controller 150 disables the first ECC unit 132 through the enable signal EN_1 , and enables the second ECC unit 134 through the enable signal EN_2 . Accordingly, during the read or write operation, the selected second ECC unit 134 operates, and the first ECC unit 132 does not operate ( S130 ).

Thus, according to this embodiment, since the first ECC unit 132 or the second ECC unit 134 is operated according to the selection information of the setting register, the error detection and correction capability can be selectively switched according to the product life cycle, and optimal The processing time for error detection and correction is properly managed to suppress a decrease in the page reading time or the operation frequency of continuous reading. That is, during the period when the aging degradation of the memory cell is small, the time required for the ECC process can be shortened to achieve high-speed reading or writing. On the other hand, during the period when the aging degradation of the memory cell increases Within, the error correction capability can be enhanced to achieve improved reliability.

Furthermore, the initial value is loaded into the setting register 190 from the fuse ROM, but this is an example, and the present embodiment is not necessarily limited to this form. For example, the setting register 190 can utilize a part of the memory space of the area that the user of the storage cell array 110 can use, and the default value (erase state) of the memory space can also represent the first ECC part 132. choose. In this case, the controller 150 reads the preset value of the memory space, enables the first ECC unit 132 , and disables the second ECC unit 134 . When the second ECC unit 134 is selected, the user programs the default value of the memory space and rewrites the selection information.

Next, a second embodiment of the present invention will be described. In the first embodiment, when the operation is switched from the first ECC unit 132 to the second ECC unit 134 , the data encoded by the first ECC unit 132 cannot be decoded by the second ECC unit 134 . That is, the error correction code generated by the first ECC unit 132 stored in the memory cell array 110 cannot be deciphered by the second ECC unit 134, so when switching to the second ECC unit 134, the code generated by the first ECC unit 132 must be The error correction code of is converted into an error correction code generated by the second ECC section 134 .

Therefore, the second embodiment uses the copy back function of the flash memory to read the page processed by the first ECC unit 132 from the storage cell array to the page buffer/sensing circuit 170, and uses the first ECC The unit 132 decodes the read data (i.e., performs error detection and correction), and then uses the second ECC unit 134 to encode the decoded data again to generate an error correction code, and converts the code containing the generated error correction code Data is programmed into the original page of the memory cell array.

This data conversion is performed on all data stored in the first ECC portion 132 of the storage cell array 110 . The controller 150 automatically executes data conversion using the write-back function in the background without interfering with the operation of the flash memory 100, or automatically executes data conversion while no operations such as reading or writing are being performed. Data conversion using the write-back function. In addition, in a certain form, a flag indicating data conversion or non-conversion may be stored in the spare area, and the controller 150 refers to the flag to perform data conversion, and rewrites the flag after conversion.

Thus, according to the present embodiment, since data conversion is automatically performed by using the write-back function, switching of the error correction function from the first ECC unit 132 to the second ECC unit 134 can be smoothly performed.

表2 Next, a third embodiment of the present invention will be described. In this embodiment, the error detection and correction capability is switched according to the address space. Table 2 shows a setting example of the setting register 190 of this embodiment. The relationship between the address space and the corresponding flag is preset in the setting register 190 . The address space defines the range of the column address of the storage cell array 110, for example, the flag “0” is assigned to the address space 1, the flag “1” is assigned to the address space 2, and the flag “1” is assigned to the address space 3. 0". A flag "0" indicates selection of the first ECC unit 132, and a flag "1" indicates selection of the second ECC unit 134. Therefore, when reading or writing to the address space 1, the first ECC unit 132 is selected. The ECC unit 132 selects the second ECC unit 134 when reading or writing to the address space 2 is performed.

Table 2

FIG. 6 is a flowchart illustrating the switching operation of the error detection and correction capability of the ECC circuit according to the third embodiment. When performing a read or write operation, a command or an address for reading or writing is input from the outside through the input/output circuit 120 ( S200 ).

The controller 150 refers to the setting register 190, identifies the flag of the address space corresponding to the column address of the input address (S210), and selects the first ECC unit 132 or the second ECC according to the identified flag. part 134, so the first ECC part 132 or the second ECC part 134 is enabled via the enable signal EN_1 and the enable signal EN_2. In this way, during the read operation or the write operation, the error detection and correction is performed by the first ECC unit 132 or the second ECC unit 134 selected according to the address ( S230 ).

Thus, according to this embodiment, the error detection and correction capability can be changed according to the address space. For example, in the case where the computer on the host side manages the data rewriting times or erasing times of the storage unit array in units of blocks, the address space is set in units of blocks, and the number of times of data rewriting or erasing When the value exceeds a certain value, the flag of the address space is rewritten from "0" to "1". Thus, the error detection and correction capability can be changed according to the aging degradation of the memory cells in the address space.

Next, a specific example of the second ECC unit 134 will be described. The second ECC section 134 includes an encoder that encodes material using a BCH code, and a decoder that decodes the BCH-encoded material. (A) of FIG. 7 is a block diagram showing an internal structure of a BCH decoder. The BCH decoder 300 includes: a syndrome calculation unit 310 for evaluating syndromes of data, a Euclidean mutual division calculation unit 320 for calculating error location polynomials (error location polynomials, ELPs), calculating roots of error location polynomials and searching for errors The error location search part 330 of the location, and the error bit correction part 340 writes the corrected data back to the page buffer/sensing circuit 170 based on the searched error location.

The BCH decoder 300 is provided with input terminals for receiving the reset signal RST, the clock signal CLK for ECC calculation, the enable signal ENABLE_IN, the valid signal VALID_IN, and the data DATA_IN. The syndrome calculation unit 310 outputs the evaluation result and a start signal EUC_S indicating the start of calculation of the Euclidean mutual division to the Euclidean mutual division calculation unit 320 . The Euclidean mutual division calculation unit 320 outputs the calculation result of the error position polynomial and an end signal EUC_E indicating the end of the calculation to the error position search unit 330 .

(B) of FIG. 7 is a sequence diagram showing an example of processing in each part of the BCH decoder. t1 indicates the processing period of the syndrome calculation unit 310 , t2 indicates the processing period of the Euclidean mutual division calculation unit 320 , t3 indicates the processing period of the error location search unit 330 , and t4 indicates the processing period of the error bit correction unit 340 .

The BCH decoder 300 performs processing in synchronization with the input clock signal CLK, and can be operated when the enable signal ENABLE_IN transitions to H level. During the period of the H level of the valid signal VALID_IN, the data held in the page buffer/sensing circuit is imported from the DATA_IN to the syndrome calculation unit 310 . When the calculation of the syndrome ends, the syndrome calculation unit 310 outputs a pulse signal EUC_S indicating the start of the Euclidean mutual division, and in response to this, the Euclidean mutual division calculation unit 320 calculates the error position polynomial. When the calculation of the error location polynomial ends, the Euclidean mutual division calculation part 320 outputs a pulse signal EUC_E indicating the end, and in response thereto, the error location search part 330 searches for the error location. The error bit correction unit 340 rewrites the data of the page buffer/sensing circuit 170 through the output terminal DATA_OUT.

For example, in the case of error detection and correction of 8 bits per 528 bytes using the BCH code, syndrome calculation requires 149 clock cycles, Euclidean mutual division calculation requires 82 clock cycles, and error location search requires 143 clock cycles. clock cycles, 48 clock cycles for error correction, and 422 clock cycles overall. When the frequency of the clock signal CLK is 50 MHz, the cycle time of the clock is 20 ns, and the decoding process of the BCH code consumes 8.44 μs. If the size of one page of the page buffer/sensing circuit 170 is 2K bytes, it takes about 34 μs (1688 cycles=422*4).

On the other hand, in the case of 1-bit error detection and correction using the Hamming code, the number of clock cycles required for 2K-byte error detection and correction is 330 or so. If one cycle time of the clock is 20 ns, the processing is completed in about 6.7 μs. When compared simply with the 8-digit BCH code, it is sufficient to use about 1/6 of the processing time. In the case of a page length of 4K bytes and an array read time of 20 ns, in an 8-bit BCH code, tRD2=(20 μs+34 μs*2)=88 μs, in contrast, at 1 In the Hamming code of the bit, tRD2=(20 μs+(6.7 μs*2)=34 μs, the difference between the two is very large. Therefore, in the case of using the BCH code, the page read time (tRD2) or It affects the upper limit of the clock frequency of the continuous read operation.

In the above-described embodiment, a 1-bit error detection and correction function (first ECC unit 132 ) and an 8-bit error detection and correction function (second ECC unit 134 ) are dually implemented, but the circuit scale is 8 bits. The error detection and correction circuit is dominant, and the error bit correction unit 340 can be reused. Therefore, the ECC circuit 130 can calculate the syndrome by only adding a 1-bit error detection and correction circuit to the 8-bit error correction function. Department to achieve. Therefore, the impact on wafer size is not so affected.

In the above-mentioned embodiments, the error detection and correction using the Hamming code and the error detection and correction using the BCH code are illustrated, but this is an example, and the present invention is also applicable to the error detection and correction using other codes.

Furthermore, in the above-described embodiment, 8-bit error detection and correction is performed in the BCH code of the second ECC section 134, but this is an example, and the BCH code of the second ECC section 134 may also perform 2-bit or 4-bit error correction. 1-bit or 16-bit error detection correction. Furthermore, in the above-described embodiment, the first ECC unit 132 performs 1-bit error detection and correction, but this is an example. If there is an error detection and correction function based on the first ECC unit 132< In addition to the error detection and correction function, the first ECC unit 132 can also perform error detection and correction of more than 2 bits.

Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims.

10, 100: flash memory 20, 110: storage cell array 30, 170: page buffer/sensing circuit 40, 130: ECC circuit 42, 136: transmission circuit 44: ECC core 46: Error register 48, 138: write circuit 50, 120: input and output circuit 60: Data bus 132: The first ECC department 134: The second ECC part 135: ECC processing department 140: Address register 150: Controller 160: word line selection circuit 180: row selection circuit 190: set register 200: regular area 210: spare area 300: BCH decoder 310: Syndrome Calculation Department 320: Euclidean Mutual Division Calculation Department 330: wrong position search department 340: error bit correction unit Ax: column address information Ay: row address information BLK(0), BLK(1), ..., BLK(m-1): storage blocks CLK: clock signal CLK_ECC: internal clock signal DATA_IN: data EN_1: The first enable signal EN_2: The second enabling signal ENABLE_IN: enable signal EUC_E: end signal (pulse signal) EUC_S: start signal (pulse signal) S100, S110, S120, S130, S200, S210, S220, S230: steps t1, t2, t3, t4: during processing VALID_IN: valid signal

FIG. 1 is a diagram showing a schematic configuration of a conventional NAND flash memory equipped with an on-chip ECC function. FIG. 2 is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention. FIG. 3 is a diagram showing an internal structure of an ECC circuit according to an embodiment of the present invention. FIG. 4 is a diagram illustrating the operation of the ECC circuit according to the first embodiment of the present invention. FIG. 5 is a flowchart illustrating the switching operation of the error detection and correction capability of the ECC circuit according to the first embodiment of the present invention. FIG. 6 is a flowchart illustrating the switching operation of the error detection and correction capability of the ECC circuit according to the third embodiment of the present invention. 7(A) and 7(B) are block diagrams showing the structure of a decoder of the ECC circuit according to the embodiment of the present invention.

S100, S110, S120, S130: steps

Claims (10)

An error detection and correction method, which is an error detection and correction method for a semiconductor storage device, comprising: a setting step of setting a first error detection and correction function for selecting m-bit error detection and correction or performing n-bit error detection and correction The selection information of the second error detection and correction function, m and n are natural numbers, and m is less than n; and the execution step is to execute the first error detection and correction based on the selection information during a read operation or a write operation function or the second error detection correction function, wherein the selection information specifies a first address space of a memory cell array for selecting the first error detection correction function and a first address space for selecting the second error detection correction function The second address space of the functional storage unit array, the execution step is based on the first address space or the second address space corresponding to the address of the read operation or the write operation, and executes the The first error detection correction function or the second error detection correction function. The error detection and correction method according to claim 1, wherein the setting step can change the selection information from the outside through an instruction. The error detection and correction method according to claim 1, wherein the error detection and correction method further includes a switching step, the switching step is switching from the first error detection and correction function to the second error detection and correction function During operation, the first data related to the first error detection and correction function written into the storage unit array is converted into the second data related to the second error detection and correction function. The error detection and correction method according to claim 3, wherein the conversion step reads the first data from the storage cell array to the page buffer/sensing circuit, so that the second error detection and correction function and converting the read-out first data into the second data during operation, and writing the converted second data into the original position of the storage unit array. The error detection and correction method according to claim 1, wherein the first error detection and correction function uses Hamming code to perform 1-bit error detection and correction, and the second error detection and correction function uses Boss-Chard Holi-Hokungum codes perform 2-bit, 4-bit or 8-bit error detection and correction. The error detection and correction method according to claim 1, wherein the storage cell array is an inverse-and type storage cell array including a normal area and a spare area, and stored in the spare area are data that pass the first error detection. The parity check bits generated by the correction function or the second error detection correction function. A semiconductor storage device, comprising: a memory cell array; an error detection and correction circuit, including a first error detection and correction function for performing m-bit error detection and correction and a second error detection and correction function for performing n-bit error detection and correction, m , n is a natural number, m is less than n; set the temporary register, set the selection information for selecting the first error detection and correction function or the second error detection and correction function; and the controller, in the read operation or write When entering an action, execute the first error detection and correction function or the second error detection and correction function based on the selection information, Wherein, the controller includes a conversion unit, and when the conversion unit switches the operation from the first error detection and correction function to the second error detection and correction function, the data written into the storage unit array and the The first data related to the first error detection and correction function is converted into the second data related to the second error detection and correction function. The semiconductor storage device according to claim 7, wherein the setting register can change the selection information from the outside through an instruction. The semiconductor storage device according to claim 7, wherein the selection information specifies a first address space of the storage cell array for selecting the first error detection and correction function and a first address space for selecting the second error detection and correction function. detecting and correcting the second address space of the storage cell array, the controller based on the first address space or the second address space corresponding to the address of the read operation or the write operation, to perform the first error detection and correction function or the second error detection and correction function. The semiconductor storage device according to claim 7, wherein the switching unit reads out the first data from the storage cell array to a page buffer/sensing circuit to operate the first error detection and correction function The read-out first data is decoded, and then the decoded data is encoded again by using the second error detection and correction function to generate the second data, and the generated second data Write to the original location of the storage cell array.

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