TWI799053B - Method for manufacturing semiconductor structure - Google Patents

Abstract

A method of manufacturing a semiconductor structure including the following steps is provided. A first substrate is provided. A first bonding dielectric layer is formed on the first substrate. A second substrate is provided. A second bonding dielectric layer is formed on the second substrate. A bonding process is performed in such a manner that the first bonding dielectric layer faces the second bonding dielectric layer to form a semiconductor structure. After the bonding process is performed, a post bonding anneal process is performed on the semiconductor structure. A temperature of the post bonding anneal process is less than or equal to an upper limit of temperature of a packaging process. The method of manufacturing the semiconductor structure further includes performing at least one first ultraviolet light and heating treatment on the first bonding dielectric layer during the period from a process of forming the first bonding dielectric layer to before the bonding process. A temperature of the first ultraviolet light and heating treatment is less than or equal to the upper limit of temperature of the packaging process.

Description

Fabrication method of semiconductor structure

The present invention relates to a semiconductor manufacturing process, and more particularly to a manufacturing method of a semiconductor structure.

In the current bonding process, a bonding dielectric layer on two substrates is often used for bonding. In addition, after the bonding process is performed, a post bonding anneal process is performed for permanent bonding. However, during the post-bonding tempering process, the bonding dielectric layer often releases gas (such as hydrogen or water gas), and bubbles or voids are formed on the bonding surface. As a result, in the subsequent process, defects (such as cracks or peeling) are likely to occur on the bonding surface due to the existence of air bubbles or holes.

The invention provides a method for manufacturing a semiconductor structure, which can remove the gas in the bonding dielectric layer in advance.

The invention provides a method for manufacturing a semiconductor structure, which includes the following steps. A first substrate is provided. A first bonding dielectric layer is formed on the first substrate. A second substrate is provided. A second bonding dielectric layer is formed on the second substrate. A bonding process is performed in such a way that the first bonding dielectric layer faces the second bonding dielectric layer to form a semiconductor structure. After performing the bonding process, a post-bonding tempering process is performed on the semiconductor structure. The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process. The manufacturing method of the semiconductor structure further includes performing a first ultraviolet light and heat treatment on the first bonding dielectric layer at least once during the period from the process of forming the first bonding dielectric layer to the bonding process. The temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the encapsulation process.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the upper temperature limit of the packaging process may be less than or equal to 400° C.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the upper temperature limit of the packaging process may be less than or equal to 250° C.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the first ultraviolet light and heat treatment may be an in-situ ultraviolet light and heat treatment.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the first ultraviolet light and heat treatment may be ex-situ ultraviolet light and heat treatment.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the bonding process may be a hybrid bonding process or a dielectric layer-to-dielectric layer bonding process.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor structure may further include the following steps. After forming the first bonding dielectric layer and before performing the bonding process, at least one of a damascene process, a chemical mechanical polishing process, a cleaning process, and a nitrogen plasma treatment (N ₂ plasma treatment) process is performed. At the same time or after performing any one of the process of forming the first bonding dielectric layer, the damascene process, the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process, the first ultraviolet light and heat treatment are performed.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor structure may further include the following steps. During the period from the process of forming the second bonding dielectric layer to before performing the bonding process, at least one second ultraviolet light and heat treatment is performed on the second bonding dielectric layer.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the temperature of the second ultraviolet light and heat treatment may be less than or equal to the upper temperature limit of the packaging process.

According to an embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor structure may further include the following steps. After forming the second bonding dielectric layer and before performing the bonding process, at least one of a damascene process, a chemical mechanical polishing process, a cleaning process, and a nitrogen plasma treatment process is performed. At the same time or after performing any one of the process of forming the second bonding dielectric layer, the damascene process, the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process, the second ultraviolet light and heat treatment are performed.

Based on the above, in the manufacturing method of the semiconductor structure proposed by the present invention, during the period from the process of forming the first bonding dielectric layer to the bonding process, the first ultraviolet light and heating are performed on the first bonding dielectric layer at least once treatment, and the temperature of the post-bonding tempering process and the temperature of the first ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the first ultraviolet light and heat treatment can degas the first bonding dielectric layer, the gas (such as hydrogen or water gas) in the first bonding dielectric layer can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1 is a flowchart of a method of fabricating a semiconductor structure according to some embodiments of the present invention.

Referring to FIG. 1 , step S100 is performed to provide a first substrate. The first substrate can be a wafer (eg, a silicon wafer) or a glass substrate, but the invention is not limited thereto. In addition, required components such as isolation structures may be provided in the first substrate, and semiconductor elements (such as active devices and/or passive devices), dielectric layers and/or interconnection structures, etc. may be provided on the first substrate. The required components are omitted here.

Next, step S102 is performed to form a first bonding dielectric layer on the first substrate. The material of the first bonding dielectric layer is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride (SiCN). The method for forming the first bonding dielectric layer is, for example, chemical vapor deposition or physical vapor deposition.

In addition, step S104 is performed, during the period from the process of forming the first bonding dielectric layer (step S102 ) to the bonding process (step S112 ), at least one first ultraviolet light and heat treatment is performed on the first bonding dielectric layer. The temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the encapsulation process. Since the heat treatment in the first ultraviolet light and heat treatment can degas the first bonding dielectric layer, and the ultraviolet light treatment in the first ultraviolet light and heat treatment can enhance the degassing effect, so the first ultraviolet light and heat treatment can be removed in advance. A gas (eg, hydrogen or water) in the bonding dielectric layer. In this article, the term "ultraviolet light and heat treatment" refers to simultaneous ultraviolet light irradiation and heat treatment. In some embodiments, when the temperature of the first ultraviolet light and heat treatment is equal to the upper temperature limit of the packaging process, the first ultraviolet light and heat treatment may have a better degassing effect.

In addition, since the semiconductor device has an upper temperature limit that can be tolerated, an "upper temperature limit for packaging processing" is set to prevent excessive temperature from causing damage to the semiconductor device on the substrate. Additionally, different types of semiconductor components may have different upper temperature limits for packaging processing. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper limit of the encapsulation process temperature that a dynamic random access memory (DRAM) device can withstand is 250° C., the temperature of the first ultraviolet light and heat treatment is set to be lower than or equal to that of the DRAM device. The upper temperature limit of the packaging process (eg, 250° C.) is used to prevent damage to the DRAM element (semiconductor element) positioned on the first substrate due to excessive temperature.

In addition, after forming the first bonding dielectric layer and before performing the bonding process, at least one of a damascene process, a chemical mechanical polishing process, a cleaning process, and a nitrogen plasma treatment process may be performed. The first ultraviolet light and heat treatment may be performed simultaneously or after performing any one of the process of forming the first bonding dielectric layer, the damascene process, the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process. The damascene process may include patterning process, deposition process and chemical mechanical polishing process.

In some embodiments, the first UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment. For example, after the CMP process, the first UV and heat treatment (ie, in-situ UV and heat treatment) may be performed in situ in the CMP machine. In some other embodiments, after the chemical mechanical polishing process is performed, the first ultraviolet light and heat treatment (ie, ex-situ ultraviolet light and heat treatment) can be performed at other locations than the chemical mechanical polishing machine.

In addition, step S106 is performed to provide a second substrate. The second substrate can be a wafer (eg, a silicon wafer) or a glass substrate, but the invention is not limited thereto. In addition, required components such as isolation structures may be provided in the second substrate, and semiconductor elements (such as active devices and/or passive devices), dielectric layers and/or interconnection structures, etc. may be provided on the second substrate. The required components are omitted here.

Next, step S108 is performed to form a second bonding dielectric layer on the second substrate. The material of the second bonding dielectric layer is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The forming method of the second bonding dielectric layer is, for example, chemical vapor deposition or physical vapor deposition.

In addition, step S110 may be carried out, during the period from the process of forming the second bonding dielectric layer (step S108) to the bonding process (step S112), at least one second ultraviolet light and heat treatment is performed on the second bonding dielectric layer . The temperature of the second ultraviolet light and heat treatment may be less than or equal to the upper temperature limit of the encapsulation process. Since the heat treatment in the second ultraviolet light and heat treatment can degas the second bonding dielectric layer, and the ultraviolet light treatment in the second ultraviolet light and heat treatment can enhance the degassing effect, the first layer can be removed in advance. Gas (eg, hydrogen or water) in the second junction dielectric layer. In some embodiments, when the temperature of the second ultraviolet light and heat treatment is equal to the upper temperature limit of the encapsulation process, the second ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250°C, the temperature of the second ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the second substrate.

In addition, after forming the second bonding dielectric layer and before performing the bonding process, at least one of a damascene process, a chemical mechanical polishing process, a cleaning process, and a nitrogen plasma treatment process may be performed. At the same time or after performing any one of the process of forming the second bonding dielectric layer, the damascene process, the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process, the second ultraviolet light and heat treatment can be performed. The damascene process may include patterning process, deposition process and chemical mechanical polishing process.

In some embodiments, the second UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment. For example, after the CMP process, the second UV and heat treatment (ie, in-situ UV and heat treatment) can be performed in situ in the CMP machine. In some other embodiments, after the chemical mechanical polishing process, the second ultraviolet light and heat treatment (ie, ex-situ ultraviolet light and heat treatment) can be performed at other locations than the chemical mechanical polishing machine.

Then, step S112 is performed, and a bonding process is performed in such a way that the first bonding dielectric layer faces the second bonding dielectric layer to form a semiconductor structure. The semiconductor structure may include a first substrate, a first bonding dielectric layer, a second substrate, and a second bonding dielectric layer. The bonding process can be a hybrid bonding process or a dielectric-to-dielectric bonding process. In addition, the hybrid bonding process can be a front-to-front hybrid bonding process, a back-to-back hybrid bonding process, or a back-to-front hybrid bonding process. In some embodiments, the bonding process can be performed at normal temperature (eg, 25° C.).

Next, step S114 is performed. After the bonding process is performed, a post-bonding tempering process is performed on the semiconductor structure, thereby improving the bonding strength. The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process. In some embodiments, better bonding strength can be obtained when the temperature of the post-bonding tempering process is equal to the upper temperature limit of the packaging process. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that DRAM components can withstand is 250°C, the temperature of the post-bonding tempering process is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of DRAM components to prevent Excessive temperature will damage the DRAM device (semiconductor device) on the first substrate and/or the second substrate.

Based on the above-mentioned embodiments, it can be seen that in the method of manufacturing a semiconductor structure, during the period from the process of forming the first bonding dielectric layer to the bonding process, the first ultraviolet light and heat treatment are performed on the first bonding dielectric layer at least once, Moreover, the temperature of the post-bonding tempering process and the temperature of the first ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the first ultraviolet light and heat treatment can degas the first bonding dielectric layer, the gas (eg, hydrogen or moisture) in the first bonding dielectric layer can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

2A-2G are cross-sectional views of a fabrication process of a semiconductor structure according to some embodiments of the present invention.

Referring to FIG. 2A , a substrate 100 is provided. In this embodiment, the substrate 100 may be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. In addition, a dielectric layer 102 and at least one conductive layer 104 may be provided on the substrate 100 . The dielectric layer 102 is on the substrate 100 . In some embodiments, the dielectric layer 102 may be a multilayer structure. The conductive layer 104 is located in the dielectric layer 102 . In addition, there may be required components such as isolation structures in the substrate 100, and there may be required components such as semiconductor elements (such as active components and/or passive components) and/or other interconnection structures on the substrate 100, The description thereof is omitted here.

Referring to FIG. 2B , a bonding dielectric layer 106 is formed on the substrate 100 . For example, a bonding dielectric layer 106 can be formed on the dielectric layer 102 and the conductive layer 104 . In some embodiments, the bonding dielectric layer 106 may be a back end of line (BEOL) dielectric layer. The bonding dielectric layer 106 can be a single-layer structure or a multi-layer structure. The material of the bonding dielectric layer 106 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The method for forming the bonding dielectric layer 106 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 2C , a bonding pad 108 may be formed in the bonding dielectric layer 106 . The bonding pads 108 are electrically connected to the conductive layer 104 . Thereby, the base structure 110 can be formed. The base structure 110 may include a substrate 100 , a dielectric layer 102 , a conductive layer 104 , a bonding dielectric layer 106 and bonding pads 108 . In some embodiments, the bonding pads 108 may be formed by a damascene process. The damascene process may include patterning process, deposition process and chemical mechanical polishing process.

In some embodiments, after the bonding pads 108 are formed, a cleaning process may be performed on the base structure 110 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 110 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 110 .

In addition, during the period from the process of forming the bonding dielectric layer 106 in FIG. 2B to before performing the bonding process in FIG. 2G , the bonding dielectric layer 106 is subjected to at least one first ultraviolet light and heat treatment. The temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 106 may be subjected to the first ultraviolet light and heat treatment at the same time as or after performing any process. Since the heat treatment in the first ultraviolet light and heat treatment can degas the bonding dielectric layer 106, and the ultraviolet light treatment in the first ultraviolet light and heat treatment can improve the degassing effect, so the bonding dielectric layer 106 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 106 . In some embodiments, when the temperature of the first ultraviolet light and heat treatment is equal to the upper temperature limit of the packaging process, the first ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250° C., the temperature of the first ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (such as 250° C.) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 100 . In some embodiments, the first UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 2D , a substrate 200 is provided. In this embodiment, the substrate 200 can be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. Additionally, a dielectric layer 202 and at least one conductive layer 204 may be provided on the substrate 200 . The dielectric layer 202 is on the substrate 200 . In some embodiments, the dielectric layer 202 may be a multilayer structure. The conductive layer 204 is located in the dielectric layer 202 . In addition, there may be required components such as isolation structures in the substrate 200, and there may be required components such as semiconductor elements (such as active components and/or passive components) and/or other interconnection structures on the substrate 200, The description thereof is omitted here.

Referring to FIG. 2E , a bonding dielectric layer 206 is formed on the substrate 200 . For example, a bonding dielectric layer 206 can be formed on the dielectric layer 202 and the conductive layer 204 . In some embodiments, the bonding dielectric layer 206 may be a back end of line (BEOL) dielectric layer. The bonding dielectric layer 206 can be a single-layer structure or a multi-layer structure. The material of the bonding dielectric layer 206 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The formation method of the bonding dielectric layer 206 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 2F , bonding pads 208 may be formed in the bonding dielectric layer 206 . The bonding pad 208 can be electrically connected to the conductive layer 204 . Thereby, the base structure 210 can be formed. The base structure 210 may include a substrate 200 , a dielectric layer 202 , a conductive layer 204 , a bonding dielectric layer 206 and bonding pads 208 . In some embodiments, the bonding pads 208 may be formed by a damascene process. The damascene process may include patterning process, deposition process and chemical mechanical polishing process.

In some embodiments, after the bonding pads 208 are formed, a cleaning process may be performed on the base structure 210 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 210 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 210 .

In addition, during the period from the process of forming the bonding dielectric layer 206 in FIG. 2E to before performing the bonding process in FIG. 2G , the bonding dielectric layer 206 may be subjected to at least one second ultraviolet light and heat treatment. The temperature of the second ultraviolet light and heat treatment may be less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 206 may be subjected to a second ultraviolet light and heat treatment at the same time or after performing any process. Since the heat treatment in the second ultraviolet light and heat treatment can degas the bonding dielectric layer 206, and the ultraviolet light treatment in the second ultraviolet light and heat treatment can improve the degassing effect, so the bonding dielectric layer 206 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 206 . In some embodiments, when the temperature of the second ultraviolet light and heat treatment is equal to the upper temperature limit of the encapsulation process, the second ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250°C, the temperature of the second ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 200 . In some embodiments, the second UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 2G , the bonding process is performed with the bonding dielectric layer 106 facing the bonding dielectric layer 206 to form the semiconductor structure 10 . In this embodiment, the semiconductor structure 10 may include a base structure 110 and a base structure 210 . The bonding process may be a hybrid bonding process, such as a front-to-front hybrid bonding process. In some embodiments, the bonding process can be performed at normal temperature (eg, 25° C.).

Next, after performing the bonding process, a post-bonding tempering process is performed on the semiconductor structure 10 , thereby improving the bonding strength. The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process. In some embodiments, better bonding strength can be obtained when the temperature of the post-bonding tempering process is equal to the upper temperature limit of the packaging process. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that DRAM components can withstand is 250°C, the temperature of the post-bonding tempering process is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of DRAM components to prevent Excessive temperature will damage the DRAM devices (semiconductor devices) on the substrate 100 and/or the substrate 200 .

Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the semiconductor structure 10, during the period from the process of forming the bonding dielectric layer 106 to before performing the bonding process, the bonding dielectric layer 106 is subjected to the first ultraviolet light and heat treatment at least once, and The temperature of the post-bonding tempering process and the temperature of the first ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the first ultraviolet light and heat treatment can degas the bonding dielectric layer 106 , the gas (eg, hydrogen or moisture) in the bonding dielectric layer 106 can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

3A to 3G are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

Referring to FIG. 3A , a substrate 300 is provided. In this embodiment, the substrate 300 may be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. In addition, there may be a through-substrate via (TSV) 302 in the substrate 300 . The TSV 302 runs through the substrate 300 and may protrude from the backside of the substrate 300 . For example, a thinning process and an etching process may be performed on the back of the substrate 300 , so that the through holes 302 penetrate through the substrate 300 and protrude from the back of the substrate 300 . In addition, the substrate 300 may have required components such as isolation structures, and the substrate 300 may have semiconductor elements (such as active elements and/or passive elements), dielectric layers and/or interconnect structures, etc. component, its description is omitted here. On the other hand, the substrate 300 can be disposed on the carrier 304 , and the substrate 300 and the carrier 304 can be bonded by the adhesive layer 306 .

Referring to FIG. 3B , a bonding dielectric layer 308 is formed on the substrate 300 . The bonding dielectric layer 308 may cover the TSV 302 . The material of the bonding dielectric layer 308 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The formation method of the bonding dielectric layer 308 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 3C , a chemical mechanical polishing process may be performed on the bonding dielectric layer 308 until the through substrate holes 302 are exposed. Thereby, the base structure 310 can be formed. The base structure 310 may include a base 300 , a TSV 302 and a bonding dielectric layer 308 . In some embodiments, a cleaning process may be performed on the base structure 310 after the chemical mechanical polishing process is performed on the bonding dielectric layer 308 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 310 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 310 .

In addition, during the period from the process of forming the bonding dielectric layer 308 in FIG. 3B to before performing the bonding process in FIG. 3G , the bonding dielectric layer 308 is subjected to at least one first ultraviolet light and heat treatment. The temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 308 may be subjected to the first ultraviolet light and heat treatment at the same time or after performing any process. Because the heat treatment in the first ultraviolet light and heat treatment can degas the bonding dielectric layer 308, and the ultraviolet light treatment in the first ultraviolet light and heat treatment can improve the degassing effect, so the bonding dielectric layer 308 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 308 . In some embodiments, when the temperature of the first ultraviolet light and heat treatment is equal to the upper temperature limit of the packaging process, the first ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250° C., the temperature of the first ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (such as 250° C.) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 300 . In some embodiments, the first UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 3D , a substrate 400 is provided. In this embodiment, the substrate 400 may be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. Additionally, there may be TSVs 402 in the substrate 400 . The TSV 402 runs through the substrate 400 and may protrude from the surface of the substrate 400 . For example, a thinning process and an etching process may be performed on the back of the substrate 400 , so that the through holes 402 penetrate through the substrate 400 and protrude from the back of the substrate 400 . In addition, the substrate 400 may have required components such as isolation structures, and the substrate 400 may have semiconductor elements (such as active elements and/or passive elements), dielectric layers and/or interconnect structures, etc. component, its description is omitted here. On the other hand, the substrate 400 can be disposed on the carrier 404 , and the substrate 400 and the carrier 404 can be bonded by the adhesive layer 406 .

Referring to FIG. 3E , a bonding dielectric layer 408 is formed on the substrate 400 . The bonding dielectric layer 408 may cover the TSV 402 . The material of the bonding dielectric layer 408 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The method for forming the bonding dielectric layer 408 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 3F , a chemical mechanical polishing process may be performed on the bonding dielectric layer 408 until the through substrate holes 402 are exposed. Thereby, the base structure 410 can be formed. The base structure 410 may include a base 400 , a TSV 402 and a bonding dielectric layer 408 . In some embodiments, a cleaning process may be performed on the base structure 410 after the chemical mechanical polishing process is performed on the bonding dielectric layer 408 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 410 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 410 .

In addition, during the period from the process of forming the bonding dielectric layer 408 in FIG. 3E to before performing the bonding process in FIG. 3G , the bonding dielectric layer 408 may be subjected to at least one second ultraviolet light and heat treatment. The temperature of the second ultraviolet light and heat treatment may be less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 408 may be subjected to the second ultraviolet light and heat treatment at the same time or after performing any process. Since the heat treatment in the second ultraviolet light and heat treatment can degas the bonding dielectric layer 408, and the ultraviolet light treatment in the second ultraviolet light and heat treatment can enhance the degassing effect, the bonding dielectric layer 408 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 408 . In some embodiments, when the temperature of the second ultraviolet light and heat treatment is equal to the upper temperature limit of the encapsulation process, the second ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250°C, the temperature of the second ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 400 . In some embodiments, the second UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 3G , the bonding process is performed with the bonding dielectric layer 308 facing the bonding dielectric layer 408 to form the semiconductor structure 20 . In this embodiment, the semiconductor structure 20 may include a base structure 310 and a base structure 410 . The bonding process may be a hybrid bonding process, such as a back-to-back hybrid bonding process. In some embodiments, the bonding process can be performed at normal temperature (eg, 25° C.).

Next, after the bonding process is performed, a post-bonding tempering process is performed on the semiconductor structure 20 , thereby improving the bonding strength. The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process. In some embodiments, better bonding strength can be obtained when the temperature of the post-bonding tempering process is equal to the upper temperature limit of the packaging process. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that DRAM components can withstand is 250°C, the temperature of the post-bonding tempering process is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of DRAM components to prevent Excessive temperature will damage the DRAM devices (semiconductor devices) on the substrate 300 and/or the substrate 400 .

In some embodiments, the carrier 304 , the adhesive layer 306 , the carrier 404 and/or the adhesive layer 406 may be selectively removed after the post-bonding tempering process is performed on the semiconductor structure 20 .

Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the semiconductor structure 20, during the period from the process of forming the bonding dielectric layer 308 to before performing the bonding process, the bonding dielectric layer 308 is subjected to the first ultraviolet light and heat treatment at least once, and The temperature of the post-bonding tempering process and the temperature of the first ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the first ultraviolet light and heat treatment can degas the bonding dielectric layer 308 , the gas (eg, hydrogen or moisture) in the bonding dielectric layer 308 can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

4A to 4E are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

Referring to FIG. 4A , a substrate 500 is provided. In this embodiment, the substrate 500 may be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. In addition, a dielectric layer 502 and at least one conductive layer 504 may be provided on the substrate 500 . The dielectric layer 502 is on the substrate 500 . In some embodiments, the dielectric layer 502 may be a multilayer structure. The conductive layer 504 is located in the dielectric layer 502 . In addition, there may be required components such as isolation structures in the substrate 500, and there may be required components such as semiconductor elements (such as active components and/or passive components) and/or other interconnection structures on the substrate 500, The description thereof is omitted here.

Referring to FIG. 4B , a bonding dielectric layer 506 is formed on the substrate 500 . Thereby, the base structure 508 can be formed. The base structure 508 may include a substrate 500 , a dielectric layer 502 , a conductive layer 504 and a bonding dielectric layer 506 . The material of the bonding dielectric layer 506 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The method for forming the bonding dielectric layer 506 is, for example, chemical vapor deposition or physical vapor deposition. In some embodiments, a chemical mechanical polishing process may be performed on the bonding dielectric layer 506 to planarize the surface of the bonding dielectric layer 506 .

In some embodiments, a cleaning process may be performed on the base structure 508 after the chemical mechanical polishing process is performed on the bonding dielectric layer 506 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 508 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 508 .

In addition, during the period from the process of forming the bonding dielectric layer 506 in FIG. 4B to before performing the bonding process in FIG. 4E , the bonding dielectric layer 506 is subjected to at least one first ultraviolet light and heat treatment. The temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 506 may be subjected to the first ultraviolet light and heat treatment at the same time or after performing any process. Since the heat treatment in the first ultraviolet light and heat treatment can degas the bonding dielectric layer 506, and the ultraviolet light treatment in the first ultraviolet light and heat treatment can improve the degassing effect, so the bonding dielectric layer 506 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 506 . In some embodiments, when the temperature of the first ultraviolet light and heat treatment is equal to the upper temperature limit of the packaging process, the first ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250° C., the temperature of the first ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (such as 250° C.) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 500 . In some embodiments, the first UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 4C , a substrate 600 is provided. In this embodiment, the substrate 600 may be a semiconductor substrate, such as a silicon substrate, but the invention is not limited thereto. Additionally, a dielectric layer 602 and at least one conductive layer 604 may be provided on the substrate 600 . A dielectric layer 602 is located on the substrate 600 . In some embodiments, the dielectric layer 602 may be a multilayer structure. Conductive layer 604 is located within dielectric layer 602 . In addition, there may be required components such as isolation structures in the substrate 600, and there may be required components such as semiconductor elements (such as active components and/or passive components) and/or other interconnection structures on the substrate 600, The description thereof is omitted here.

Referring to FIG. 4D , a bonding dielectric layer 606 is formed on the substrate 600 . Thereby, the base structure 608 can be formed. The base structure 608 may include a substrate 600 , a dielectric layer 602 , a conductive layer 604 and a bonding dielectric layer 606 . The material of the bonding dielectric layer 606 is, for example, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. The method for forming the bonding dielectric layer 606 is, for example, chemical vapor deposition or physical vapor deposition. In some embodiments, a chemical mechanical polishing process may be performed on the bonding dielectric layer 606 , thereby planarizing the surface of the bonding dielectric layer 606 .

In some embodiments, after the chemical mechanical polishing process is performed on the bonding dielectric layer 606 , a cleaning process may be performed on the base structure 608 . After performing the cleaning process, a nitrogen plasma treatment process may be performed on the base structure 608 . After performing the nitrogen plasma treatment process, a cleaning process may be performed on the base structure 608 .

In addition, during the period from the process of forming the bonding dielectric layer 606 in FIG. 4D to before performing the bonding process in FIG. 4E , the bonding dielectric layer 606 may be subjected to at least one second ultraviolet light and heat treatment. The temperature of the second ultraviolet light and heat treatment may be less than or equal to the upper temperature limit of the encapsulation process. For example, during the above period, the bonding dielectric layer 606 may be subjected to a second ultraviolet light and heat treatment while or after any process is performed. Since the heat treatment in the second ultraviolet light and heat treatment can degas the bonding dielectric layer 606, and the ultraviolet light treatment in the second ultraviolet light and heat treatment can enhance the degassing effect, the bonding dielectric layer 606 can be removed in advance. Gas (eg, hydrogen or water) in the electrical layer 606 . In some embodiments, when the temperature of the second ultraviolet light and heat treatment is equal to the upper temperature limit of the encapsulation process, the second ultraviolet light and heat treatment may have a better degassing effect. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that the DRAM element can withstand is 250°C, the temperature of the second ultraviolet light and heat treatment is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of the DRAM element, In order to prevent excessive temperature from damaging the DRAM element (semiconductor element) on the substrate 600 . In some embodiments, the second UV and heat treatment can be an in-situ UV and heat treatment or an ex-situ UV and heat treatment.

Referring to FIG. 4E , the bonding process is performed with the bonding dielectric layer 506 facing the bonding dielectric layer 606 to form the semiconductor structure 30 . In this embodiment, the semiconductor structure 30 may include a base structure 508 and a base structure 608 . The bonding process may be a dielectric-to-dielectric bonding process. In some embodiments, the bonding process can be performed at normal temperature (eg, 25° C.).

Next, after the bonding process is performed, a post-bonding tempering process is performed on the semiconductor structure 30 , thereby improving the bonding strength. The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process. In some embodiments, better bonding strength can be obtained when the temperature of the post-bonding tempering process is equal to the upper temperature limit of the packaging process. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 400°C. In some embodiments, the upper temperature limit of the packaging process may be less than or equal to 250°C. For example, since the upper temperature limit of the packaging process that DRAM components can withstand is 250°C, the temperature of the post-bonding tempering process is set to be less than or equal to the upper temperature limit (eg, 250°C) of the packaging process of DRAM components to prevent Excessive temperature will damage the DRAM devices (semiconductor devices) on the substrate 500 and/or the substrate 600 .

Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the semiconductor structure 30, during the period from the process of forming the bonding dielectric layer 506 to before performing the bonding process, the bonding dielectric layer 506 is subjected to the first ultraviolet light and heat treatment at least once, and The temperature of the post-bonding tempering process and the temperature of the first ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the first ultraviolet light and heat treatment can degas the bonding dielectric layer 506 , the gas (eg, hydrogen or moisture) in the bonding dielectric layer 506 can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

To sum up, in the manufacturing method of the semiconductor structure of the above embodiment, during the period from the process of forming the bonding dielectric layer to the bonding process, the bonding dielectric layer is subjected to ultraviolet light and heat treatment at least once, and after bonding The temperature of the tempering process and the temperature of the ultraviolet light and heat treatment are less than or equal to the upper temperature limit of the packaging process. Since the ultraviolet light and heat treatment can degas the bonding dielectric layer, the gas (eg, hydrogen or moisture) in the bonding dielectric layer can be removed in advance. In this way, in the subsequent post-bonding tempering process, bubbles or holes can be prevented from being generated on the bonding surface. In this way, defects (such as cracks or peeling) on the bonding surface can be avoided in subsequent processes.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 20, 30: Semiconductor structures 100, 200, 300, 400, 500, 600: Base 102, 202, 502, 602: dielectric layer 104, 204, 504, 604: conductive layer 106, 206, 308, 408, 506, 606: bonding dielectric layers 108, 208: Bonding pads 110, 210, 310, 410, 508, 608: base structure 302, 402: Basal perforation 304, 404: carrier board 306, 406: Adhesive layer S100, S102, S104, S106, S108, S110, S112, S114: Steps

FIG. 1 is a flowchart of a method of fabricating a semiconductor structure according to some embodiments of the present invention. 2A-2G are cross-sectional views of a fabrication process of a semiconductor structure according to some embodiments of the present invention. 3A to 3G are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention. 4A to 4E are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

S100, S102, S104, S106, S108, S110, S112, S114: steps

Claims (9)

A method of manufacturing a semiconductor structure, comprising: providing a first substrate; forming a first bonding dielectric layer on the first substrate; providing a second substrate; forming a second bonding dielectric layer on the second substrate; performing a bonding process in such a way that the first bonding dielectric layer faces the second bonding dielectric layer to form a semiconductor structure; and after performing the bonding process, performing a post-bonding tempering process on the semiconductor structure, wherein The temperature of the post-bonding tempering process is less than or equal to the upper temperature limit of the packaging process, and the manufacturing method of the semiconductor structure further includes: a period from the process of forming the first bonding dielectric layer to before performing the bonding process , performing at least one first ultraviolet light and heat treatment on the first bonding dielectric layer, wherein the temperature of the first ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the packaging process. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the upper limit of the packaging process temperature is less than or equal to 400°C. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the upper limit of the packaging process temperature is less than or equal to 250°C. The method for manufacturing a semiconductor structure according to claim 1, wherein the first ultraviolet light and heat treatment includes in-situ ultraviolet light and heat treatment. The method for manufacturing a semiconductor structure according to claim 1, wherein the first ultraviolet light and heat treatment includes ex-situ ultraviolet light and heat treatment. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the bonding process includes a hybrid bonding process or a dielectric layer-to-dielectric layer bonding process. The method for manufacturing a semiconductor structure according to claim 1, further comprising: after forming the first bonding dielectric layer and before performing the bonding process, performing a damascene process, a chemical mechanical polishing process, a cleaning process, a nitrogen electrode At least one of the slurry treatment process, wherein during the process of forming the first bonding dielectric layer, the damascene process, the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process Simultaneously or after any of them, the first ultraviolet light and heat treatment are performed. The method for manufacturing a semiconductor structure according to claim 1, further comprising: during the period from the process of forming the second bonding dielectric layer to before performing the bonding process, performing at least one process on the second bonding dielectric layer The second ultraviolet light and heat treatment, wherein the temperature of the second ultraviolet light and heat treatment is less than or equal to the upper temperature limit of the packaging process. The method for manufacturing a semiconductor structure according to claim 8, further comprising: performing a damascene process, a chemical mechanical polishing process, and a cleaning process after forming the second bonding dielectric layer and before performing the bonding process . At least one of the nitrogen plasma treatment process, wherein the process of forming the second bonding dielectric layer, the damascene process, the Simultaneously or after any one of the chemical mechanical polishing process, the cleaning process, and the nitrogen plasma treatment process, the second ultraviolet light and heat treatment are performed.

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