TWI798993B - Detection circuit, DC-DC converter and power supply device - Google Patents

Abstract

The present invention mainly discloses a detection circuit for integration in a DC-DC power converter including at least one drive unit, at least one switch unit, at least one inductor and a capacitor, and includes: a first detection unit, a A second detection unit, and an electrical state judgment unit. Wherein, the first detection unit is coupled to an inductance connection node of the switch unit, and is used for performing a first electrical state judgment operation on the inductance connection node, so as to generate a first detection signal. Moreover, the second detection unit is coupled to the inductance connection node, and is used for performing a second electrical state judgment operation on the inductance connection node, so as to generate a second detection signal. Further, the electrical state judging unit generates a state indication signal for indicating an electrical connection state of the inductor connection node according to the first detection signal and the second detection signal, so that the system can determine whether the inductor is connected to the The inductance connection node is connected to determine whether to turn on the designated switch unit.

Description

Detection circuit, DC-DC converter and power supply device

The invention relates to the technical field of electronic circuits, in particular to a detection circuit, which can be applied to a DC-DC converter and used to detect the connection state between a switch arm and an inductor.

As known, there are various types of DC-DC power conversion circuits, including Buck, Boost, Inverter, and Buck-Boost. Under certain application conditions, the DC-DC power conversion circuit needs to output more current, which makes the inductor current larger. However, limited by the saturation inductor current of the inductor, the output current of the DC-DC power conversion circuit is also limited accordingly. In order to solve this problem, it is necessary to make the DC-DC power conversion circuit have multiple channels through circuit design, so as to ensure that it has a certain driving capability, and at the same time, the inductor current in each channel can also be controlled below the saturated inductor current.

For example, FIG. 1 shows a first structural diagram of a conventional step-up-down power conversion circuit adopting a multi-channel design. As shown in FIG. 1 , a conventional step-up-step-down power conversion circuit 1a adopting a multi-channel design includes: a plurality of driving units 10a, a plurality of switching units, a plurality of inductors 13a and a capacitor 14a, wherein each of the The switch unit is controlled by the driving unit 10a, and includes an upper arm switch element 11a and a lower arm switch element 12a. It should be noted that, in each of the switch units, there is an output node (SW1a, SW2a, . . . , SWNa) between the upper arm switch element 11a and the lower arm switch element 12a.

Further, FIG. 2 shows a second structural diagram of a conventional step-up-down power conversion circuit adopting a multi-channel design. Comparing Fig. 2 with Fig. 1, it can be seen that the step-up-step-down power conversion circuit 1a shown in Fig. 2 adopts a four-channel design. When the boost-buck power conversion circuit 1a is actually applied, each output node (SW1a, SW2a, SW3a, SW4a) will be adaptively switched to different connection states. For example, as shown in FIG. 2, the first output node SW1a is normally connected to the inductor 13a, the second output node SW2a is floating, the third output node SW3a is short-circuited to ground, and the fourth An output node SW4a is coupled to a high potential (input voltage V _IN ).

Therefore, it is necessary to judge the relationship between each output node (SW1a, SW2a, SW3a, SW4a) and each The connection state of an inductor 13a. This is done for two purposes. First, when all phases are required to work, it is ensured that each output node is properly connected to the inductor. Second, when only certain phases need to work, it is still necessary to decide whether to turn on the switch unit of the corresponding path according to whether the inductor is connected to the output node, so as to reduce power consumption. However, the conventional DC-DC power conversion circuit with multi-channel design still lacks the function of automatically detecting and judging the connection status of each output node.

It can be seen from the above description that there is an urgent need for a detection circuit in the art.

The main purpose of the present invention is to provide a detection circuit that can be integrated in a DC-DC converter to detect the connection state between the switch unit and the inductor, so that the system can rely on whether the inductor is connected to the inductor connection node To determine whether to turn on the specified switch unit, so as to reduce power consumption.

To achieve the above object, the present invention proposes an embodiment of the detection circuit, which is applied in a DC-DC power converter and includes: a first detection unit coupled to the DC-DC power converter An inductance connection node of a switch unit is coupled to an enable signal and a clock signal at the same time, so as to perform a first electrical state judgment operation on the inductance connection node according to the enable signal and the clock signal; a first Two detection units, coupled to the inductive connection node, the enable signal and the clock signal, so as to perform a second electrical state judgment operation on the inductive connection node according to the enable signal and the clock signal; and an electrical The state judging unit is coupled to a first detection signal transmitted by the first detection unit and a second detection signal transmitted by the second detection unit, so as to generate a user according to the first detection signal and the second detection signal A state indication signal representing an electrical connection state of the inductance connection node is used.

In one embodiment, the electrical state judging unit is an AND gate, and has a first terminal coupled to the first detection signal, a second terminal coupled to the second detection signal, and used to transmit the An output terminal of the status indication signal.

In one embodiment, the first detection unit includes: A first P-type MOSFET element, the source of which is coupled to an operating voltage; a first resistor, one end of which is coupled to the drain of the first P-type MOSFET element; a second resistor, one end of which is connected to the first resistor The other end forms a first common contact point, and the first common contact point is coupled to the inductance connection node; a first capacitor, one end of which is coupled to the other end of the second resistor, and the other end is coupled to a A ground terminal; a first timer, coupled to the enabling signal En and the clock signal, thereby performing a timing operation according to the enabling signal and the clock signal, and outputting a first timing signal; a first OR gate, It has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the enabling signal, the second input terminal is coupled to the first timing signal, and the output terminal is coupled to the first timing signal. A gate of a P-type MOSFET element; a first Schmitt trigger, having an input terminal and an output terminal, the input terminal is coupled to a second common connection between the second resistor and the first capacitor point; and a first latch having a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the first Schmitt trigger an output terminal, the second input terminal is coupled to the first timing signal, and the third input terminal is coupled to the enable signal.

In one embodiment, the second detection unit includes: a second P-type MOSFET element, the source of which is coupled to the operating voltage; a third resistor, one end of which is coupled to the drain of the second P-type MOSFET element; A fourth resistor, one end of which and the other end of the third resistor form a third common point, and the third common point is coupled to the inductance connection node; a first N-type MOSFET element, the drain of which is coupled connected to the other end of the fourth resistor, and its source is coupled to the ground; a second timer is coupled to the enable signal and the clock signal, so as to execute the described Timing operation, and output a second timing signal; a second OR gate, with a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the enable signal, the second input terminal is coupled to the second timing signal number, and the output terminal is coupled to the gate of the second P-type MOSFET element; a second Schmitt trigger has a first input terminal, a second input terminal and an output terminal, and the first input The terminal is coupled to a fourth common point between the fourth resistor and the drain of the first N-type MOSFET element, and the second input terminal is coupled to the second timing signal; a signal delayer has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the second Schmitt trigger; an AND gate has a first input terminal, a second input terminal and an output terminal, and the first input terminal terminal is coupled to the output terminal of the signal delayer, and the second input terminal is coupled to the second timing signal; and a second latch has a first input terminal, a second input terminal, a third An input terminal and an output terminal, the first input terminal is coupled to the output terminal of the AND gate, the second input terminal is coupled to the second timing signal, and the third input terminal is coupled to the operating voltage.

In one embodiment, the signal delayer is any one selected from the group consisting of a digital delay circuit, an analog delay circuit, a signal delay element, and a signal delay line.

Moreover, the present invention also proposes a DC-DC converter, which includes at least one drive unit, at least one switch unit, at least one inductor, and a capacitor; it is characterized in that the DC-DC converter further includes at least one detection circuit , wherein the detection circuit is coupled to an inductance connection node of the switch unit to detect an electrical connection state of the inductance connection node, and includes: a first detection unit coupled to the DC-DC power converter An inductive connection node of a switch unit, and coupled to an enable signal and a clock signal at the same time, so as to perform a first electrical state judgment operation on the inductive connection node according to the enable signal and the clock signal; The second detection unit is coupled to the inductive connection node, the enable signal and the clock signal, so as to perform a second electrical state judgment operation on the inductive connection node according to the enable signal and the clock signal; and an electrical A sex status judging unit, coupled to a first detection signal transmitted by the first detection unit and a second detection signal transmitted by the second detection unit, so as to generate A state used to represent an electrical connection state of the inductively connected node indicator signal.

In one embodiment, the electrical state judging unit is an AND gate, and has a first terminal coupled to the first detection signal, a second terminal coupled to the second detection signal, and used to transmit the An output terminal of the status indication signal.

In one embodiment, the first detection unit includes: a first P-type MOSFET element, the source of which is coupled to an operating voltage; a first resistor, one end of which is coupled to the drain of the first P-type MOSFET element; A second resistor, one end of which and the other end of the first resistor form a first common point, and the first common point is coupled to the inductance connection node; a first capacitor, one end of which is coupled to the second The other end of the resistor, and the other end is coupled to a ground terminal; a first timer, coupled to the enable signal and the clock signal, so as to perform a timing operation according to the enable signal and the clock signal, and output A first timing signal; a first OR gate, having a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the enabling signal, and the second input terminal is coupled to the first A timing signal, and the output terminal is coupled to the gate of the first P-type MOSFET element; a first Schmitt trigger, has an input terminal and an output terminal, and the input terminal is coupled to the second resistor and A second common contact between the first capacitors; and a first latch having a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal The output end of the first Schmitt trigger is coupled, the second input end is coupled to the first timing signal, and the third input end is coupled to the enable signal.

In one embodiment, the second detection unit includes: a second P-type MOSFET element, the source of which is coupled to the operating voltage; a third resistor, one end of which is coupled to the drain of the second P-type MOSFET element; A fourth resistor, one end of which and the other end of the third resistor form a third common point, and the third common point is coupled to the inductance connection node; a first N-type MOSFET element, the drain of which is coupled Connect to the other end of the fourth resistor, And its source is coupled to the ground terminal; a second timer is coupled to the enable signal and the clock signal, so as to perform the timing operation according to the enable signal and the clock signal, and output a second timing Signal; a second OR gate, having a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the enabling signal, and the second input terminal is coupled to The second timing signal, and the output end is coupled to the gate of the second P-type MOSFET element; a second Schmitt trigger has a first input end, a second input end and an output end, and The first input end is coupled to a fourth common point between the fourth resistor and the drain of the first N-type MOSFET element, the second input end is coupled to the second timing signal; a signal delayer , having an input end and an output end, and the input end is coupled to the output end of the second Schmitt trigger; an AND gate, having a first input end, a second input end and an output end, The first input terminal is coupled to the output terminal of the signal delayer, and the second input terminal is coupled to the second timing signal; and a second latch has a first input terminal and a second input terminal , a third input terminal and an output terminal, the first input terminal is coupled to the output terminal of the AND gate, the second input terminal is coupled to the second timing signal, and the third input terminal is coupled to the operating voltage.

Further, the present invention also proposes a power supply device, which is characterized in that it includes at least one DC-DC converter, and the DC-DC converter has the detection circuit of the present invention as mentioned above.

1a: Step-up-step-down power conversion circuit

10a: Drive unit

11a: Upper arm switching element

12a: Lower arm switching element

13a: Inductance

14a: capacitance

1: DC-DC power conversion device

10: Drive unit

12: switch unit

121: upper arm switch element

122: lower arm switch element

13: Inductance

14: capacitance

2: Detection circuit

21: The first detection unit

211: First timer

212: first or gate

213: The first Schmitt trigger

214: the first latch

21I1: the first inverter

21I2: Second inverter

22: The second detection unit

221: second timer

222:Second OR gate

223:Second Schmitt trigger

224: Signal delayer

225: gate

226: Second latch

22I3: The third inverter

22I4: The fourth inverter

22I5: fifth inverter

22I6: sixth inverter

23: Electrical state judgment unit

MP1: The first P-type MOSFET component

MP2: The second P-type MOSFET

MN1: the first N-type MOSFET

R1: the first resistor

R2: Second resistor

R3: the third resistor

R4: the fourth resistor

C1: the first capacitor

Fig. 1 is the first structural diagram of a known step-up-down power conversion circuit with multi-channel design; Fig. 2 is the second structural diagram of a conventional step-up-down power conversion circuit with multi-channel design ; Fig. 3 is a structural diagram of a DC-DC power conversion device integrated with a detection circuit of the present invention; Fig. 4 is a block diagram of a detection circuit of the present invention; Fig. 5 is the first detection unit shown in Fig. 4 Circuit topology diagrams; and FIG. 6 is a circuit topology diagram of the second detection unit shown in FIG. 4 .

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are hereby attached.

FIG. 3 shows a structure diagram of a DC-DC power conversion device integrated with a detection circuit of the present invention. As shown in Figure 3, the DC-DC power conversion device 1 adopts a multi-channel design, and includes: N drive units 10, N switch units 12, N inductors 13, N detection circuits 2 of the present invention, and a The capacitor 14 , wherein the driving unit 10 is used to control the on/off of the switch unit 12 , and the switch unit 12 includes an upper arm switch element 121 and a lower arm switch element 122 . It should be noted that, in each of the switch units 12, there is an inductive connection node (SW1, SW2, . Connect the inductance 13.

As shown in FIG. 3 , the detection circuit 2 of the present invention is integrated in the DC-DC conversion device 1 to detect the connection state between the switch unit 12 and the inductance 13, so that the system can rely on the inductance 13 Whether it is connected to the inductance connection node of the switch unit 12 is used to determine whether to turn on the specified switch unit 12 to achieve the purpose of reducing power consumption. For example, as shown in FIG. 3 , the DC-DC conversion device 1 includes a multi-channel step-up-step-down power conversion circuit. However, in a feasible embodiment, the DC-DC conversion device 1 may also include a multi-channel step-up-step-down power conversion circuit. However, in a feasible embodiment, the DC-DC conversion device 1 may also include: a multi-channel step-down power conversion circuit, a multi-channel step-up power conversion circuit, or a multi-channel reverse voltage power conversion circuit.

FIG. 4 is a block diagram of a detection circuit of the present invention. As shown in FIG. 4 , the detection circuit 2 of the present invention includes: a first detection unit 21 , a second detection unit 22 and an electrical state judgment unit 23 . According to FIG. 3 and FIG. 4, the first detection unit 21 is coupled to an inductive connection node SW of the switch unit 12, and is coupled to an enable signal En and a clock signal Clock at the same time, so that according to the enable signal En and The clock signal Clock executes a first electrical state judgment operation on the inductive connection node SW. On the other hand, the second detection unit 22 is also coupled to the same inductive connection node SW, the enable signal En, and the clock signal Clock, so that according to the enable signal En and the clock signal Clock to perform a second electrical state judgment operation on the inductive connection node SW. Furthermore, the electrical state determination unit 23 is coupled to a first detection signal transmitted by the first detection unit 21 and a second detection signal transmitted by the second detection unit 22 . As shown in FIG. 4 , in one embodiment, the electrical state judging unit 23 is an AND gate, and has a first terminal coupled to the first detection signal, coupled to the second detection signal A second terminal and an output terminal, so as to generate a state indication signal for indicating an electrical connection state of the inductive connection node SW according to the first detection signal and the second detection signal. Therefore, the electrical connection state of the inductance connection node SW can be obtained from the following Table 1 (ie, the truth table of the AND gate).

FIG. 5 is a circuit topology diagram of the first detection unit shown in FIG. 4 . As shown in FIG. 4 and FIG. 5, in one embodiment, the first detection unit 21 includes: a first P-type MOSFET element MP1, a first resistor R1, a second resistor R2, a first capacitor C1, A first timer 211 , a first OR gate 212 , a first Schmitt trigger 213 , and a first latch 214 . According to FIG. 5, the source of the first P-type MOSFET element MP1 is coupled to an operating voltage V _DD , one end of the first resistor R1 is coupled to the drain of the first P-type MOSFET element MP1, and the second resistor R2 One end of the resistor R1 and the other end of the first resistor R1 form a first common point, and the first common point is coupled to the inductance connection node SW. In more detail, one end of the first capacitor C1 is coupled to the other end of the second resistor R2, and the other end is coupled to a ground. Moreover, the first timer 211 is coupled to the enable signal En and the clock signal Clock, so as to perform a timing operation according to the enable signal En and the clock signal Clock, and output a first timing signal.

As shown in FIG. 4 and FIG. 5, the first OR gate 212 has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the enable signal En, and the second input terminal The first timing signal is coupled, and the output terminal is coupled to the gate of the first P-type MOSFET element MP1. On the other hand, the first Schmitt trigger 213 has an input terminal and an output terminal, and the input terminal is coupled to a second common point between the second resistor R2 and the first capacitor C1. Moreover, the first latch 214 has a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the first Schmitt trigger 213 An output terminal, the second input terminal is coupled to the first timing signal, and the third input terminal is coupled to the enable signal En.

When the first detection unit 21 works normally, as shown in FIG. 5 , the initial level of the enable signal En is 0, so that the level of the first timing signal is reset to 0, and then the first P-type MOSFET is turned off. Element MP1. Further, when the level of the enable signal En rises to 1, the first P-type MOSFET element MP1 is turned on. At this time, if the electrical connection state of the inductance connection node SW is "normally connected" or "short-circuited to ground", the potential of the inductance connection node SW is 0, so that the output of the first Schmitt trigger 213 The level of the signal is 0. Further, after the first timer 211 finishes timing, the level of the first timing signal rises to 1. At this time, the level of the logic signal output by the first OR gate 212 is 1, thereby turning off the first P-type MOSFET element MP1. At the same time, the first latch 214 performs a latch operation on the output signal of the first Schmitt trigger 213 whose level is 0, and sends out a first detection signal. As shown in FIG. 5, the enable signal is transmitted to the first timer 211, the first OR gate 212 and the first latch 214 through a first inverter (or buffer) 21I1, and the The first detection signal has a level of 1 after being inverted by a second inverter (or buffer) 21I2.

On the contrary, if the electrical connection state of the inductance connection node SW is “floating”, the level of the output signal of the first Schmitt trigger 213 will be 1. Further, after the first timer 211 finishes timing, the level of the first timing signal rises to 1. At this time, the level of the logic signal output by the first OR gate 212 is 1, thereby turning off the first P-type MOSFET element MP1. At the same time, the first latch 214 performs a latch operation on the output signal of the first Schmitt trigger 213 whose level is 1, and sends out a first detection signal. As shown in FIG. 5 , the first detection signal has a level of 0 after being inverted by the second inverter 21I2 .

Moreover, if the electrical connection state of the inductance connection node SW is “coupled to high potential (input voltage VIN)”, the potential of the inductance connection node SW is 1, so that the output of the first Schmitt trigger 213 The level of the signal is 1. Further, after the first timer 211 finishes timing, the level of the first timing signal rises to 1. At this time, the level of the logic signal output by the first OR gate 212 is 1, thereby turning off the first P-type MOSFET element MP1. At the same time, the first latch 214 performs a latch operation on the output signal of the first Schmitt trigger 213 whose level is 1, and sends out a first detection signal. As shown in FIG. 5 , the first detection signal has a level of 0 after being inverted by the second inverter 21I2 .

FIG. 6 is a circuit topology diagram of the second detection unit shown in FIG. 4 . As shown in Figure 4 and Figure 6, in one embodiment, the second detection unit 22 includes: a second P-type MOSFET element MP2, a third resistor R3, a fourth resistor R4, a first N-type MOSFET The element MN1 , a second timer 221 , a second OR gate 222 , a second Schmitt trigger 223 , a signal delayer 224 , an AND gate 225 , and a second latch 226 . According to FIG. 6 , the source of the second P-type MOSFET MP2 is coupled to the operating voltage V _DD , and one end of the third resistor R3 is coupled to the drain of the second P-type MOSFET MP2 . Moreover, one end of the fourth resistor R4 and the other end of the third resistor R3 form a third common point, and the third common point is coupled to the inductance connection node SW.

In more detail, the drain of the first N-type MOSFET MN1 is coupled to the other end of the fourth resistor R4 , and the source is coupled to the ground. Moreover, the second timer 221 is coupled to the enable signal En and the clock signal Clock, so as to execute the timing operation according to the enable signal En and the clock signal Clock, and output a second timing signal. On the other hand, the second OR gate 222 has a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the enable signal En, and the second input terminal The terminal is coupled to the second timing signal, and the output terminal is coupled to the gate of the second P-type MOSFET element MP2. Further, as shown in FIG. 6, the second Schmitt trigger 223 has a first input terminal, a second input terminal and an output terminal, and the first input terminal is coupled to the fourth resistor R4 and A fourth common point between the drains of the first N-type MOSFET element MN1 is coupled to the second timing signal at the second input end.

As shown in FIG. 6 , the signal delayer 224 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the second Schmitt trigger 223 . In a feasible embodiment, the signal delayer 224 may be a buffer gate circuit (that is, a digital signal delay circuit) composed of at least one inverter (Inverter), a resistance-capacitance delay circuit (RC delay, that is, an analog The present invention is not particularly limited. In more detail, the AND gate 225 has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the output terminal of the signal delayer 224, and the second input terminal is coupled to Connect to the second timing signal. On the other hand, the second latch 226 has a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the output terminal of the AND gate 225, The second input terminal is coupled to the second timing signal, and the third input terminal is coupled to the working voltage V _DD .

When the second detection unit 22 works normally, as shown in FIG. 6 , the initial level of the enable signal En is 0, so that the level of the second timing signal is reset to 0. Since the enable signal En is transmitted to the second timer 221, the second OR gate 222 and the second latch 226 through a third inverter (or buffer) 22I3, and the second timing signal It is transmitted to the second Schmitt trigger 223 and the AND gate 225 through a fourth inverter 22I4. Therefore, the level of the output signal of the second latch 226 is 0, thereby turning off the second P-type MOSFET element MP2 and turning on the first N-type MOSFET element MN1. Further, when the level of the enable signal En rises to 1, the second P-type MOSFET element MP2 is turned on, and the first N-type MOSFET element MN1 is turned off. At this time, if the electrical connection state of the inductance connection node SW is "normal connection", the inductance connection node SW will have a potential of 1 due to the conduction of the second P-type MOSFET element MP2. Furthermore, as the inductor current gradually increases, the potential of the inductor connection node SW also gradually decreases. It is worth noting that before the inductance connection node SW falls below a threshold value, the high potential of the inductance connection node SW makes the output signal of the second Schmitt trigger 223 be 1. Therefore, before timing ends, the level of the second timing signal after inversion is 1, and at this moment, the level of the logic signal output by the AND gate 225 is 1, so that the second latch 226 is The working voltage V _DD performs a latch operation and sends out a second detection signal. As shown in FIG. 6 , the second detection signal has a level of 1 after being inverted by a fifth inverter 22I5 and a sixth inverter 22I6 .

It should be noted that after a set delay time (such as 100ns), the AND gate 225 The level of the output logic signal changes to 0. At the same time, after the second timer 221 finishes timing, the level of the inverted second timing signal rises to 1. At this time, the level of the logic signal output by the AND gate 225 is reversed back to 1 again, maintaining the level of the second detection signal at 1, and avoiding the winding of the inductive connection node SW in the later stage.

If the electrical connection state of the inductance connection node SW is “short to ground”, the level of the output signal of the second Schmitt trigger 223 is 0. Therefore, before the timing ends, the level of the second timing signal after inversion is 1, and at this time, the level of the logic signal output by the AND gate 225 is 0, so that the second latch 226 is not correct. The working voltage V _DD performs a latch operation and sends out a second detection signal with a level of 0. After the timing of the second timer 221 ends, the level of the inverted second timing signal rises to 1. At this time, the level of the logic signal output by the AND gate 225 is maintained at 1, and the level of the second detection signal is also maintained at 1, which avoids the winding of the inductive connection node SW in the later stage.

If the electrical connection state of the inductance connection node SW is “floating”, the level of the output signal of the second Schmitt trigger 223 will be 1. Before the timing ends, the level of the second timing signal after the inversion is 1, and at this moment, the level of the logic signal output by the AND gate 225 is 1, so that the second latch 226 can respond to the operating voltage V _DD performs a latch operation and sends out a second detection signal whose level is 1. As shown in FIG. 6 , the second detection signal has a level of 1 after being inverted by the fifth inverter 22I5 and the sixth inverter 22I6 . Further, after the timing of the second timer 221 ends, the level of the logic signal output by the AND gate 225 maintains 1, together with maintaining the level of the second detection signal as 1, which avoids the winding of the inductance connection node SW in the later stage. move.

Moreover, if the electrical connection state of the inductance connection node SW is “coupled to high potential (input voltage VIN)”, the potential of the inductance connection node SW is 1, so that the output of the second Schmitt trigger 223 The level of the signal is 1. Before the timing ends, the level of the second timing signal after the inversion is 1, and at this moment, the level of the logic signal output by the AND gate 225 is 1, so that the second latch 226 can respond to the operating voltage V _DD performs a latch operation and sends out a second detection signal whose level is 1. As shown in FIG. 6 , the second detection signal has a level of 1 after being inverted by the fifth inverter 22I5 and the sixth inverter 22I6 . Further, after the timing of the second timer 221 ends, the level of the logic signal output by the AND gate 225 maintains 1, together with maintaining the level of the second detection signal as 1, which avoids the winding of the inductance connection node SW in the later stage. move.

Thus, the above has completely and clearly described a detection circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a detection circuit that can be integrated in a DC-DC converter to detect the connection state between the switch unit and the inductor, so that the system can determine whether the inductor is connected to the inductor connection node or not. Deciding whether to turn on the designated switch unit to achieve the purpose of reducing power consumption.

(2) The present invention also provides a DC-DC converter, which is characterized in that it includes the detection circuit of the present invention as described above.

(3) The present invention also provides a power supply device, which is characterized in that it includes the DC-DC converter of the present invention as described above.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

10: Drive unit

12: switch unit

121: upper arm switch element

122: lower arm switch element

14: capacitance

2: Detection circuit

21: The first detection unit

22: The second detection unit

23: Electrical state judgment unit

Claims (10)

A detection circuit is applied in a DC-DC power converter 1 and includes: a first detection unit 21 coupled to an inductance connection node SW of a switch unit 12 of the DC-DC power converter 1 , and at the same time coupled to an enable signal En and a clock signal Clock, so as to perform a first electrical state judgment operation on the inductance connection node SW according to the enable signal En and the clock signal Clock; a second detection unit 22. Coupling the inductance connection node SW, the enable signal En, and the clock signal Clock, so as to perform a second electrical state judgment operation on the inductance connection node SW according to the enable signal En and the clock signal Clock; And an electrical state judging unit 23, which is coupled to a first detection signal transmitted by the first detection unit 21 and a second detection signal transmitted by the second detection unit 22, so that according to the first detection signal and the The second detection signal generates a state indication signal for representing an electrical connection state of the inductance connection node SW. The detection circuit as described in claim 1, wherein the electrical state judgment unit 23 is an AND gate, and has a first end coupled to the first detection signal, a second end coupled to the second detection signal terminal and an output terminal for transmitting the status indicating signal. The detection circuit as described in Claim 1, wherein the first detection unit 21 includes: a first P-type MOSFET element MP1, the source of which is coupled to an operating voltage V _DD ; a first resistor R1, one end of which is coupled to The drain of the first P-type MOSFET element MP1; a second resistor R2, one end of which and the other end of the first resistor R1 form a first common point, and the first common point is coupled to the inductive connection Node SW; a first capacitor C1, one end of which is coupled to the other end of the second resistor R2, and the other end is coupled to a ground; a first timer 211, coupled to the enable signal En and the clock Signal Clock, thereby performing a timing operation according to the enabling signal En and the clock signal Clock, and outputting a first timing signal; a first OR gate 212 having a first input terminal, a second input terminal and an output end, the first input end is coupled to the enable signal En, the second input end is coupled to the first timing signal, and the output end is coupled to the gate of the first P-type MOSFET element MP1; a first implementation The Mitte trigger 213 has an input terminal and an output terminal, the input terminal is coupled to a second common point between the second resistor R2 and the first capacitor C1; and a first latch 214 , has a first input end, a second input end, a third input end and an output end, the first input end is coupled to the output end of the first Schmitt trigger 213, the second input end The first timing signal is coupled, and the third input terminal is coupled to the enable signal En. The detection circuit as described in claim 3, wherein the second detection unit 22 includes: a second P-type MOSFET element MP2, the source of which is coupled to the operating voltage V _DD ; a third resistor R3, one end of which is coupled to The drain of the second P-type MOSFET element MP2; a fourth resistor R4, one end of which and the other end of the third resistor R3 form a third common point, and the third common point is coupled to the inductive connection node SW; a first N-type MOSFET element MN1, its drain coupled to the other end of the fourth resistor R4, and its source coupled to the ground terminal; a second timer 221 coupled to the enabling signal En and the clock signal Clock, so as to perform the timing operation according to the enabling signal En and the clock signal Clock, and output a second timing signal; a second OR gate 222 has a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the enable signal En, the second input terminal is coupled to the second timing signal, and the output terminal is coupled to the second P-type Gate of the MOSFET element MP2; a second Schmitt trigger 223 having a first input, a second input and an output, and the first input is coupled to the fourth resistor R4 and the fourth resistor R4 A fourth common point between the drains of the first N-type MOSFET element MN1, the second input end is coupled to the second timing signal; a signal delayer 224 has an input end and an output end, and the second input end is coupled to the second timing signal; The input terminal is coupled to the output terminal of the second Schmitt trigger 223; an AND gate 225 has a first input terminal, a second input terminal and an output terminal, and the first input terminal is coupled to the signal delay The output terminal of device 224, and the second input terminal is coupled to the second timing signal; and a second latch 214 has a first input terminal, a second input terminal, a third input terminal and a output terminal, the first input terminal is coupled to the output terminal of the AND gate 225, the second input terminal is coupled to the second timing signal, the third input terminal is coupled to the operating voltage V _DD , and the output terminal is coupled to connected to the third input end of the second OR gate. The detection circuit according to claim 4, wherein the signal delayer 224 is any one selected from the group consisting of a digital delay circuit, an analog delay circuit, a signal delay element, and a signal delay line. A DC-DC converter, including at least one drive unit, at least one switch unit, at least one inductor, and a capacitor; characterized in that, the DC-DC converter further includes at least one detection circuit, wherein the detection circuit It is coupled to an inductance connection node SW of the switch unit to detect an electrical connection state of the inductance connection node SW, and includes: a first detection unit 21, coupled to the inductance connection node SW, and coupled to the inductance connection node SW at the same time An enable signal En and a clock signal Clock, thereby performing a first electrical state judgment operation on the inductance connection node SW according to the enable signal En and the clock signal Clock; a second detection unit 22 coupled to the The inductance connection node SW, the enable signal En and the clock signal Clock, so as to perform a second electrical state judgment operation on the inductance connection node SW according to the enable signal En and the clock signal Clock; and an electrical state The judging unit 23 is coupled to a first detection signal transmitted by the first detection unit 21 and a second detection signal transmitted by the second detection unit 22, so as to determine according to the first detection signal and the second detection signal A status indication signal for indicating an electrical connection status of the inductance connection node SW is generated. The DC-DC converter as described in claim 6, wherein the electrical state judgment unit 23 is an AND gate, and has a first terminal coupled to the first detection signal, and a terminal coupled to the second detection signal A second terminal and an output terminal for transmitting the status indicating signal. The DC-DC converter as described in Claim 6, wherein the first detection unit 21 includes: a first P-type MOSFET element MP1, the source of which is coupled to an operating voltage V _DD ; a first resistor R1, which One end is coupled to the drain of the first P-type MOSFET element MP1; a second resistor R2, one end of which and the other end of the first resistor R1 form a first common point, and the first common point is coupled to the The inductance is connected to the node SW; a first capacitor C1, one end of which is coupled to the other end of the second resistor R2, and the other end is coupled to a ground end; a first timer 211, coupled to the enable signal En and the clock signal Clock, thereby performing a timing operation according to the enabling signal En and the clock signal Clock, and outputting a first timing signal; a first OR gate 212 having a first input terminal and a second input terminal and an output terminal, the first input terminal is coupled to the enable signal En, the second input terminal is coupled to the first timing signal, and the output terminal is coupled to the gate of the first P-type MOSFET element MP1; The first Schmitt trigger 213 has an input terminal and an output terminal, the input terminal is coupled to a second common contact point between the second resistor R2 and the first capacitor C1; a first latch The device 214 has a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the output terminal of the first Schmitt trigger 213, the second The input terminal is coupled to the first timing signal, and the third input terminal is coupled to the enable signal En. The DC-DC converter as described in Claim 8, wherein the second detection unit 22 includes: a second P-type MOSFET element MP2, the source of which is coupled to an operating voltage V _DD ; a third resistor R3, which One end is coupled to the drain of the second P-type MOSFET element MP2; a fourth resistor R4, one end of which and the other end of the third resistor R3 form a third common point, and the third common point is coupled to the The inductance connection node SW; a first N-type MOSFET element MN1, its drain is coupled to the other end of the fourth resistor R4, and its source is coupled to the ground terminal; a second timer 221, coupled to the Enabling signal En and the clock signal Clock, thereby performing the timing operation according to the enabling signal En and the clock signal Clock, and outputting a second timing signal; a second OR gate 222 having a first input terminal, A second input terminal, a third input terminal and an output terminal, the first input terminal is coupled to the enabling signal En, the second input terminal is coupled to the second timing signal, and the output terminal is coupled to the first Gates of two P-type MOSFET elements MP2; a second Schmitt trigger 223 having a first input terminal, a second input terminal and an output terminal, and the first input terminal is coupled to the fourth resistor A fourth common point between R4 and the drain of the first N-type MOSFET element MN1, the second input end is coupled to the second timing signal; a signal delayer 224 has an input end and an output end , and the input end is coupled to the output end of the second Schmitt trigger 223; an AND gate 225 has a first input end, a second input end and an output end, and the first input end is coupled to The output end of the signal delayer 224, and the second input end is coupled to the second timing signal; a second latch 226 has a first input end, a second input end, and a third input end and an output terminal, the first input terminal is coupled to the output terminal of the AND gate 225, the second input terminal is coupled to the second timing signal, the third input terminal is coupled to the operating voltage V _DD , and the output The terminal is coupled to the third input terminal of the second OR gate. A power supply device, characterized by comprising at least one DC-DC converter, and the DC-DC converter has the detection circuit as described in any one of Claim 1 to Claim 5.

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