TWI798809B - Semiconductor structure and the forming method thereof - Google Patents

Abstract

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region located in the first well region, the deep drain doped region has a first conductivity type.

Description

Semiconductor structure and method of forming same

The present invention relates to semiconductor structures, in particular to a lateral diffused metal oxide semiconductor (LDMOS) transistor element and a manufacturing method thereof.

A laterally diffused metal-oxide-semiconductor (LDMOS) device is a common power semiconductor device. Since the laterally diffused metal oxide semiconductor device has a horizontal structure, it is easy to manufacture and easy to integrate with the current semiconductor technology, thereby reducing the production cost. At the same time, it can withstand high breakdown voltage and has high output power, so it is widely used in power converters, power amplifiers, switches, rectifiers and other components.

However, since components such as LDMOS usually have a relatively large area, they also occupy nearly half of the area of the entire semiconductor structure. Therefore, how to improve the device structure so as to reduce the area of the LDMOS will be one of the research directions in the industry.

The present invention provides a semiconductor structure, including a substrate, the substrate has a first conductivity type, a laterally diffused metal-oxide-semiconductor (laterally diffused metal-oxide-semiconductor, LDMOS) element is located on the substrate, wherein the LDMOS element includes a first well area, located on the substrate, the first well area has a first conductivity type, a second well area, located within the first well area , and the upper and lower sides of a part of the second well area are surrounded by the first well area, wherein the second well area has a second conductivity type, wherein the second conductivity type is the same as the first conductivity type Complementary, a source doped region, located in the second well region, the source doped region has the first conductivity type, and a deep drain doped region, located in the first well region, deep The drain doped region has a first conductivity type.

The present invention further provides a method for forming a semiconductor structure, including providing a substrate having a first conductivity type, forming a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, Wherein the LDMOS device includes forming a first well region on the substrate, the first well region has a first conductivity type, forming a second well region within the first well region, and a part of the second well region The upper and lower sides of the well region are surrounded by the first well region, wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, forming a source doped region, located within the second well region, the source doped region has the first conductivity type, and a groove is formed in the first well region, and a deep drain doped region is formed in the groove The region is within the first well region, and the deep drain doped region has the first conductivity type.

The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well region, the required area of the deep drain doped region in this case is greatly reduced, so the total size of the device can also be reduced. area, to achieve the effect of miniaturization. this The outer deep drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.

1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure with reduced surface field

10: Base

12: The first well area

14: Barrier layer

16: Drift zone

20: Second well area

22: Insulation layer

24: Groove

25: photoresist layer

26: Polysilicon layer

27: Deep drain doped region

27A: Deep drain doped region

28:Gate structure

29: Gate dielectric layer

30: Gate conductive layer

32: Source doped region

34: shallow drain doped region

34A: Ion-doped area

36: Matrix area

40: metal silicide layer

42: Dielectric layer

44: Contact structure

44A: Contact structure

45: Cushion layer

46: Conductive layer

50: insulating layer

60: insulation layer

A: area

B: area

C: area

G: Spacing

P1: Doping step

FIG. 1 to FIG. 7 are schematic flow charts of forming a Reduced Surface Field Laterally Diffused MOSFET (RESURF LDMOS for short) according to the present invention.

FIG. 8 shows a schematic structure diagram of a RESURF LDMOS in which a deep drain doped region is formed by ion implantation and heating steps.

FIG. 9 shows a schematic structure diagram of a P-type RESURF LDMOS.

10-11 are schematic structural diagrams of RESURF LDMOS according to two other embodiments of the present invention, respectively.

12-14 are schematic structural diagrams of RESURF LDMOS according to another embodiment of the present invention.

In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, the composition of the present invention and the desired effects are described in detail. .

For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the up-down relationship of relative elements in the figures described in the text, those skilled in the art should understand that they refer to the relative positions of objects, so they can be reversed to present the same components, which should all belong to this specification. The scope of disclosure is described here first.

Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 illustrate the formation of a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS) according to the present invention. schematic diagram of the process. As shown in FIG. 1 , a substrate 10 is provided, and a first well region 12 and a second well region 20 are formed in the substrate 10 by, for example, doping. It is worth noting that the substrate 10 is, for example, a silicon substrate (single crystal silicon), and the first well region 12 is located on the substrate 10 and includes a first conductivity type (such as N type, and the first well region 12 may include a barrier layer 14 and a drift region 16, both of which are connected to each other and have the same conductivity type (for example, N type). The second well region 20 includes a second conductivity type (for example, P type) complementary to the first conductivity type. In this embodiment, the substrate 10 is, for example, a P-type substrate.

It is worth noting that, as shown in Figure 1, part of the second well area 20 penetrates laterally into the first well area 12, and the upper and lower sides of part of the second well area 20 are surrounded by the first well area 12, forming A structure in which the first well area 12 and the second well area 20 are interlaced. In other words, a part of the extension of the second well region 20 is located between the barrier layer 14 and the drift region 16 of the first well region 12 . In the actual manufacturing process, the barrier layer 14 may be formed on the substrate 10 first, and then the second well region 20 is formed, and then a part of the second well region 20 is doped with ions to form the drift region 16 .

In the subsequent steps, when the distribution structure of this well region is made into LDMOS elements, it is beneficial to form a depletion region at the N-P interface to block the passage of current, so that the LDMOS can withstand a large voltage difference when it is off. The area required by the LDMOS is smaller, so the above LDMOS can also be referred to as a Reduced Surface Field Laterally Diffused MOSFET (Resurf LDMOS for short). Other introductions about RESURF LDMOS have already been disclosed in some prior art (such as US Patent No. US 9484454), so details will not be repeated here.

The present invention is improved under the structure of RESURF LDMOS, so as to achieve the effect of reducing the element area and increasing the element quality. As shown in FIG. 2 , a patterned insulating layer 22 is formed on the surfaces of the first well region 12 and the second well region 20 . The insulating layer 22 is, for example, silicon oxide or silicon nitride, but not limited thereto. Then, using the insulating layer 22 as a mask, a groove 24 is formed in the first well region 12 . The groove 24 can be formed by, for example, patterning and etching, but is not limited thereto. In addition, in this embodiment, the width of the groove 24 is preferably less than 0.5 microns, and the depth is greater than 8 microns, but it is not limited thereto. In this embodiment, the width of the groove 24 is about 0.3 microns, and the depth is preferably larger than the interface between the barrier layer 14 and the second well region 20 .

Next, as shown in FIG. 3, a polysilicon layer 26 is formed to fill the groove 24, wherein the polysilicon layer 26 is, for example, a polysilicon layer with a high doping concentration, which can be formed by an in-situ doping process. It has a first conductivity type (such as N type). In this embodiment, the concentration of the polysilicon layer 26 is preferably greater than 1E18 cm ³ . The above concentration is higher than that of the doped region formed by ion implantation and heating steps in conventional steps.

Next, as shown in FIG. 4 , the redundant polysilicon layer 26 and the insulating layer 22 are removed by etching back or chemical mechanical polishing to expose the surfaces of the first well region 12 and the second well region 20 . Here, the remaining polysilicon layer 26 in the groove 24 can be defined as a deep drain doped region 27 , and its function will be described in the following paragraphs.

As shown in FIG. 5, a gate structure 28 is formed on the first well region 12 and the second well region 20, wherein the gate structure 28 includes a gate dielectric layer 29 and a gate conductive layer 30, wherein the gate The dielectric layer 29 has a thicker thickness above the drift region 16 and a thinner thickness near the junction of the first well region 12 and the second well region 20 on the surface. The above-mentioned gate structure 28 belongs to the known technology of RESURF LDMOS, and the rest The characteristics are not repeated.

Continuing to refer to FIG. 6, after the gate structure 28 is completed, at least a source (source) doped region 32 and a shallow well region 32 are formed in the first well region 12 and the second well region 14 by means of ion doping and heating steps, etc. Drain doped region 34 . The source doped region 32 and the shallow drain doped region 34 both contain the first conductivity type (for example, N type), and the shallow drain doped region 34 is connected to the above-mentioned deep drain doped region 27 . It is worth noting that since the source doped region 32 and the shallow drain doped region 34 are formed in the well region composed of single crystal silicon through the steps of ion doping and heating, their material is also single crystal silicon. And the material is different from the deep-drain doped region 27 . In addition, in this embodiment, the ion doping concentrations of the source doped region 32 and the shallow drain doped region 34 are, for example, greater than 1E20 cm ³ . In addition, in some embodiments, a body region (body) 36 may be additionally formed beside the source doped region 32, where the body region 36 is, for example, doped with a second conductivity type (such as P type). Miscellaneous area.

As shown in FIG. 7 , the metal silicide layer 40 can be selectively formed on the surfaces of the gate structure 28 , the first well region 12 and the second well region 20 . Then a dielectric layer 42 is formed to cover the above components, and a contact structure 44 is formed in the dielectric layer 42 , the contact structure is connected to the source doped region 32 and the shallow drain doped region 34 . In some embodiments, the metal silicide layer 40 may be omitted, or the metal silicide layer 40 may be formed under the contact structure 44 after the dielectric layer 42 is completed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, and the contact structure 44 may include a liner layer 45 made of, for example, titanium/titanium nitride, and a conductive layer 46, made of, for example, tungsten (W). Other details and manufacturing methods of the above-mentioned components belong to the known technology in the art, and will not be repeated here. So far, the RESURF LDMOS structure 1 described in the present invention has been completed. Since the first well region 12 of the RESURF LDMOS structure 1 in this embodiment is N-type, the RESURF LDMOS structure 1 in this embodiment can be defined as an N-type RESURF LDMOS structure.

In the RESURF LDMOS structure 1 of the present invention, when the gate structure 28 is closed, the source terminal and The drain terminal still has a potential difference. For example, the contact structure 44 above the drain terminal introduces a high voltage (for example, 100V), while the source terminal maintains a potential of 0. At this time, due to the high doping concentration and good conductivity of the deep drain doped region 27, Therefore the voltage conducted to the bottom is only slightly reduced. The voltage will make the first well region 12 maintain a high potential, and the second well region 20 maintain a low potential, so that the N-P interface located at the central part of the RESURF LDMOS structure 1 generates a depletion region. For example, regions A, B, and C in FIG. 7 are all regions where depletion regions may be generated. That is to say, when the gate structure 28 of the RESURF LDMOS structure 1 is turned off, in addition to the isolation caused by the closing of the channel region, the depletion region generated in the center can also further isolate the current, so that the RESURF LDMOS structure 1 can withstand high voltage operation mode .

In order to smoothly form the above-mentioned depletion region, it is preferable to make the depth of the deep-drain doped region deeper in the prior art, so that the voltage can be smoothly transmitted to the lower part close to the barrier layer 14 and the depletion region can be smoothly generated. FIG. 8 shows a schematic structure diagram of a RESURF LDMOS in which a deep drain doped region is formed by ion implantation and heating steps. In the conventional technology, the depth of the deep-drain doped region is increased by ion implantation and heating steps. However, the ions also diffuse toward the lateral direction while being heated, so the width of the deep-drain doped region in the conventional technology is relatively large. Large (such as the ion-doped region 34A in FIG. 8), this will lead to an excessively large area of the device, which is not conducive to the miniaturization of the device. For example, in the prior art, if the depth of the ion-doped region 34A is to reach 8 micrometers, its width will be diffused to about 12 micrometers. In addition, the doping concentration of the ion-doped region 34A is lower than that of the deep-drain doped region 27 of the present invention, so the conductivity is also lower than that of the deep-drain doped region 27 . When a high voltage (for example, 100V) is introduced from above the ion-doped region 34A, the voltage transmitted to the lower part of the ion-doped region 34A will drop even more, which is not conducive to the formation of a depletion region.

The main difference between the RESURF LDMOS structure 1 of the present invention and the RESURF LDMOS structure in the prior art is that a deep drain doped region 27 is formed to replace part of the ion doped region, and the deep drain doped region 27 is used to etch the groove 24 is formed by backfilling the polysilicon layer 26 . Among them, the width of the groove 24 The width can be much smaller than the width of the ion-doped region 34A in the above-mentioned conventional technology. Another feature is that the polysilicon layer 26 with higher doping concentration and better conductivity is filled in the groove 24, which can not only greatly reduce the device area (Because the width of the deep drain doped region 27 is small), and the conduction effect of the deep drain doped region 27 is better, so that the high voltage from the upper contact structure 44 can be successfully conducted to the deep drain doped region 27, it is further conducted into the first well area 12, so that the depletion area can be formed smoothly. In a word, the present invention has the advantages of reducing device area, improving device quality, and being compatible with existing manufacturing processes.

In the above-mentioned embodiments (Fig. 1 to Fig. 7), the N-type RESURF LDMOS structure is taken as an example, that is, the first well region 12 and the deep drain doped region 27 are N-type, and the second well region 20 is N-type. Type P. However, in other embodiments of the present invention, a P-type RESURF LDMOS structure can also be fabricated. As shown in FIG. 9, FIG. 9 shows a schematic structure diagram of a P-type RESURF LDMOS. Among them, the structures, materials and manufacturing methods of most components are the same as those of the above-mentioned first preferred embodiment and will not be described in detail. The doped region 27 , the source doped region 32 and the shallow drain doped region 34 are P-type, while the second well region 20 and the base region 36 are N-type. It should be noted that in this embodiment, the deep drain doped region 27 does not contact the second well region 20, and a distance G is maintained between the deep drain doped region 27 and the second well region 20 to avoid When an extremely high potential is introduced, a current punch through occurs between the deep drain doped region 27 with a higher doping concentration and the second well region 20 with a lower doping concentration, causing breakdown of the device. .

Likewise, in other embodiments of the present invention, in order to avoid lateral current breakdown, an insulating layer may be disposed beside or below the deep drain doped region 27 . Please refer to FIGS. 10-11. FIGS. 10-11 respectively illustrate the structural schematic diagrams of RESURF LDMOS according to two other embodiments of the present invention. As shown in FIG. 10 , in this embodiment, an insulating layer 50 is additionally formed beside the deep drain doped region 27 . The insulating layer 50 is, for example, silicon oxide or a polysilicon layer surrounded by silicon oxide. The depth of insulating layer 50 can be deeper than the drain The depth of the doped region 27 is deeper, and the insulating layer 50 is disposed in the substrate 10 next to the first well region 12. In some embodiments, deep trench isolation (DTI) can be used as the insulating layer 50 here. . The insulating layer 50 has the function of preventing the deep drain doped region 27 from breaking through the first well region 12 and affecting other adjacent components.

In another embodiment, as shown in FIG. 11 , in addition to the above-mentioned insulating layer 50 , part of the barrier layer 14 is replaced by another insulating layer 60 in this embodiment. The insulating layer 60 is, for example, silicon oxide. In some embodiments, a silicon on substrate (SOI) substrate may be used to replace the original silicon substrate to achieve the structure shown in FIG. 11 . In this embodiment, the insulating layer 60 can also prevent current breakdown in the longitudinal direction.

In other embodiments of the present invention, different LDMOSs can also be formed on the same substrate. For example, N-type RESURF LDMOS (structure shown in FIG. 7 ) and P-type RESURF LDMOS (structure shown in FIG. 9 ) can be formed together on different regions of the same substrate. This structure also falls within the scope of the present invention.

In the above embodiments, the polysilicon layer 26 with high doping concentration is filled in the groove 24 to form a polysilicon deep drain doped region 27 with a narrow width. In addition, in other embodiments of the present invention, a deep drain with a narrow width and sufficient depth can also be formed in the first well region 12 by doping or plasma implantation in the groove 24. The details of the doped region are shown in Figure 12 to Figure 14 below.

As shown in Figure 12, in this embodiment, after forming the groove 24 (continuing the steps in Figure 1 and Figure 2 of the first embodiment), a photoresist layer 25 is first formed to cover the first well region 12 and the second well region 20, and expose part of the first well region 12 and the second well region 20 at the same time, wherein the exposed region contains the groove 24, and the second well region 20 is intended to form source doping The location of the impurity region 32 . Next, proceed to A doping step P1 is to dope the area not covered by the photoresist layer 25. In this embodiment, the doping of high-concentration N-type ions is taken as an example, but in other embodiments of the present invention, it is also possible to dope High concentration of P-type ions, the present invention is not limited thereto. In addition, the groove 24 , the source doped region 32 , and the gate structure 28 can also be individually and independently doped with different masks, and the present invention is not limited thereto.

It is worth noting that the doping angle can be adjusted during the ion doping step P1 in this embodiment, for example, doping in an oblique direction, so that the doped ions can penetrate deep into the bottom surface and sidewall of the groove 24, A deep drain doped region 27A is formed on the bottom and sidewalls of the groove 24 . Different from the deep drain doped region 27 mentioned in the previous embodiments, the deep drain doped region 27A in this embodiment is formed on the periphery of the groove 24 of the first well region 12 by means of ion doping. , so it has a U-shaped cross-sectional profile, and the material of the deep drain doped region 27A is the same as that of the first well region 12, both of which are single crystal silicon. In addition, in this embodiment, while forming the deep drain doped region 27A, the source doped region 32 can also be formed in the second well region 20 at the same time, so the effect of saving steps can be achieved. In addition, the groove 24 can also be doped by plasma doping, and the present invention is not limited thereto.

Next, as shown in FIG. 13, the photoresist layer 25 is removed, and then a base region 36 is formed next to the source doped region 32, where the base region 36 is, for example, a P-type doped doped region formed by doping. district. Then a metal silicide layer 40 is formed, wherein the metal silicide layer 40 covers the surfaces of the gate structure 28 , the first well region 12 , the second well region 20 and the groove 24 (ie, the deep drain doped region 27A). In addition, the present invention may not form the metal silicide layer, or selectively form the metal silicide layer on the substrate, or the gate structure, or the inner surface of the groove, and the present invention is not limited thereto.

Then, as shown in FIG. 14 , a dielectric layer 42 and a contact structure 44 and a contact structure 44A are formed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, and the contact structure 44 and the contact structure 44A may It includes a liner layer 45 whose material is, for example, titanium/titanium nitride, and a conductive layer 46, whose material is, for example, tungsten (W). The steps of forming the base region 36 , the metal silicide layer 40 and the contact structures 44 , 44A are similar to those of the above-mentioned embodiments (refer to the description in FIG. 6 and FIG. 7 ), and will not be repeated here. It should be noted that the contact structure 44A in this embodiment is formed in the groove 24 , that is, formed on the deep drain doped region 27A. The contact structure 44A goes deep into the first well region 12 , that is, the bottom surface of the contact structure 44A is lower than the top surface of the first well region 12 , so it can effectively conduct current from other components above to below.

Based on the above-mentioned FIG. 12 to FIG. 14 , this embodiment forms the deep-drain doped region 27A in another way, which forms the deep-drain doped region in the groove by doping or ion implantation. The depth of the deep drain doped region is sufficient to conduct current from above to below. In another embodiment, the width of the deep drain doped region is also less than 0.5 micron, which also has the effect of saving space. In addition, this embodiment is also compatible with existing manufacturing processes. In addition, in this embodiment, an N-type RESURF LDMOS structure is fabricated as an example, but the type of dopant ions can be adjusted to fabricate a P-type RESURF LDMOS structure. That is, applying the method of doping ions in the grooves in this embodiment to the embodiment shown in FIG. 9 also falls within the scope of the present invention.

Based on the above description and drawings, the present invention provides a semiconductor structure, including a substrate 10, and a laterally diffused metal-oxide-semiconductor (LDMOS) device is located on the substrate 10, wherein the LDMOS device includes: a The first well area 12 is located on the substrate 10, the first well area 12 has a first conductivity type, a second well area 20 is located in the first well area 12, and a part of the second well area The upper and lower sides of the region 20 are surrounded by the first well region 12, wherein the second well region 20 has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, and a source doped impurity region 32, located in the second well region 20, the source doped region 32 has the first conductivity type, and a deep drain doped region (27 or 27A), located in the first well region 12 inside, deeply drawn The impurity region (27 or 27A) has the first conductivity type. In another embodiment, a width of the deep drain doped region ( 27 or 27A) is less than 0.5 microns.

The present invention further provides a method for forming a semiconductor structure, including providing a substrate 10, forming a laterally diffused metal-oxide-semiconductor (LDMOS) element on the substrate, wherein the step of forming the LDMOS element includes: forming a The first well area 12 is on the substrate 10, the first well area 12 has a first conductivity type, a second well area 20 is formed in the first well area 12, and the upper and lower sides of a part of the second well area 20 Surrounded by the first well region 12, the second well region 20 has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, forming a source doped region 32, located in the second well Within the region 20, the source doped region 32 has a first conductivity type, and a groove 24 is formed in the first well region 12, and a deep drain doped region (27 or 27A) is formed in the groove 24. ) within the first well region 12, the deep drain doped region (27 or 27A) has the first conductivity type. In another embodiment, a width of the deep drain doped region ( 27 or 27A) is less than 0.5 microns.

In some embodiments, the materials of the first well region 12 and the second well region 20 both include monocrystalline silicon, and the material of the deep drain doped region 27 includes polysilicon, and the shape of the deep drain doped region 27 includes A columnar body.

In some embodiments, the materials of the first well region 12, the second well region 20, and the deep-drain doped region 27A all include single crystal silicon, and the deep-drain doped region 27A has a U-shaped profile.

In some embodiments, it further includes a contact structure 44A located on the first well region 12 and electrically connected to the deep drain doped region 27A, wherein a bottom surface of the contact structure 44A is lower than the first well region 12 a top surface of the .

In some embodiments, a doping concentration of the deep-drain doped region 27 is higher than 1E18 cm ³ .

In some embodiments, it further includes a shallow drain doped region 34 located in the first well region 12 and connected to the deep drain doped region 27 .

In some embodiments, the first well region 12 includes a barrier layer 14 and a drift region 16 connected to each other, and part of the second well region 20 is located between the barrier layer 14 and the drift region 16 .

In some embodiments, at least one insulating structure 50 is further included, located beside the deep drain doped region 27 .

In some embodiments, the first conductivity type includes N type, and the second conductivity type includes P type.

In some embodiments, the first conductivity type includes P type, and the second conductivity type includes N type.

The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well area, the deep drain doped region in this case The required area of the miscellaneous area is greatly reduced, so the total area of the components can also be reduced to achieve the effect of miniaturization. In addition, the deep-drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure with reduced surface field

10: Base

12: The first well area

20: Second well area

27: Deep drain doped region

28:Gate structure

32: Source doped region

34: Deep drain doped region

36: Matrix area

40: metal silicide layer

42: Dielectric layer

44: Contact structure

45: Cushion layer

46: Conductive layer

A: area

B: area

C: area

Claims (19)

A semiconductor structure comprising: a substrate; a laterally diffused metal-oxide-semiconductor (LDMOS) element located on the substrate, wherein the laterally diffused metal-oxide-semiconductor element comprises: a first well region located on the substrate On the substrate, the first well area has a first conductivity type; a second well area is located within the first well area, and a part of the second well area is surrounded by the first well area on the upper and lower sides , wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; a source doped region is located in the second well region, and the source The doped region has the first conductivity type; and a deep drain doped region is located in the first well region, the deep drain doped region has the first conductivity type, and the deep drain doped region A bottom surface of the impurity region is lower than a bottom surface of the second well region, wherein the materials of the first well region and the second well region both include monocrystalline silicon, and the material of the deep drain doped region includes polysilicon, and The shape of the deep-drain doped region includes a columnar body. The semiconductor structure described in item 1 of the scope of the patent application, wherein the materials of the first well region, the second well region and the deep drain doped region all include single crystal silicon, and the deep drain doped region has a U-shaped profile. The semiconductor structure described in item 2 of the scope of the patent application further includes a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein a bottom surface of the contact structure is lower than the A top surface of the first well area. The semiconductor structure as described in claim 1, wherein a doping concentration of the deep drain doped region is higher than 1E18cm ³ . The semiconductor structure described in claim 1 further includes a shallow drain doped region located in the first well region and connected to the deep drain doped region. The semiconductor structure described in claim 1, wherein the first well region includes a barrier layer and a drift region connected to each other, and part of the second well region is located between the barrier layer and the drift region. The semiconductor structure described in claim 1 further includes at least one insulating structure located beside the deep drain doped region. The semiconductor structure described in item 1 of the scope of the patent application, wherein the first conductivity type includes N type, the second conductivity type includes P type, or the first conductivity type includes P type, and the second conductivity type Type includes N type. The semiconductor structure according to claim 1, wherein a width of the deep drain doped region is less than 0.5 microns. A method for forming a semiconductor structure, comprising: providing a substrate; forming a laterally diffused metal-oxide-semiconductor (LDMOS) element on the substrate, wherein the step of forming the laterally diffused metal-oxide-semiconductor element includes: Forming a first well area on the substrate, the first well area has a first conductivity type; forming a second well area within the first well area, and part of the upper and lower sides of the second well area Surrounded by the first well region, wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; forming a source doped region, located at the first In the second well region, the source doped region has the first conductivity type; a groove is formed in the first well region; and a deep drain doped region is formed in the groove in the first well region Within the well region, the deep drain doped region has the first conductivity type. The method described in claim 10 of the patent application, wherein the deep drain doped region is formed by filling a doped polysilicon layer in the groove, wherein the first well region and the second well region The material of the deep drain doped region includes polysilicon, and the shape of the deep drain doped region includes a columnar body. The method described in item 10 of the scope of patent application, wherein the deep drain doped region is formed by performing a doping step in the groove, wherein the first well region, the second well region and the deep The material of the drain doped region includes single crystal silicon, and the deep drain doped region has a U-shaped profile. The method described in claim 12 further includes forming a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein a bottom surface of the contact structure is lower than the A top surface of the first well area. The method according to claim 10, wherein a doping concentration of the deep-drain doped region is higher than 1E18cm ³ . The method described in claim 10 further includes forming a shallow drain doped region located within the first well region and connected to the deep drain doped region. The method described in claim 10, wherein the first well region includes a barrier layer and a drift region connected to each other, and part of the second well region is located between the barrier layer and the drift region. The method described in claim 10 further includes forming at least one insulating structure next to the deep drain doped region. The method described in item 10 of the scope of the patent application, wherein the first conductivity type includes N type, the second conductivity type includes P type, or the first conductivity type includes P type, and the second conductivity type States include N-type. The method according to claim 10, wherein a width of the deep-drain doped region is less than 0.5 microns.

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