TWI798877B - Circuit structure and manufacturing method thereof - Google Patents

Abstract

A circuit structure including a substrate, a first conductor and a second conductor is provided. The substrate has a first surface and a second surface opposite to the first surface. The first conductor is embedded in the substrate from the first surface of the substrate. The second conductor is embedded in the substrate from the second surface of the substrate. The second conductor is electrically connected to the first conductor.

Description

Circuit structure and its manufacturing method

The present invention relates to a circuit structure and its manufacturing method, and in particular to a circuit structure with a conductor embedded in a base material and its manufacturing method.

In a general circuit structure, it is necessary to electrically connect electronic components or circuits on both sides of the substrate through conductors (such as plated-through holes (PTH)) penetrating the substrate. However, in the conventional manufacturing process, the manufacturing method of the aforementioned conductor is relatively complicated and/or the manufacturing cost is relatively high.

The invention provides a circuit structure and a manufacturing method thereof, which are relatively simple and can have good quality.

The circuit structure of the present invention includes a substrate, a first conductor and a second conductor. The substrate has a first surface and a second surface opposite to the first surface. The first conductor is embedded in the substrate from the first surface of the substrate. The second conductor is embedded in the substrate from the second surface of the substrate. The second conductor is electrically connected to the first conductor.

The manufacturing method of the circuit structure of the present invention comprises the following steps: providing a base material, which has a first surface and a second surface opposite to the first surface; forming a first blind hole from the first surface of the base material; forming a hole filled in the second A first conductor of a blind hole; forming a second blind hole from the second surface of the base material, and the second blind hole exposes part of the first conductor; and forming a second conductor filled in the second blind hole, and the second blind hole A conductor is electrically connected with the second conductor.

Based on the above, the circuit structure and manufacturing method of the present invention are relatively simple and can have good quality.

The contents of the following examples are illustrative and not limiting. Also, descriptions of well-known devices, methods and materials may be omitted so as not to obscure the description of the various principles of the invention. Directional terms (eg, up, down, top, bottom) used herein refer only to the pictorial usage or corresponding idiom and are not intended to imply absolute orientation. In addition, unless the content clearly indicates otherwise, the singular forms "a", "an", "the" or forms not expressly expressing a quantity may include one or a plurality of forms, ie, include "at least one".

In some drawings, for the sake of clarity, some elements or film layers may be enlarged, reduced or omitted. Similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions thereof are omitted. It will be apparent to those skilled in the art to which this invention pertains that, from the context of the embodiments and the corresponding illustrations, the invention may be practiced in other embodiments that depart from the specific details disclosed herein.

Referring to FIG. 1A , a substrate 130 is provided. The substrate 130 has a first surface 130a and a second surface 130b opposite to the first surface 130a.

In this embodiment, the substrate 130 may include a glass substrate. In one embodiment, the substrate 130 may be a homogeneous material, and the aforementioned homogeneous material cannot be separated into different components by mechanical methods (such as crushing, shearing, cutting, sawing, grinding, etc.). single material. In other words, the substrate 130 may not have an interface formed by different materials or different processes (eg, adhesion). In one embodiment, the substrate 130 is a glass substrate.

In an unillustrated embodiment, there may be corresponding films, layers and/or elements on the first surface 130a or on the second surface 130b (such as: the lower part in the drawings) of the substrate 130, but the present invention does not limited to this. For example, the substrate 130 may have a patterned or unpatterned insulating layer, conductive layer and/or semiconductor layer on the first surface 130a or the second surface 130b.

Referring to FIGS. 1A-1B , a first blind hole 131 is formed from a first surface 130 a of a substrate 130 . The depth 131h of the first blind hole 131 may be about 30% to 70% of the thickness 130h of the substrate 130 . In addition, in FIG. 1B , only one first blind hole 131 is shown as an example, but the number, shape (such as: the opening shape of the blind hole 131 ) and/or size (such as : the opening size of the blind hole 131) is not limited.

In one embodiment, the first blind hole 131 may be formed by laser ablation. Compared with other etching methods, the laser ablation method is simpler and/or can be preferably changed. For example, laser ablation causes less damage to etched or drilled objects (e.g., the same or similar to the substrate 130) than conventional mechanical drilling, corrosion drilling, or other similar contact drilling. objects) deform; and/or less likely to damage films, layers and/or elements located on etched or drilled objects.

In one embodiment, in the aforementioned laser ablation method, the depth of the first blind hole 131 can be adjusted correspondingly by adjusting the focus of the laser light.

In one embodiment, compared with other methods (such as etching), laser ablation may generate relatively less waste (eg, waste liquid and/or exhaust gas). Therefore, waste disposal costs may be lower and/or more eco-friendly.

In an embodiment, in the aforementioned laser ablation method, the time domain pulse width (time domain pulse width; may be referred to as: pulse width) of the laser light may be femtosecond (femtosecond; fs). Compared with ordinary lasers, femtosecond lasers have shorter pulse widths, so they can obtain extremely high peak power (that is, single pulse energy/pulse width) with lower pulse energy.

In an embodiment, in the aforementioned laser ablation method, the major peak of the laser light may be located in the infrared region. In one embodiment, an infrared laser of appropriate energy may be suitable for melting and/or vaporizing glass material. In this way, the substrate 130 including the glass substrate can be adapted to form corresponding blind holes by infrared laser.

In one embodiment, compared with other methods, in the laser ablation method by infrared femtosecond laser, the structure of the first blind hole 131 formed is steeper and/or cleaner (for example: the first blind hole 131 A blind hole 131 may have a higher aspect ratio, the sidewall 131s of the first blind hole 131 may be flatter, and/or the interior of the first blind hole 131 may have less protrusions and/or residues) .

Referring to FIG. 1B to FIG. 1F , the first conductor 110 (marked in FIG. 1F ) filled in the first blind hole 131 is formed. The first conductor 110 may be formed as follows.

Referring to FIG. 1B to FIG. 1C , on the substrate 130 having the first blind hole 131 , a first conductive layer 119 is formed, and the first conductive layer 119 may further fill the first blind hole 131 . In one embodiment, the first conductive layer 119 can be completely formed on the substrate 130 .

In one embodiment, the first conductive layer 119 is, for example, a seed layer formed by sputtering. Common seed layers may include titanium layers and/or copper layers. However, the actual material of the seed layer depends on the conductive material to be filled into the first blind hole 131 later, which is not limited in the present invention.

Referring to FIG. 1C to FIG. 1D , a first photoresist layer 162 is formed on the first conductive layer 119 , and the first photoresist layer 162 covers part of the first conductive layer 119 . The first photoresist layer 162 can be formed by a photolithography process. The first photoresist layer 162 has a plurality of openings corresponding to the first blind holes 131 to expose a portion of the first conductive layer 119 located in and/or above the first blind holes 131 .

It should be noted that, according to design requirements, in other regions not shown in FIG. 1D , the first photoresist layer 162 may have other openings. Moreover, the aforementioned openings are not limited to correspond to blind holes that are the same as or similar to the first blind holes 131 .

Referring to FIGS. 1D to 1E , after forming the first photoresist layer 162 , a second conductive layer 112 is formed on the first conductive layer 119 exposed by the opening.

In an embodiment, the second conductive layer 112 may be formed on the first conductive layer 119 by electroplating. The material of the second conductive layer 112 may include copper, but the invention is not limited thereto.

Referring to FIGS. 1E to 1F , after the formation of the second conductive layer 112 , the first photoresist layer 162 (indicated in FIG. 1E ) is removed. For example, the first photoresist layer 162 can be removed by plasma ashing or etching, but the invention is not limited thereto.

Please continue to refer to FIG. 1E to FIG. 1F , after removing the first photoresist layer 162, use the second conductive layer 112 as a mask to remove the part of the first conductive layer 119 not covered by the second conductive layer 112 (marked in Figure 1E). For example, a part of the first conductive layer 111 can be removed by wet etching to form the first conductive layer 111 having the same or similar pattern as the second conductive layer 112 (marked in FIG. 1F ), but the present invention Not limited to this.

In one embodiment, during the process of removing part of the first conductive layer 119 , part of the second conductive layer 112 may also be slightly removed.

Please continue to refer to FIG. 1F , in this embodiment, the first conductive layer 111 and the second conductive layer 112 having the same or similar pattern can constitute the first conductor 110 .

Please continue to refer to FIG. 1F to FIG. 1G , the second blind hole 132 is formed from the second surface 130 b of the substrate 130 . The second blind hole 132 exposes part of the first conductor 110 . Specifically, the second blind hole 132 exposes part of the bottom surface of the first conductor 110 (that is, the surface of the first conductor 110 farthest from the first surface 130a; or, the surface of the first conductor 110 closest to the second surface 130b) . For example, the second blind hole 132 exposes part of the first conductive layer 111 .

For example, the structure shown in FIG. 1F can be flipped upside down, and then, the second blind hole 132 can be correspondingly formed by the same or similar formation method as the first blind hole 131 .

In one embodiment, since the substrate 130 is a glass substrate 130, and the material of the first conductor 110 includes metal. Therefore, the step of forming the second blind hole 132 can be relatively simple. For example, after the structure shown in FIG. 1F is turned upside down, viewed from the direction from the second surface 130b to the first surface 130a (that is, the substrate 130 ), compared with other regions, corresponding to the first The color of the conductor 110 may be darker and/or the transmittance of visible light may be lower. In this way, before forming the second blind hole 132 , it is easier to perform alignment or identification.

In one embodiment, the area of the bottom of the second blind hole 132 may be smaller than the area of the bottom surface of the first conductor 110, and the projection of the bottom of the second blind hole 132 on the first surface 130a and/or the second surface 130b The range may be located within the projection range of the bottom surface of the first conductor 110 on the first surface 130a and/or the second surface 130b. In this way, the second blind hole 132 can be formed more easily, and/or have a better process window.

In this embodiment, during the process of forming the second blind hole 132 , part of the first conductor 110 may be slightly removed. For example, part of the first conductive layer 111 may be slightly removed.

Referring to FIG. 1G to FIG. 1H , the second conductor 120 filled in the second blind hole 132 can be formed by the same or similar formation method as the first conductor 110 . For example, the third conductive layer 121 and the fourth conductive layer 122 having the same or similar pattern can constitute the second conductor 120 embedded in the substrate 130 from the second surface 130 b of the substrate 130 . The material or formation method of the third conductive layer 121 may be the same or similar to that of the first conductive layer 111 , and/or the material or formation method of the fourth conductive layer 122 may be the same or similar to that of the second conductive layer 112 .

After the above-mentioned manufacturing process, the fabrication of the circuit structure 100 of this embodiment can be substantially completed.

1H and 1I are partial cross-sectional schematic diagrams of a circuit structure according to the first embodiment of the present invention. For example, FIG. 1I may be an enlarged view corresponding to the region R1 in FIG. 1H .

Referring to FIG. 1H and FIG. 1I , the wiring structure 100 includes a substrate 130 , a first conductor 110 and a second conductor 120 . The substrate 130 has a first surface 130a and a second surface 130b opposite to the first surface 130a. The first conductor 110 is embedded in the substrate 130 from the first surface 130 a of the substrate 130 . The second conductor 120 is embedded in the substrate 130 from the second surface 130 b of the substrate 130 . The second conductor 120 is electrically connected to the first conductor 110 .

In this embodiment, the first conductor 110 is in contact with the second conductor 120 and has a first contact interface S1.

In this embodiment, the manufacturing method of the circuit structure 100 includes: after forming the first conductor 110, forming a second blind hole 132 corresponding to and exposing part of the first conductor 110 (marked in FIG. 1F ), and then forming at least The first conductor 120 inside the second blind hole 132 . Moreover, the second blind hole 132 can be formed by infrared laser ablation and/or vaporization of the substrate 130 including the glass substrate. Therefore, during the process of forming the second blind hole 132 , there may be some slightly melted and/or vaporized glass material adhering to part of the bottom surface of the first conductor 110 . Of course, the above-mentioned material adhered to the part of the bottom surface of the first conductor 110 is basically quite small and/or quite small in size, and may not affect the electrical properties between the first conductor 110 and the second conductor 120. Has a substantial impact and/or is difficult to observe. However, it is still possible to infer its presence by means of elemental analysis (eg, Energy-dispersive X-ray spectroscopy (EDS/EDX), but not limited to).

For example, taking FIG. 1I as an example, the substrate 130 may include a specific element (eg, silicon contained in glass); and the first conductor 110 and the first conductor 120 basically do not include the aforementioned specific element. And, compared with a region R2 including the first contact interface S1, in other regions away from the first contact interface S1 and the substrate 130 (such as: the region R3 located in the first conductor 110 and/or located in the second conductor 120 In the region R4 within ), the signal of the aforementioned specific element is weaker (ie, the concentration is lower).

For another example, taking FIG. 1I as an example, in the aforementioned region R2, the signal of the aforementioned specific element may be measured (that is, including the aforementioned specific element); and in the aforementioned region R3 and/or region R4, the aforementioned Signals for specific elements may be below the detection limit (ie, do not contain the aforementioned specific elements).

In this embodiment, the first conductor 110 is in contact with the substrate 130 and has a second contact interface S2, and the surface roughness (surface roughness; may be referred to as: roughness) of the first contact interface S1 is different from that of the second contact interface Roughness of S2. For example, as shown in FIG. 1I , the roughness of the first contact interface S1 is greater than the roughness of the second contact interface S2 .

In this embodiment, the second conductor 120 is in contact with the substrate 130 and has a third contact interface S3, and the roughness of the first contact interface S1 is different from the roughness of the third contact interface S3. For example, as shown in FIG. 1I , the roughness of the first contact interface S1 is greater than the roughness of the second contact interface S2 .

In this embodiment, the projected area of the first contact interface S1 on the first surface 130a and/or the second surface 130b is less than or equal to the projected area of the first conductor 110 on the first surface 130a and/or the second surface 130b . For example, the projected area of the first contact interface S1 on the first surface 130a and/or the second surface 130b is smaller than the projected area of the first conductor 110 on the first surface 130a and/or the second surface 130b.

In this embodiment, the second conductor 120 may be further embedded in the first conductor 110 . For example, the second conductor 120 can be further embedded in the first conductive layer 111 of the first conductor 110 .

FIG. 2 is a schematic partial cross-sectional view of a circuit structure according to a second embodiment of the present invention. The manufacturing method of the wiring structure 200 of this embodiment is similar to the manufacturing method of the wiring structure 100 of the previous embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions thereof are omitted. For example, FIG. 2 may be a partial cross-sectional schematic diagram similar to the region R1 in FIG. 1H .

Referring to FIG. 2 , the wiring structure 200 includes a substrate 130 , a first conductor 210 and a second conductor 120 . The first conductor 210 is embedded into the substrate 130 from the first surface (not directly shown, but may be the same as the first surface 130a of the foregoing embodiment) of the substrate 130 . The second conductor 120 is electrically connected to the first conductor 210 . The first conductor 210 may include a first conductive layer 211 and a second conductive layer 212 . The first conductive layer 211 may be formed in the same or similar manner as the aforementioned first conductive layer 111 , and/or the second conductive layer 212 may be formed in the same or similar manner as the aforementioned second conductive layer 112 .

In this embodiment, the second conductor 120 may penetrate a part of the first conductive layer 211 of the first conductor 210 and be further embedded in the second conductive layer 212 of the first conductor 210 .

In this embodiment, during the process of forming the second blind hole (such as the aforementioned second blind hole 132 ), part of the first conductive layer 211 may be penetrated, and part of the second conductive layer 212 may be slightly shifted. remove.

FIG. 3 is a schematic partial cross-sectional view of a circuit structure according to a third embodiment of the present invention. The manufacturing method of the wiring structure 300 in this embodiment is similar to the manufacturing method of the wiring structure 100 in the foregoing embodiments, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions thereof are omitted.

Referring to FIG. 3 , the wiring structure 300 includes a substrate 130 , a first conductor 110 and a second conductor 320 . The second conductor 320 is embedded in the substrate 130 from the second surface 130 b of the substrate 130 . The second conductor 320 is electrically connected to the first conductor 110 .

In this embodiment, the second conductor 320 may be a single layer structure.

In one embodiment, the second conductor 320 may be formed by screen printing.

FIG. 4 is a schematic partial cross-sectional view of a circuit structure according to a fourth embodiment of the present invention. The manufacturing method of the wiring structure 400 in this embodiment is similar to the manufacturing method of the wiring structure 100 in the foregoing embodiments, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions thereof are omitted.

Referring to FIG. 4 , the circuit structure 400 includes a substrate 130 , a first conductor 410 and a second conductor 120 . The first conductor 410 is embedded in the substrate 130 from the first surface 130 a of the substrate 130 . The second conductor 120 is electrically connected to the first conductor 410 .

In this embodiment, the first conductor 410 may be a single-layer structure.

In one embodiment, the first conductor 410 may be formed by screen printing.

FIG. 5 is a schematic partial cross-sectional view of a circuit structure according to a fifth embodiment of the present invention. The manufacturing method of the wiring structure 500 of this embodiment is similar to the manufacturing method of the wiring structure 100 of the previous embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions thereof are omitted.

Referring to FIG. 5 , the wiring structure 500 includes a substrate 130 , a first conductor 110 and a second conductor 520 . The second conductor 520 is embedded in the substrate 130 from the second surface 130 b of the substrate 130 . The second conductor 520 is electrically connected to the first conductor 110 . The second conductor 520 may include a third conductive layer 521 and a fourth conductive layer 522 . The third conductive layer 521 may be formed in the same or similar manner as the aforementioned third conductive layer 121 , and/or the fourth conductive layer 522 may be formed in the same or similar manner as the aforementioned fourth conductive layer 122 .

In this embodiment, the first conductor 110 is in contact with the second conductor 520 and has a first contact interface S1. The projected area of the first contact interface S1 on the first surface 130a and/or the second surface 130b is substantially equal to the projected area of the first conductor 110 on the first surface 130a and/or the second surface 130b.

To sum up, the circuit structure and manufacturing method of the present invention are relatively simple and can have good quality.

100, 200, 300, 400, 500: line structure 110, 210, 410: the first conductor 111, 119, 211: the first conductive layer 112, 212: the second conductive layer 120, 320, 520: second conductor 121, 521: the third conductive layer 122, 522: the fourth conductive layer 130: Substrate 130a: first surface 130b: second surface 130h: Thickness 131: The first blind hole 131h: Depth 131s: side wall 132: Second blind hole 162: photoresist layer R1, R2, R3, R4: Regions S1: first contact interface S2: Second contact interface S3: The third contact interface

1A to 1H are partial cross-sectional schematic diagrams of a partial manufacturing method of a circuit structure according to a first embodiment of the present invention. FIG. 1I is a schematic partial cross-sectional view of a circuit structure according to the first embodiment of the present invention. FIG. 2 is a schematic partial cross-sectional view of a circuit structure according to a second embodiment of the present invention. FIG. 3 is a schematic partial cross-sectional view of a circuit structure according to a third embodiment of the present invention. FIG. 4 is a schematic partial cross-sectional view of a circuit structure according to a fourth embodiment of the present invention. FIG. 5 is a schematic partial cross-sectional view of a circuit structure according to a fifth embodiment of the present invention.

100: Line structure

110: first conductor

111: the first conductive layer

112: second conductive layer

120: second conductor

121: the third conductive layer

122: The fourth conductive layer

130: Substrate

130a: first surface

130b: second surface

R1: Region

Claims (11)

A wiring structure, comprising: a base material having a first surface and a second surface opposite to the first surface; a first conductor embedded into the base material from the first surface of the base material; and a first Two conductors are embedded in the base material from the second surface of the base material and are electrically connected with the first conductor, wherein the second conductor is further embedded in the first conductor. The circuit structure according to claim 1, wherein the substrate is a glass substrate. The wiring structure as claimed in claim 1, wherein the first conductor is in contact with the second conductor and has a first contact interface. The circuit structure according to claim 3, wherein the first conductor is in contact with the substrate and has a second contact interface, and the roughness of the first contact interface is different from the roughness of the second contact interface. The circuit structure according to claim 3, wherein the second conductor is in contact with the substrate and has a third contact interface, and the roughness of the first contact interface is different from the roughness of the third contact interface. The circuit structure according to claim 3, wherein the projected area of the first contact interface on the first surface and/or the second surface is smaller than or equal to that of the first conductor on the first surface and/or the second surface The projected area on the surface. The circuit structure according to claim 1, wherein the first conductor includes a first conductive layer and a second conductive layer covering the first conductive layer. The circuit structure according to claim 1, wherein the second conductor includes a third conductive layer and a fourth conductive layer covering the third conductive layer. A method for manufacturing a circuit structure, comprising: providing a substrate having a first surface and a second surface opposite to the first surface; forming a first blind hole from the first surface of the substrate; forming filling a first conductor in the first blind hole; forming a second blind hole from the second surface of the substrate, and exposing part of the first conductor in the second blind hole; and forming filling in A second conductor of the second blind hole, and the first conductor is electrically connected to the second conductor, wherein the second conductor is further embedded in the first conductor. The method for manufacturing a circuit structure as claimed in claim 9, wherein the substrate is a glass substrate. The manufacturing method of the circuit structure according to claim 9, wherein the first blind hole and the second blind hole are formed by laser ablation.

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