TWI797889B - Low power consumption source driver and input stage comparator control method thereof - Google Patents

Abstract

A source driver is disclosed, including an input stage comparator, a plurality of output stage registers, and a control circuit. The input stage comparator receives a clock signal and a screen signal, and the input stage comparator generates a voltage swing signal according to the clock signal and the screen signal. Each output stage register is connected with the input stage comparator, and each output stage register generates a data signal according to the received voltage swing signal, and stores the data signal in a line latch. When the data signal of each the line latch is stored, the control circuit outputs a control signal to turn off the input stage comparator, and the source driver outputs a trigger signal to the next source driver connected in series.

Description

Low power consumption source driver and its input stage comparator control method

The present invention relates to a source driver chip, in particular, the present invention relates to a source driver chip with low power consumption

The source driver (source driver) is applied to the liquid crystal display, the main function is to transmit the voltage to the thin film transistor element of the panel (panel), to control the rotation angle of the liquid crystal to achieve the purpose of color display, the large size of the liquid crystal display has a large area, When driving, multiple source drivers (cascaded) are required for use.

However, when the number of source drivers connected in series increases, the power consumption will also increase. In order to enable the input stage circuit to receive high-speed input signals and quickly convert them into voltage swing signals between the power supply voltage and the ground voltage, In order to provide the internal circuit of the next stage, the bias current consumed by the comparator will account for a considerable proportion of the power consumption of the power supply voltage.

In order to solve the above known technical problems, an object of an embodiment of the present invention is to provide a source driver with low power consumption, which reduces the bias current of the comparator in the input stage circuit, so as to reduce the overall source driver operating time. Power consumption.

Another object of the embodiments of the present invention is to provide a method for controlling an input-stage comparator, which turns off the bias current of the input-stage comparator in the source driver that completes the data input, so as to reduce the excess power when the overall source driver operates consume.

According to an embodiment of the present invention, a source driver is provided, including an input-stage comparator, a plurality of output-stage registers, and a control circuit. The input-level comparator receives the clock signal and the frame signal, and the input-level comparator generates a voltage swing signal according to the clock signal and the frame signal. Each output-stage register is connected to the input-stage comparator, and each output-stage register generates a data signal according to the received voltage swing signal, wherein the data signal is stored in the linear latch. When the data signals of each linear latch are stored, the control circuit outputs a control signal to turn off the input stage comparator, and the source driver outputs a trigger signal to the next source driver connected in series.

According to an embodiment of the present invention, a method for controlling an input-stage comparator is provided, which is suitable for a source driver and at least includes the following steps.

Input the clock signal and picture signal to the input stage comparator of the source driver. When the source driver finishes inputting data, a control signal and a trigger signal are generated, and the control signal turns off the input stage comparator of the source driver. The trigger signal is input to the serially connected source driver for data input.

Compared with the prior art, in the source driver of the embodiment of the present invention, after the source driver finishes writing and storing the data signal, the source driver will send a control signal to turn off the internal input stage comparator, Then, write and store the data signal of the next source driver. Therefore, when the next source driver writes and stores the data signal, the input stage comparator in the source driver that has completed the writing and storing of the data signal will not have power consumption caused by additional bias current.

In the accompanying drawings, the dimensions of various layers, films, panels, regions, etc., may not be drawn to scale for clarity. Throughout the specification, the same reference numerals refer to the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Moreover, "electrically connected" or "coupled" means that other elements exist between two elements.

Please refer to FIG. 1 , which is a schematic diagram of source drivers connected in series. As shown in the figure, when a large-sized display panel is used, it usually requires multiple source drivers to be used in series, such as source driver 10-1, source driver 10-2, source driver 10-3 to source driver 10-m and so on. Specifically, the source driver 10-1 latches and reads the picture data and clock signal sent by the circuit in a timing sequence, and then reads the picture data into an analog signal by a digital-to-analog converter, and then converts it by an output circuit. Into the impedance, supply the data line of the liquid crystal display.

Please refer to FIG. 2 , which is a schematic diagram of the structure of the source driver. As shown in the figure, the source driver chip 10-1 may include a shift register (Shift Register) 300, a linear latch (Line Latch) 400, a level shifter (Level Shift) 500, a digital-to-analog converter ( Digital to Analog Converter) 600, and output buffer (Output Buffer) and so on. The input stage comparator 100 and the output stage register 200 are also required to transmit the signal to the shift register 300 . It should be noted that, for the convenience of illustration, all the detailed structures in the source driver chip 10 - 1 are not shown in FIG. 2 .

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

According to an embodiment of the present invention, the source driver 10-1 includes an input stage comparator 100, a plurality of output stage registers 200, a plurality of shift registers 300, a plurality of linear latches 400, and a control circuit 160 (will be further described later in FIG. 6A ). The input-stage comparator 100 receives the clock signal 110 and the frame signal 120 , and the input-stage comparator 100 generates a voltage swing signal 150 - 0 according to the clock signal 110 and the frame signal 120 (as shown in FIG. 3 ). Each output stage register 200 is connected to the input stage comparator 100, and each output stage register 200 generates a data signal 210 according to the received voltage swing signal 150-0, and stores the data signal 210 in a linear latch device 400, and pass the data signal 210 on to the subsequent circuit. When the data signal 210 of each linear latch 400 is stored, the control circuit 160 outputs a control signal to turn off the input stage comparator 100, and the source driver 10-1 outputs a trigger signal to the next source driver 10 connected in series. -2.

Please refer to FIG. 3 , which is a structural diagram of an input-stage comparator and an output-stage register. As shown, the input stage comparator 100 may have a comparator 140 corresponding to the input clock signal 110 and a minimum low voltage differential signal receiver 130 corresponding to the input frame signal 120 . The minimum low voltage differential signal receiver 130 has a frame signal input terminal corresponding to the number of bits of each frame signal 120 , and the output terminal of the minimum low voltage differential signal receiver 130 is connected to the corresponding output stage register 200 . The comparator 140 has a clock signal input terminal and a clock signal output terminal.

Please refer to FIG. 4 , which is a schematic diagram of the structure of the input stage comparator. As shown in the figure, the input-stage comparator 100 can be implemented by the following elements. The input-stage comparator 100 can include a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, and a first N-type transistor MN2. Two P-type transistors MP2.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The drain of the first N-type transistor MN1 is connected to the power supply voltage VDD through the first load L1. The drain of the second N-type transistor MN2 is connected to the power supply voltage VDD through the second load L2, wherein the source of the first N-type transistor MN1 and the source and ground terminal of the second N-type transistor MN2 (that is, the ground voltage GND) has a first bias current In, and a first node V1 for comparing voltages is provided between the first N-type transistor MN1 and the first load L1, and the second N-type transistor MN2 and the second load L2 There is a second node V2 between them for comparing voltages.

The drain of the first P-type transistor MP1 is connected to the ground terminal through the third load L3, wherein the gate of the first N-type transistor MN1 and the gate of the first P-type transistor MP1 receive a minimum low voltage differential signal (Mini The positive-phase signal of Low Voltage Differential Signaling, LVDS), that is, the positive-phase clock signal LCLK+ and the normal-phase picture signal LVn+.

The drain of the second P-type transistor MP2 is connected to the ground terminal through the fourth load L4, wherein the gate of the second N-type transistor MN2 and the gate of the second P-type transistor MP2 receive the negative signal of the minimum low voltage differential signal. The phase signal, that is, the negative phase clock signal LCLK- and the negative phase picture signal LVn-, wherein the source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 have a second Bias current Ip. And there is a first node V1 for comparing voltages between the first P-type transistor MP1 and the third load L3, and a second node V2 for comparing voltages between the second P-type transistor MP2 and the fourth load L4 .

It should be noted that the implementation of the input stage comparator 100 is not limited to the above description, and appropriate adjustments can be made according to requirements.

Please refer to FIG. 5, which is a schematic diagram of the minimum low voltage differential signal. As shown in the figure, the picture signal input terminals of the minimum low-voltage differential signal receiver 130 include the input terminals of positive-phase picture signals (ie, LV0+, LV1+, . . . , to LVn+), and the input terminals of negative-phase picture signals (ie, LV0- , LV1-, ..., to LVn-). The clock signal input terminals of the comparator 140 include the input terminal LCLK+ of the positive-phase clock signal, and the input terminal LCLK- of the negative-phase clock signal, wherein the positive-phase picture signal, the negative-phase picture signal, the positive-phase clock signal, and The negative-phase clock signal constitutes a minimum low-voltage differential signal, wherein V _CM represents a common-mode voltage V _CM between the power supply voltage VDD and the ground voltage GND. From the above description, if each frame signal is represented by 6 bits, the minimum number of frame signal input terminals of the low voltage differential signal receiver 130 needs to be 12. Through the aforementioned method, each data signal 210 is sequentially generated and stored in the corresponding linear latch 400 .

Please refer to FIG. 6A , which is a schematic diagram of an input-stage comparator and a control circuit according to a first embodiment of the present invention. As shown in the figure, when the data signal 210 of each output stage register 200 is stored in the linear latch 400 through the shift register 300, the control circuit 160 outputs a control signal to turn off the input The stage comparator 100, for example, outputs a positive-phase control signal CTP to turn off the first P-type transistor MP1 and the second P-type transistor MP2, and outputs a negative-phase control signal CTN to turn off the first N-type transistor MN1 and the second N-type transistor. Crystalline MN2. Therefore, when the first N-type transistor MN1, the second N-type transistor MN2, the first P-type transistor MP1, and the second P-type transistor MP2 are turned off, the first bias current In and the second bias current Ip Therefore, it is turned off, so that the input stage comparator 100 does not have power consumption caused by the bias current after the data writing is completed, reducing the overall power of the source driver 10 - 1 in use.

However, in addition to reducing the power consumption caused by the bias current of the input stage comparator 100 through the above embodiments, the following methods can also be used.

Please refer to FIG. 6B , which is a schematic diagram of an input-stage comparator and a control circuit according to a second embodiment of the present invention. As shown in the figure, the input-stage comparator 100 is turned off to reduce the bias current. For example, the control circuit 160 can connect the first N-type transistor MN1 and the second N-type transistor MN2 with the first bias A first switch 161 is provided between the current In, and a second switch 162 is provided between the first P-type transistor MP1 and the second P-type transistor MP2 and the second bias current Ip. Moreover, when the data signal 210 of each linear latch 400 is stored, the control circuit 160 outputs the negative phase control signal CTN to close the first switch 161 , and outputs the positive phase control signal CTP to close the second switch 162 . Through the above implementation manner, cutting off the first bias current In and the second bias current Ip can also realize that the input stage comparator 100 will not have power consumption caused by the bias current after the completion of data writing, reducing the source of power consumption. The overall power of the pole driver 10-1 when in use.

Please refer to FIG. 7 , which is a timing diagram of signal control of the input stage comparator and the control circuit according to an embodiment of the present invention. As shown in the figure, when the source driver 10 - 1 is activated, the clock signal 110 and the frame signal 120 , namely DIO_int_1 , DIO_int_2 , DIO_int_3 , . . . , and DIO_int_last are used to write and store data.

For example, assuming that the source driver 10 - 1 has 960 data channels, each data signal can be composed of 8 bits. The corresponding minimum low voltage differential signals are LVn+, LVn−, LCLK+, and LCLK− corresponding to n is 0 to 5, thereby forming DIO_int_1. Each data signal is sequentially written into the above-mentioned linear latch 400, when the data of the source driver 10-1 is written into the corresponding linear latch 400, the control circuit 160 in the source driver 10-1 The input-stage comparator 100 is turned off to cut off the bias current, that is, the first bias current In and the second bias current Ip are turned off by using the positive phase control signal CTP and the negative phase control signal CTN. Moreover, the source driver 10-1 sends a trigger signal DIO1 to the next source driver 10-2 to write data, and so on, the source driver 10-m starts to write data after receiving the trigger signal DIO(m-1). write.

It should be noted that the number of data channels of the source driver, or the number of bits constituting the data signal, etc. are not limited to the above descriptions, and can be appropriately adjusted according to requirements.

Please refer to FIG. 8 , which is a schematic diagram of source drivers connected in series according to an embodiment of the present invention. As shown in the figure, after the source driver 10-1 finishes storing data, it sends a trigger signal DIO1 to the next source driver 10-2. When the source driver 10-2 writes and stores data, the source The input-stage comparator 100 in the pole driver 10-1 is in an off state. Similarly, when the source driver 10-3 receives the trigger signal DIO2 to write and store data, the input stage comparators 100 in the source driver 10-1 and the source driver 10-2 are in the off state. , and so on until all the source driving crystals 10-m complete the storage of data.

That is to say, since the data writing and storage of the source drivers are carried out sequentially, the source drivers sorted earlier can save the most power consumption, that is, the source drivers 10-1 are the most, and then decrease in order, and the source drivers Drive 10-m is the least. The implementation of the control circuit 160 described above can be implemented in the following ways.

Please refer to FIG. 9 , which is a schematic structural diagram of a control circuit according to an embodiment of the present invention. As shown in the figure, the control circuit 160 includes at least a flip-flop 170 , a first inverter 180 , and a second inverter 190 . The flip-flop 170 has a voltage signal input terminal, a clock signal input terminal, and an output terminal, wherein the voltage signal input terminal receives the power voltage VDD, the clock signal input terminal receives the trigger signal DIO1, and the output terminal outputs the initial control signal CT_int. The first inverter 180 receives the initial control signal CT_int, and outputs the negative phase control signal CTN. The second inverter 190 receives the negative phase control signal CTN, and outputs the positive phase control signal CTP.

With the above circuit structure, when the control circuit 160 does not set switches on the paths of the first bias current In and the second bias current Ip, the first P-type transistor MP1 and the second P-type transistor MP1 can be turned off by the positive phase control signal CTP. type transistor MP2, and the negative phase control signal CTN turns off the first N-type transistor MN1 and the second N-type transistor MN2, so as to close the first bias current In and the second bias current Ip, so that the input stage comparator 100 After the data writing is completed, there will be no power consumption caused by the bias current, reducing the overall power of the source driver 10 - 1 in use. If the control circuit 160 sets the first switch 161 and the second switch 162 on the paths of the first bias current In and the second bias current Ip, the first switch 161 can be turned off by the negative phase control signal CTN, and the positive phase The control signal CTP turns off the second switch 162 .

Please refer to FIG. 10 , which is a flow chart of the steps of the method for controlling the input-stage comparator according to an embodiment of the present invention. As shown in the figure, the control method of the input stage comparator 100 has at least the following steps:

Step S1: Input the clock signal 110 and the frame signal 120 to the input stage comparator 100 of the source driver 10-1.

Step S2: When the source driver 10-1 finishes inputting data, generate a control signal (such as a positive-phase control signal CTP and a negative-phase control signal CTN) and a trigger signal DIO1, and the control signal compares the input level of the source driver 10-1 The device 100 is turned off.

Step S3: The trigger signal DIO1 is input to the serially connected source driver 10-2 for data input. Similarly, the input stage comparator 100 can be controlled in the above manner until the source driver 10-m finishes writing data.

According to an embodiment of the present invention, the input clock signal 110 includes an input positive-phase clock signal LCLK+ and a negative-phase clock signal LCLK-, and the input frame signal 120 includes an input positive-phase frame signal LVn+ and a negative-phase frame signal LVn-, wherein The clock signal 110 and the picture signal 120 are composed of minimum low voltage differential signals.

According to an embodiment of the present invention, the implementation of closing the input-stage comparator 100 may include closing a plurality of N-type transistors in the input-stage comparator 100, such as the first N-type transistor MN1 and the second N-type transistor MN1 in FIG. 6A The transistor MN2 is used to turn off the first bias current In between the plurality of N-type transistors and the ground voltage GND. And, close the plurality of P-type transistors of the input stage comparator 100, such as the first P-type transistor MP1 and the second P-type transistor MP2 in FIG. Between the second bias current Ip.

According to an embodiment of the present invention, the implementation of turning off the input stage comparator 100 may include turning off the first N-type transistor MN1 and the second N-type transistor MN2 as shown in FIG. 6B , and the first bias current In The first switch 161 is turned off, and the second switch 162 between the first P-type transistor MP1 and the second P-type transistor MP2 and the second bias current Ip as shown in FIG. 6B is turned off.

According to the embodiment of the present invention, before the source driver 10-2 receives the trigger signal DIO1, the input stage comparator 100 in the source driver 10-2 is kept in the on state, and so on, the input stage comparator 100 in the source driver 10-m The input-stage comparator 100 remains on before receiving the trigger signal DIO(m−1).

The present invention has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the patent claims are included in the scope of the present invention.

10-1, 10-2, 10-3, ..., 10-m: source driver 100: Input stage comparator 110: clock signal 120: Screen signal 130: Minimum low voltage differential signal receiver 140: Comparator 150-0, 150-1, 150-2, ..., 150-n: voltage swing signal 160: control circuit 161, 162: switch 170: Flip-flop 180: the first inverter 190: The second flip-flop CT_int: initial control signal CTP: positive phase control signal CTN: negative phase control signal 200: output stage register 210: data signal 300: shift register 400: Linear Latch 500: level converter 600: digital to analog converter 700: output buffer LV0+, LV1+, LV2+, ..., LVn+: positive phase picture signal LV0-, LV1-, LV2-, ..., LVn-: Negative phase picture signal LCLK+: positive phase clock signal LCLK-: Negative phase clock signal MN1: the first N-type transistor MN2: The second N-type transistor MP1: the first P-type transistor MP2: The second P-type transistor L1: first load L2: second load L3: the third load L4: Fourth load In: first bias current Ip: second bias current VDD: power supply voltage GND: ground voltage V1: first node V2: second node DIO_int_1, DIO_int_2, DIO_int_3, ..., DIO_int_last: screen signal DIO1, DIO2, DIO3, ..., DIO(m-1): trigger signal

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of source drivers connected in series.

FIG. 2 is a schematic diagram of the structure of the source driver.

FIG. 3 is a structural schematic diagram of an input stage comparator and an output stage register.

FIG. 4 is a schematic diagram of the structure of the input stage comparator.

FIG. 5 is a schematic diagram of a minimum low voltage differential signal.

FIG. 6A is a schematic diagram of an input-stage comparator and a control circuit according to a first embodiment of the present invention.

FIG. 6B is a schematic diagram of an input-stage comparator and a control circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of signal control of the input stage comparator and the control circuit according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of source drivers connected in series according to an embodiment of the present invention.

FIG. 9 is a schematic structural diagram of a control circuit according to an embodiment of the present invention.

FIG. 10 is a flowchart of steps of a method for controlling an input-stage comparator according to an embodiment of the present invention.

160: control circuit

161, 162: switch

CTP: positive phase control signal

CTN: negative phase control signal

LV0+, LV1+, LV2+, ..., LVn+: positive phase picture signal

LV0-, LV1-, LV2-, ..., LVn-:: Negative picture signal

LCLK+: positive phase clock signal

LCLK-: Negative phase clock signal

MN1: the first N-type transistor

MN2: The second N-type transistor

MP1: the first P-type transistor

MP2: The second P-type transistor

L1: first load

L2: second load

L3: the third load

L4: Fourth load

In: first bias current

Ip: second bias current

VDD: power supply voltage

GND: ground voltage

V1: first node

V2: second node

DIO1: trigger signal

Claims (10)

A source driver, comprising: an input-level comparator receiving a clock signal and a picture signal, and the input-level comparator generates a voltage swing signal according to the clock signal and the picture signal; a plurality of output-level temporarily registers, each of the output-stage registers is connected to the input-stage comparator, and each of the output-stage registers generates a data signal according to the received voltage swing signal, wherein the data signal is stored in a linear a latch; and a control circuit, wherein when the data signal of each linear latch is stored, the control circuit outputs a control signal to close the input stage comparator, and the source driver outputs a trigger signal to the next source driver in series. The source driver as described in claim 1, wherein the input stage comparator at least includes: a minimum low voltage differential signal receiver, having a picture signal input terminal corresponding to the number of bits of each picture signal, and the minimum low voltage The output terminal of the voltage difference signal receiver is connected to the corresponding output stage register; and a comparator has a clock signal input terminal and a clock signal output terminal. The source driver as described in claim 2, wherein the picture signal input terminal of the minimum low-voltage differential signal receiver includes an input terminal of a positive-phase picture signal and an input terminal of a negative-phase picture signal; The pulse signal input terminal includes the input terminal of the positive-phase clock signal and the input terminal of the negative-phase clock signal; and the positive-phase picture signal, the negative-phase picture signal, the positive-phase clock signal, and the negative-phase time signal The pulse signal constitutes a minimum low voltage differential signal. The source driver as described in claim 3, wherein the input stage comparator at least includes: a first N-type transistor, the drain of the first N-type transistor is connected to a power supply voltage through a first load; a The second N-type transistor, the drain of the second N-type transistor is connected to the power supply voltage through a second load, wherein the source of the first N-type transistor and the source of the second N-type transistor There is a first bias current between a ground terminal; a first P-type transistor, and the drain of the first P-type transistor is connected to the ground terminal through a third load, wherein the first N-type transistor The gate of the crystal and the gate of the first P-type transistor receive the positive-phase clock signal and the positive-phase picture signal; and a second P-type transistor, the drain of the second P-type transistor is passed through a The fourth load is connected to the ground terminal, wherein the gate of the second N-type transistor and the gate of the second P-type transistor receive the negative-phase clock signal and the negative-phase picture signal, wherein the first P There is a second bias current between the source of the P-type transistor and the source of the second P-type transistor and the power supply voltage. The source driver as described in Claim 4, wherein the control circuit at least includes: a flip-flop having a voltage signal input terminal, a clock signal input terminal, and an output terminal, wherein the voltage signal input terminal receives the power supply Voltage, the clock signal input end receives the trigger signal, and the output end outputs an initial control signal; a first inverter receives the initial control signal, and outputs a negative phase control signal; and a second inversion The device receives the negative phase control signal and outputs a positive phase control signal, wherein the positive phase control signal turns off the first P-type transistor and the second P-type transistor, and the negative phase control signal turns off the first P-type transistor. N-type transistor and the second N-type transistor. The source driver as claimed in item 4, wherein the control circuit at least includes: A flip-flop has a voltage signal input terminal, a clock signal input terminal, and an output terminal, wherein the voltage signal input terminal receives the power supply voltage, the clock signal input terminal receives the trigger signal, and the output terminal outputs An initial control signal; a first inverter, receiving the initial control signal, and outputting a negative phase control signal; a second inverter, receiving the negative phase control signal, and outputting a positive phase control signal; a first A switch is arranged between the source of the first N-type transistor and the source of the second N-type transistor and the first bias current, wherein when the data signal of each of the linear latches is When the storage is completed, the negative phase control signal closes the first switch; and a second switch is set on the source of the first P-type transistor and the source of the second P-type transistor and the second bias current Between, wherein when the data signal of each of the linear latches is stored completely, the positive phase control signal turns off the second switch. A method for controlling an input-level comparator, suitable for a source driver, at least comprising: inputting a clock signal and a frame signal to the input-level comparator of the source driver; when the source driver completes data input, generates a A control signal and a trigger signal, the control signal turns off the input stage comparator of the source driver; and the trigger signal is input to the source driver connected in series for data input. The control method as described in claim 7, wherein turning off the input-level comparator includes: turning off a plurality of N-type transistors of the input-level comparator, so as to turn off a connection between the plurality of N-type transistors and a ground terminal a first bias current; and turning off a plurality of P-type transistors of the input stage comparator, so as to turn off a second bias current between the plurality of P-type transistors and a power supply voltage. The control method as described in Claim 8, wherein: Turning off the first bias current further includes: turning off a first switch between the plurality of N-type transistors and the first bias current; and turning off the second bias current further includes: turning off the plurality of P-type transistors. A second switch between the transistor and the second bias current. The control method according to claim 7, wherein before the source driver finishes inputting data, the input stage comparator of the serially connected source driver remains on.

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