TWI796160B - Memory device and method of manufacturing the same - Google Patents

Abstract

Provided is a memory device including a substrate, a plurality of stack structures, and a protective layer. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In the cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, that of the control gate and that of the cap layer are substantially equal to each other.

Description

Memory element and manufacturing method thereof

The present invention relates to a memory element and its manufacturing method, and in particular to a memory element including a multi-layer cap layer and its manufacturing method.

With the improvement of semiconductor technology, the size of semiconductor memory elements is getting smaller and smaller, among which flash memory (Flash Memory) has gradually attracted attention due to its advantages of light weight, small size, and low power. However, in the current manufacturing process of the flash memory, it is easy to form a protrusion at the corner above the gate. Therefore, when removing dummy source contact plugs or dummy drain contact plugs to form source or drain contact openings by performing an etching process, etc., it is easy to make the The protection layer near the protruding portion is damaged, which causes problems such as element leakage current, which reduces the reliability of the semiconductor memory element.

The invention provides a memory element, which includes a plurality of stacked structures and a protection layer. A plurality of stacked structures are arranged on the array area of the substrate along a first direction, and each stacked structure extends along a second direction different from the first direction. In the cross-sectional view of the memory device, each stack structure includes a charge storage structure, a control gate and a top cover layer sequentially from the base, and the top cover layer has a multi-layer structure. The protective layer covers the sidewalls of the stacked structure. The width of the charge storage structure along the first direction, the width of the control gate along the first direction and the width of the top cover layer along the first direction are substantially equal to each other.

The invention provides a method for manufacturing a memory element, the steps of which are as follows. A plurality of stacked structures are formed on the substrate of the array area. A plurality of stacked structures are arranged along a first direction, and each stacked structure extends along a second direction different from the first direction. And in the cross-sectional view of the memory element, each stacked structure sequentially includes a charge storage structure, a control gate and a top cover layer from the base, wherein the top cover layer has a multi-layer structure. The width of the charge storage structure along the first direction, the width of the control gate along the first direction and the width of the top cover layer along the first direction are substantially equal to each other. Next, a protective layer is formed on the sidewalls of the stacked structure. A conductor layer is formed on the substrate to fill the spaces between the multiple stacked structures. A planarization process is performed to form a plurality of conductor strips. At least one conductor strip is patterned to form a plurality of conductor columns. Moreover, a replacement process is performed to replace the plurality of conductor strips and the plurality of conductor posts with a plurality of contact plugs.

Based on the above, in the present invention, the width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the top cover layer along the first direction are substantially equal to each other, so that the stacked structure has Substantially smooth sidewalls. In this way, the protection layer can be prevented from being damaged by the etching process, etc., and its integrity can be maintained, To further improve component reliability. On the other hand, in the manufacturing method of the present invention, the top cover layer of the stacked structure can be used as a polishing buffer layer, so the dummy source contact plugs can be directly isolated through the planarization process, and only the subsequent patterning process is required It is enough to form a dummy drain contact plug.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

10: memory element

100: base

100a: surface

101: Isolation structure

102: array area

104: Surrounding area

106: Tunneling dielectric layer

110: The first stack structure

110a, 120a, 138a, 150a, 152a, 160a: top surface

110b, 120b: side walls

112:Charge storage structure

114: dielectric layer

116, 140: hard mask layer

120: second stack structure

122: gate electrode

124: dielectric layer

130, 131, 132, 133: spacer wall layer

131A, 132A, 133A: layers of spacer material

136: protective layer

136a, 156a: highest top surface

138: conductor layer

142: gap wall

144: Silicide layer

146: lining

148, 150, 158, 160: oxide layer

152: conductor bar

154: conductor column

156: Nitride layer

162, 164: contact plug

AA: active area

BL: barrier layer

CG: Control Gate

CL: cap layer

D1: the first direction

D2: Second direction

PR: Mask Pattern

OP1: first opening

OP2: second opening

OP3: the third opening

OP4: fourth opening

Figure 1A, Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 11D, Figure 12A, Figure 12D, Figure 13A, Figure 13C, Figure 14A , FIG. 14C, FIG. 15A, FIG. 15C, FIG. 16A, FIG. 16C, FIG. 17A and FIG. 17C are schematic cross-sectional views of the manufacturing process of the array region of the memory device according to an embodiment of the present invention.

Figure 1B, Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 11E, Figure 12B, Figure 12E, Figure 13B, Figure 13D, Figure 14B , FIG. 14D, FIG. 15B, FIG. 15D, FIG. 16B, FIG. 16D, FIG. 17B and FIG. 17D are schematic cross-sectional views of the manufacturing process of the peripheral region of the memory device according to an embodiment of the present invention.

FIG. 1C , FIG. 11C and FIG. 12C are schematic top views of FIG. 1A , FIG. 11A and FIG. 12A , respectively.

Figure 1A, Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 11D, Figure 12A, Figure 12D, Figure 13A, Figure 13C, Figure 14A , FIG. 14C, FIG. 15A, FIG. 15C, FIG. 16A, FIG. 16C, FIG. 17A and FIG. 17C are schematic cross-sectional views of the manufacturing process of the array region of the memory element according to an embodiment of the present invention; FIG. 1B, FIG. 2B, FIG. 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 11E, Figure 12B, Figure 12E, Figure 13B, Figure 13D, Figure 14B, Figure 14D, Figure 15B, Figure 15D , FIG. 16B, FIG. 16D, FIG. 17B and FIG. 17D are schematic cross-sectional views of the manufacturing process of the peripheral region of the memory element according to an embodiment of the present invention; FIG. 1C, FIG. 11C and FIG. 12C are respectively FIG. 1A, FIG. 11A and FIG. 12A top view diagram. It should be noted that Fig. 1A, Fig. 11A and Fig. 12A are schematic cross-sectional views of line II' in Fig. 1C, Fig. 11C and Fig. 12C respectively; Fig. 11D and Fig. 12D are respectively II-II' in Fig. 11C and Fig. 12C Line schematic diagram.

First, please refer to FIG. 1A to FIG. 1C at the same time, a substrate 100 is provided. The substrate 100 includes an array area 102 and a peripheral area 104 . As shown in FIG. 1C , the isolation structure 101 is disposed in the substrate 100 to define a plurality of active areas (AA) on the substrate 100 . The active area AA extends, for example, along the first direction D1. In one embodiment, the substrate 100 is, for example, a silicon substrate. The isolation structure 101 may be a shallow trench isolation (STI) structure. As shown in FIGS. 1A and 1B , a tunneling dielectric layer 106 may be formed on the surface 100 a of the substrate 100 . In an embodiment, the material of the tunneling dielectric layer 106 may include dielectric materials such as silicon oxide.

A plurality of first stacked structures 110 are disposed on the substrate 100 of the array area 102, A plurality of second stacked structures 120 are disposed on the substrate 100 in the peripheral area 104 . As shown in FIG. 1A and FIG. 1B , the height of the first stack structure 110 is greater than the height of the second stack structure 120 , for example. As shown in FIG. 1C , the first stack structure 110 may be a strip structure and cross the active area AA. In other words, the first stack structure 110 extends along a second direction D2 different from the first direction D1. In this embodiment, the second direction D2 is perpendicular or orthogonal to the first direction D1, but the invention is not limited thereto. In addition, although only one second stack structure 120 is shown in FIG. 1A and FIG. 1B , only five first stack structures 110 are shown in FIG. 1C . In other embodiments, the quantities of the first stacked structures 110 and the second stacked structures 120 can be adjusted according to design requirements, which is not limited in the present invention.

In this embodiment, the first stack structure 110 includes a charge storage structure 112 , a barrier layer BL, a control gate (Control Gate) CG and a cap layer CL in order from bottom to top. In the cross-sectional view 1A, the sidewall 110b of the first stack structure 110 is substantially straight. Specifically, the sidewalls of the charge storage structure 112 , the control gate CG and the cap layer CL on the same side are, for example, located on the same straight line parallel to the normal vector of the substrate 100 . In other words, the width of the charge storage structure 112 along the first direction D1 , the width of the control gate CG along the first direction D1 , and the width of the cap layer CL along the first direction D1 are substantially equal to each other. In this way, the first stacked structure 110 can have a substantially smooth sidewall 110b. Therefore, when the protective layer and the like are formed on the sidewall 110b of the first stacked structure 110 in subsequent processes, protrusions can be avoided, and the position on the sidewall can be ensured. The protective layer on 110b has a smooth surface. In one embodiment, the barrier layer BL can be regarded as an inter-gate dielectric layer, which can be oxide/nitride/oxide (Oxide-Nitride-Oxide, ONO) composite layer. The material of the control gate CG includes conductive material, which can be, for example, doped polysilicon, non-doped polysilicon or a combination thereof.

In this embodiment, the charge storage structure 112 is suitable for storing charges. In one embodiment, the charge storage structure 112 may include a floating gate (Floating Gate), but the invention is not limited thereto. The material of the floating gate includes conductive material, which can be, for example, doped polysilicon, non-doped polysilicon or a combination thereof.

In this embodiment, the capping layer CL has a multilayer structure. For example, the cap layer CL may include a dielectric layer 114 and a hard mask layer 116 . The dielectric layer 114 is, for example, disposed between the control gate CG and the hard mask layer 116 . The width of the dielectric layer 114 along the first direction D1 is substantially equal to the width of the hard mask layer 116 along the first direction D1. In this way, a smooth surface can be maintained even when a protective layer or the like is formed on the sidewall of the cap layer CL in subsequent processes. In this embodiment, the thickness of the hard mask layer 116 is, for example, 100 nm˜150 nm. In addition, the material of the hard mask layer 116 is, for example, silicon nitride, but the invention is not limited thereto. In other embodiments, the hard mask layer 116 can also adopt other suitable thickness and/or hard mask material, as long as it can prevent polishing during chemical mechanical polishing process and other steps. In an embodiment, the material of the dielectric layer 114 may include dielectric materials such as silicon oxide.

In this embodiment, the second stack structure 120 includes, for example, a gate electrode 122 and a dielectric layer 124 sequentially from bottom to top. In one embodiment, the material of the gate electrode 122 includes a conductive material, which can be, for example, doped polysilicon, undoped polysilicon or a combination thereof. The material of the dielectric layer 124 is, for example, silicon oxide.

Next, please refer to FIG. 2A and FIG. 2B , the spacer material layer 131A, the spacer material layer 132A and the spacer material layer 133A are sequentially formed on the substrate 100 , the first stack structure 110 and the second stack structure 120 . For example, in the array region 102, the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A sequentially conformally cover the surface 100a of the substrate 100, and the top surface 110a and sidewall 110b; in the peripheral region 104, the spacer material layer 131A, the spacer material layer 132A and the spacer material layer 133A sequentially conformally cover the surface 100a of the substrate 100, and the top surface 120a and the sidewall of the second stack structure 120 120b. In one embodiment, the method for forming the spacer material layer 131A, the spacer material layer 132A and the spacer material layer 133A is, for example, a deposition method. The material of the spacer material layer 131A may be silicon oxide or the like. The material of the spacer material layer 132A may be silicon nitride or the like. The material of the spacer material layer 133A may be silicon oxide or the like.

Then, please refer to FIG. 3A and FIG. 3B at the same time, remove part of the spacer material layer 131A, the spacer material layer 132A and the spacer material layer 133A, to expose the top surface 110a of the first stack structure 110, the second stack structure 120 and part of the tunneling dielectric layer 106, and the spacer layer 131, the spacer layer 132 and the spacer layer 133 are formed on the sidewall 110b of the first stack structure 110 and the sidewall 120b of the second stack structure 120. (hereinafter collectively referred to as the spacer layer 130). In one embodiment, the method of removing part of the spacer material layer 131A, the spacer material layer 132A and the spacer material layer 133A is, for example, performing an anisotropic etching process, but the invention is not limited thereto.

Then, please refer to FIG. 4A and FIG. 4B at the same time, the protective layer 136 conformal topography formed on the substrate 100. In the present embodiment, the first stacked structure 110 has a substantially smooth sidewall 110b, thus ensuring that the protection layer 136 formed on the sidewall 110b can have a substantially smooth surface. In an embodiment, the method of forming the protective layer 136 is, for example, a deposition method, and the material of the protective layer 136 may be silicon nitride or the like.

Afterwards, referring to FIG. 5A and FIG. 5B simultaneously, the conductive layer 138 is disposed on the protective layer 136 . In this embodiment, the height of the conductor layer 138 is greater than the height of the first stack structure 110 and the height of the second stack structure 120 . In this embodiment, the height of the conductor layer 138 located in the array region 102 is greater than that of the conductor layer 138 located in the peripheral region 104 , for example. Next, a hard mask layer 140 is formed on the conductive layer 138 . In one embodiment, the material of the conductive layer 138 can be, for example, doped polysilicon, undoped polysilicon or a combination thereof. The material of the hard mask layer 140 may be a suitable material such as silicon nitride.

Next, referring to FIG. 6A and FIG. 6B , a spacer wall 142 is formed on the sidewall 120 b of the second stack structure 120 . The method for forming the spacer 142 includes, for example, the following steps, but the invention is not limited thereto. Firstly, a photoresist pattern layer (not shown) is formed on the hard mask layer 140 in the array region 102, and an etching process is performed using the photoresist pattern layer as a mask to remove the conductor layer 138 in the peripheral region 104. and the hard mask layer 140 to expose the second stack structure 120 . In an embodiment, the etching process may be a dry etching process in which different etching gases are used for etching, such as a reactive ion etching (RIE) process. Next, the photoresist pattern layer is removed, and a spacer material (not shown) such as silicon oxide is blanket-deposited on the substrate 100 , and the spacer material is etched to form the spacer 142 . In this embodiment, part of the protection layer 136 is also removed.

Then, please refer to FIG. 7A and FIG. 7B at the same time. After forming the spacers 142 , it may further include forming a plurality of silicide layers 144 on the substrate 100 and the second stack structure 120 . In one embodiment, the material of the silicide layer 144 may be, for example, titanium silicide, cobalt silicide, nickel silicide or a combination thereof. A liner 146 is then conformally deposited on the substrate 100 . In an embodiment, the material of the lining layer 146 may be silicon nitride or the like.

Afterwards, referring to FIG. 8A and FIG. 8B simultaneously, an oxide layer 148 is blanket formed on the substrate 100 . In this embodiment, the height of the oxide layer 148 located in the array region 102 is greater than the height of the oxide layer 148 located in the peripheral region 104 , for example. In an embodiment, the material of the oxide layer 148 may be silicon oxide or the like.

Next, referring to FIG. 9A and FIG. 9B , for example, a wet etching process is performed to remove part of the oxide layer 148 , the liner layer 146 and the remaining hard mask layer 140 to expose the conductor layer 138 . In this embodiment, taking one surface of the substrate 100 as a reference plane, the level of the top surface 150 a of the oxide layer 150 is lower than the level of the top surface 138 a of the conductor layer 138 , for example. In addition, the level of the top surface 150 a of the oxide layer 150 is, for example, higher than the level of the top surface 110 a of the first stacked structure 110 . In other words, the level of the top surface 150 a of the oxide layer 150 is between the level of the top surface 138 a of the conductive layer 138 and the level of the top surface 110 a of the first stacked structure 110 .

Then, please refer to FIG. 10A and FIG. 10B at the same time, using the hard mask layer 116 as a polishing buffer layer, the conductor layer 138 is planarized until the highest top surface 136 a of the protection layer 136 is exposed, so as to obtain conductor strips 152 . In this embodiment, the conductor strip 152 is located between two adjacent first stacked structures 110 . Taking one surface of the substrate 100 as As a reference plane, the level of the highest top surface 136 a of the protective layer 136 is substantially equal to the level of the top surface 152 a of the conductor strip 152 . In other words, the highest top surface 136 a of the passivation layer 136 is substantially coplanar with the top surface 152 a of the conductive strip 152 . In contrast, in the prior art, a conductor layer with a certain height is usually reserved, wherein the height is, for example, greater than the height of the first stacked structure, and a spin-coated carbon layer or a photoresist layer is formed on the conductor layer; and then the The conductor layer is subjected to a patterning process to obtain a plurality of conductor strips. However, the present invention uses the hard mask layer 116 in the first stack structure 110 as a polishing buffer layer, which can directly form the conductor strips 152 and also isolate the source contact plugs to be formed later by the planarization process. Therefore, it is only necessary to perform a patterning process on at least one of the plurality of conductor strips 152 to form a conductor column (that is, form a dummy drain contact plug). Details are described later. In one embodiment, the planarization process is, for example, a chemical mechanical polishing (CMP) process, an etch back process or a combination thereof.

On the other hand, in the step of forming the conductor strips 152 , the oxide layer 150 may also be planarized to reduce the level of the top surface 150 a of the oxide layer 150 . In this embodiment, taking a surface of the substrate 100 as a reference plane, the level of the top surface 150 a of the oxide layer 150 is substantially equal to the level of the top surface 152 a of the conductor strip 152 . In other words, the top surface 150 a of the oxide layer 150 is substantially coplanar with the top surface 152 a of the conductive strip 152 .

Then, referring to FIGS. 11A to 11E , a mask pattern PR is formed on the substrate 100 . The mask pattern PR has a plurality of first openings OP1 corresponding to the first stack Conductor strips 152 on one side of stack structure 110. That is to say, the first opening OP1 is located directly above the conductor strip 152 on one side of the first stack structure 110 , but not directly above the conductor strip 152 on the other side of the first stack structure 110 . In addition, it can be seen from FIG. 11A , FIG. 11C , and FIG. 11D that the first opening OP1 is located directly above the conductor strip 152 on the isolation structure 101 , but not directly above the conductor strip 152 on the active area AA. As shown in FIG. 11A and FIG. 11C , the width W of the first opening OP1 along the second direction D2 is, for example, 120 nm, and exposes part of the protection layer 136 and the corresponding conductor strips 152 . In an embodiment, the material of the mask pattern PR is such as carbon, photoresist material and other suitable materials.

Afterwards, referring to FIGS. 12A to 12E , the conductor bar 152 is patterned into a plurality of conductor columns 154 . Specifically, using the mask pattern PR as a mask, the conductor strips 152 exposed by the first opening OP1 are removed to form a plurality of conductor columns 154 and the second opening OP2. The second opening OP2 exposes the protective layer 136 on the surface 100 a of the substrate 100 . In addition, as shown in FIG. 12C , the conductive pillars 154 are respectively disposed on the active area AA, and are alternately disposed along the second direction D2. In more detail, FIG. 12A is a schematic cross-sectional view of line I-I' in FIG. 12C . Therefore, after the above-mentioned patterning process is performed, the conductor strip 152 in FIG. 12A will be removed. On the other hand, FIG. 12D is a schematic cross-sectional view of line II-II' in FIG. 12C. Therefore, after the above-mentioned patterning process is performed, the conductor strips 152 in FIG. 12D will not be removed to form the conductor pillars 154 . In one embodiment, the method for removing the conductor strips 152 may be a dry etching process, such as a reactive ion etching (RIE) process, but the invention is not limited thereto.

In this embodiment, as shown in FIG. 12A, FIG. 12C, and FIG. 12D, the conductor bar 152 can be regarded as a virtual source contact plug, and the conductor post 154 can be regarded as a virtual drain. contact plug. Here, the so-called "dummy" refers to a structure that will be removed by a subsequent replacement process. The positions of the dummy source/drain contact plugs are replaced by subsequently formed source/drain contact plugs.

Next, please refer to FIGS. 13A to 13D, FIGS. 14A to 14D, FIGS. 15A to 15D, FIGS. 16A to 16D and FIGS. 154 is replaced by a plurality of contact plugs 162, 164. Specifically, referring to FIGS. 13A to 13D , a nitride layer 156 and an oxide layer 158 may be sequentially formed on the substrate 100 . The nitride layer 156 conformally covers the substrate 100 . The oxide layer 158 fills the second opening OP2 and blankets the nitride layer 156 . In one embodiment, the nitride layer 156 may be silicon nitride. The oxide layer 158 may be silicon oxide.

Then, referring to FIGS. 14A to 14D , a planarization process is performed on the oxide layer 158 to expose the nitride layer 156 outside the second opening OP2 . In this case, the uppermost top surface 156a of the nitride layer 156 and the top surface 160a of the oxide layer 160 can be considered to be coplanar. In one embodiment, the planarization process may be, for example, a chemical mechanical polishing (CMP) process, an etch back process, or a combination thereof.

Then, referring to FIG. 15A to FIG. 15D , part of the nitride layer 156 , the conductor strip 152 and the conductor column 154 are removed to form a plurality of third openings OP3 and fourth openings OP4 . A plurality of third openings OP3 and fourth openings OP4 are respectively formed between the first stack structures 110 and expose the passivation layer 136 . Here, since the first stacked structure 110 of this embodiment has smooth sidewalls 110b without protrusions, when removing the conductor strip 152 and the conductor post 154, it is possible to avoid alignment with the side of the first stacked structure 110. The protection layer 136 on the wall 110 b causes damage, thereby avoiding problems such as element leakage current and improving the reliability of the semiconductor memory element. In this embodiment, the third opening OP3 may be a strip opening extending along the second direction D2. The fourth openings OP4 may be island-shaped or column-shaped openings, which are alternately arranged along the second direction D2. In one embodiment, the method for removing part of the nitride layer 156 , the conductive strips 152 and the conductive pillars 154 may be, for example, a dry etching process using different etching gases, such as a reactive ion etching (RIE) process.

After that, referring to FIGS. 16A to 16D , an etching process is performed to remove the protection layer 136 and the tunneling dielectric layer 106 under the third opening OP3 and the fourth opening OP4, so as to separate the third opening OP3 and the fourth opening OP4 extends downwards, thereby exposing the substrate 100 . In the etching process, the protection layer 136 on the top surface 110a of the first stacked structure 110 is also removed, so that the top surface 110a of the first stacked structure 110 and the top surface 160a of the adjacent oxide layer 160 share the same thickness. flat. In one embodiment, the etching process may include a dry etching process, such as a reactive ion etching (RIE) process. In this embodiment, the hard mask layer 116 can further protect the first stack structure 110 from being damaged by the etching process.

Next, referring to FIG. 17A to FIG. 17D , a conductive material is formed in the third opening OP3 and the fourth opening OP4 to form a plurality of contact plugs 162 and contact plugs 164 , thereby completing the memory element 10 of this embodiment. In this embodiment, the contact plug 162 can be regarded as a source contact plug, and the contact plug 164 can be regarded as a drain contact plug. In one embodiment, the contact plugs 162 may be strip-shaped in the top view direction of the memory element 10 and extend along the second direction D2. In another embodiment, in the memory element 10 The contact plugs 164 may be island-shaped in a top view direction, and arranged alternately along the second direction D2. In one embodiment, the memory device 10 is, for example, a flash memory device, but the invention is not limited thereto. In one embodiment, the conductor material includes a metal material (such as W, Cu, AlCu, etc.), a barrier metal (such as Ti, TiN, Ta, TaN, etc.) or a combination thereof, and the formation method may be electroplating, physical Appropriate forming methods such as vapor deposition (physical vapor deposition, PVD) and chemical vapor deposition (chemical vapor deposition, CVD).

Hereinafter, the memory device of this embodiment will be described with reference to FIGS. 17A to 17D . It should be noted that although the manufacturing method of the memory element in this embodiment is manufactured using the above-mentioned manufacturing method as an example, the manufacturing method of the memory element in this embodiment is not limited thereto.

Please refer to FIG. 17A to FIG. 17D , the memory element 10 of this embodiment includes: a substrate 100 , a plurality of first stacked structures 110 , a plurality of second stacked structures 120 , a protective layer 136 and a plurality of contact plugs 162 , 164 . The passivation layer 136 covers the sidewall 110 b of the first stacked structure 110 . A plurality of first stack structures 110 are arranged on the substrate 100 of the array region 102 along the first direction D1, and each first stack structure 110 extends along the second direction D2. As shown in cross-sectional views 17A and 17C , the first stack structure 110 sequentially includes a charge storage structure 112 , a barrier layer BL, a control gate CG and a cap layer CL from the substrate 100 . Specifically, the width of the charge storage structure 112 along the first direction D1 , the width of the control gate CG along the first direction D1 , and the width of the cap layer CL along the first direction D1 are substantially equal to each other. That is to say, the first stacked structure 110 has a substantially smooth sidewall 110b, which can prevent the protection layer 136 from being etched. The damage of the process, etc., maintains its integrity, so as to further improve the reliability.

In this embodiment, the cap layer CL is, for example, a multi-layer structure including a dielectric layer 114 and a hard mask layer 116 . The dielectric layer 114 is disposed between the control gate CG and the hard mask layer 116 . The width of the dielectric layer 114 along the first direction D1 is substantially equal to the width of the hard mask layer 116 along the first direction D1. In this way, the first stacked structure 110 can maintain a smooth surface and ensure the integrity of the protection layer 136 on the sidewall 110b.

As shown in FIGS. 17A to 17D , a plurality of contact plugs 162 and contact plugs 164 are respectively disposed on the substrate 100 between the plurality of first stack structures 110 . In this embodiment, the contact plug 162 can be regarded as a source contact plug, and the contact plug 164 can be regarded as a drain contact plug. In one embodiment, the contact plugs 162 may be strip-shaped in the top view direction of the memory element 10 and extend along the second direction D2. In another embodiment, the contact plugs 164 may be island-shaped in the plan view direction of the memory element 10 and arranged alternately along the second direction D2. In this embodiment, the top surface of the contact plug 162 , the top surface of the contact plug 164 , and the top surface 110 a of the first stack structure 110 are substantially coplanar with each other.

In summary, the width of the charge storage structure of the present invention along the first direction, the width of the control gate along the first direction, and the width of the top cover layer along the first direction are substantially equal to each other, so that the first stacked structure With substantially smooth sidewalls, the protection layer can be prevented from being damaged by etching processes and the like, and its integrity can be maintained, so as to further improve reliability. On the other hand, in the manufacturing method of the present invention, the hard mask layer of the first stack structure can be used as a polishing buffer layer, so the dummy source contact plugs can be directly isolated through the planarization process, and only need to be patterned later. process in shape It is sufficient to form a dummy drain contact plug.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: memory element

100: base

100a: surface

102: array area

106: Tunneling dielectric layer

110: The first stack structure

110a: top surface

110b: side wall

112:Charge storage structure

114: dielectric layer

116: hard mask layer

131, 132, 133: spacer layer

136: protective layer

156: Nitride layer

160: oxide layer

162: contact plug

BL: barrier layer

CG: Control Gate

CL: cap layer

D1: the first direction

OP2: second opening

OP3: the third opening

Claims (9)

A memory element, comprising: a plurality of stacked structures arranged on an array area of a substrate along a first direction, and each of the stacked structures extends along a second direction different from the first direction, in the memory In the cross-sectional view of the element, each of the stacked structures includes a charge storage structure, a control gate, and a top cover layer sequentially from the base, and the top cover layer has a multi-layer structure; a protective layer covers the side walls of the stacked structure and a plurality of contact plugs respectively arranged on the substrate between the plurality of stacked structures, and the top surface of the contact plugs relative to the substrate is the same as the top surface of the stacked structures relative to the The top surface of the substrate is substantially coplanar, the width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the top cover layer along the first direction The widths are substantially equal to each other. The memory device according to claim 1, wherein the capping layer includes a dielectric layer and a hard mask layer, the dielectric layer is disposed between the control gate and the hard mask layer, and the A width of the dielectric layer along the first direction is substantially equal to a width of the hard mask layer along the first direction. The memory device according to claim 2, wherein the material of the hard mask layer is silicon nitride. The memory element as claimed in claim 1, wherein the plurality of contact plugs include; a plurality of source contact plugs, the plurality of The source contact plugs are strip-shaped and extend along the second direction; and a plurality of drain contact plugs are island-shaped in a plan view direction of the memory element, And arranged alternately along the second direction. A method for manufacturing a memory element, comprising: forming a plurality of stacked structures on a base of an array area, the plurality of stacked structures are arranged along a first direction, and each of the stacked structures is along a direction different from the first direction Extending in the second direction, in the cross-sectional view of the memory element, each of the stacked structures sequentially includes a charge storage structure, a control gate, and a top cover layer from the base, and the top cover layer has a multi-layer structure, Wherein the width of the charge storage structure along the first direction, the width of the control gate along the first direction and the width of the cap layer along the first direction are substantially equal to each other; forming a protective layer on the sidewall of the stacked structure; forming a conductor layer on the base to fill the space between the multiple stacked structures; performing a planarization process to form a plurality of conductor strips; at least one of the conductors patterning the strips to form a plurality of conductor columns; and performing a replacement process to replace the plurality of conductor strips and the plurality of conductor columns with a plurality of contact plugs. The method for manufacturing a memory device according to claim 5, wherein the top cover layer includes a dielectric layer and a hard mask layer, and the dielectric layer is disposed between the control gate and the hard mask layer , and the width of the dielectric layer along the first direction is substantially equal to the width of the hard mask layer along the first direction. The method for manufacturing a memory device according to claim 6, wherein the material of the hard mask layer is silicon nitride. The method of manufacturing a memory element as claimed in claim 5, wherein the top surface of the contact plug relative to the base is substantially coplanar with the top surface of the stack structure relative to the base. The manufacturing method of the memory element according to claim 5, wherein the replacement process includes: removing the plurality of conductor strips and the plurality of conductor columns, so as to form a plurality of stacked structures respectively. openings, wherein the plurality of openings expose the base; and filling the plurality of openings with conductive material to form the plurality of contact plugs.

Images