TWI795926B - 3d flash memory and operation thereof - Google Patents

Abstract

Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. A material of the annular channel pillar is P-type doped semiconductor. The first source/drain pillar, the second source/drain pillar, the charge storage structure, the annular channel pillar and the gate layers form a plurality of memory units.

Description

3D flash memory and method of operation thereof

The invention relates to a 3D flash memory and its operating method.

Non-volatile memory, such as flash memory, is widely used in personal computers and other electronic devices due to the advantage that stored data will not disappear after power failure. The 3D flash memory currently used in the industry includes a non-or (NOR) flash memory, a non-and-type and (NAND) flash memory. In addition, another type of 3D flash memory is AND flash memory, which can be applied to a multi-dimensional flash array with high integration and high area utilization, and has the advantage of fast operation speed. The development of 3D flash memory has gradually become a current trend.

According to an embodiment of the present invention, the 3D flash memory includes a gate stack structure, a ring channel column, a first source/drain column, a second source/drain column and a charge storage structure. The gate stack structure is disposed on a dielectric substrate and includes a plurality of gate layers electrically isolated from each other. The ring-shaped channel column is arranged on the dielectric substrate and passes through the gate stack structure. A first source/drain column and a second source/drain column are disposed on the dielectric substrate, and are located within the ring-shaped channel column, and pass through the gate stack structure, the first source The pole/drain pole and the second source/drain pole are respectively coupled to the annular channel pole and separated from each other. The charge storage structure is disposed between each of the gate layers and the ring channel pillar. The material of the first source/drain column and the second source/drain column is P-type doped semiconductor, and the first source/drain column, the second source/drain column, the The charge storage structure, the ring channel column and the gate layers form a plurality of memory cells.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10:3D flash memory

101a, 101b: grooves

103a, 103b: direction

120:Gate stack structure

126: gate layer

104: insulation layer

122: The first source/drain column

124: Second source/drain column

116: isolation column

112, 902: charge storage structure

110: ring channel column

114: insulating material

100: Dielectric substrate

BL, BL1~BL4: Bit lines

SL, SL1~SL4: source line

WL, WL1~WL4: word line

12. C1~C16: memory unit

FIG. 1 is a schematic top view of a 3D flash memory according to an embodiment of the present invention.

FIG. 2 shows a schematic cross-sectional view of a 3D flash memory (AA' section line in FIG. 1 ) according to an embodiment of the present invention.

FIG. 3 is a schematic perspective view of a 3D flash memory according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of gate voltage versus drain current of a memory cell according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the probability distribution of threshold voltages of memory cells according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a circuit layout of a 3D flash memory according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a 3D flash memory according to an embodiment of the present invention.

FIG. 8 is a schematic top view of a memory unit according to another embodiment of the present invention.

FIG. 9 is a schematic top view of a 3D flash memory according to another embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a 3D flash memory according to another embodiment of the present invention.

Please refer to Figures 1, 2 and 3. Figure 1 shows a schematic top view of a 3D flash memory according to an embodiment of the present invention, and Figure 2 shows a 3D flash memory according to an embodiment of the present invention. Figure 3 shows a perspective view of a 3D flash memory according to an embodiment of the present invention. The 3D flash memory 10 includes a gate stack structure 120 , a ring channel pillar 110 , a first source/drain pillar 122 , a second source/drain pillar 124 and a charge storage structure 112 . The gate stack structure 120 is disposed on a dielectric substrate 100 and includes a plurality of gate layers 126 electrically isolated from each other by a plurality of insulating layers 104 . The annular channel pillar 110 is disposed on the dielectric substrate 100 and passes through the gate stack structure 120 . The first source/drain stud 122 and the second source/drain stud 124 are disposed on the dielectric substrate 100 , are located inside the annular channel stud 110 , and pass through the gate stack structure 120 . The charge storage structure 112 is disposed between each gate layer 126 and the annular channel pillar 110 . The charge storage structure 112 can be oxide-nitrogen-oxide (oxide-nitride-oxide, ONO), oxide-nitride-oxide-nitride-oxide (oxide-nitride-oxide-nitride-oxide, ONONO), energy Gap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS), metal-aluminum oxide-nitride-silicon (metal-aluminum oxide-nitride- oxide-silicon, MANOS), etc. Within the annular channel pillar 110 , the first source/drain pillar 122 and the second source/drain pillar 124 are respectively coupled to the annular channel pillar 110 and separated from each other by an insulating pillar 116 . First The space between the source/drain pole 122 and the second source/drain pole 124 and the charge storage structure 112 is provided with an insulating material 114 . The insulating pillar 116 can be a silicon nitride layer. The first source/drain column 122 and the second source/drain column 124 are respectively disposed on opposite sides of the insulating column 116, and may be in contact with or not in contact with the insulating column 116. The 3D flash memory 10 includes A plurality of memory units 12.

In one embodiment, a trench 101a is provided on the upper side of the gate stack, and a trench 101b is provided on the lower side of the gate stack. The extending direction 103a of the trench 101a is parallel to the extending direction 103b of the trench 101b. In addition, the connection line 105 between the first source/drain column 122 and the second source/drain column 124 is parallel to the extending directions 103a and 103b. In an alternative embodiment, as shown in FIG. 9 , the connection line 105 between the first source/drain column 122 and the second source/drain column 124 may not be perpendicular to the extending directions 103a and 103b. For example, the connection line 105 between the first source/drain column 122 and the second source/drain column 124 may have an included angle of 45 degrees with the extending directions 103a and 103b.

In one embodiment, as shown in FIG. 10 , different from FIG. 2 , the charge storage structure 112 is disposed on the surface between the gate layer 126 , the insulating layer 104 and the annular channel pillar 110 . That is to say, the charge storage structure 112 is not only disposed between the gate layer 126 and the annular channel pillar 110 , but also disposed between the gate layer 126 and the insulating layer 104 .

Although the shape of the "ring" in the illustrated embodiments of the present invention is a circle as an example, it should be noted that the shape of the "ring" can be a regular or irregular ellipse or polygon.

In one embodiment, the material of the first source/drain column 122 and the second source/drain column 124 is P-type doped semiconductor material, such as boron (Boron) doped silicon. In this embodiment, the 3D flash memory 10 is an AND type flash memory with a P-type channel. The operation of the 3D flash memory 10 can be performed individually for the memory unit 12 , as detailed below.

In an alternative embodiment, as shown in FIG. 8, a part of the first source/drain pillar 122' and a part of the second source/drain pillar 124' are located inside the annular channel pillar 110', and Another part of the first source/drain pillar 122' and another part of the second source/drain pillar 124' are not located within the annular channel pillar 110'.

Please also refer to FIG. 4 which is a schematic diagram of gate voltage versus drain current of a memory cell according to an embodiment of the present invention. For example, it is for the memory unit 12 shown in FIG. 2 and FIG. 3 . In Fig. 4, INIT is the curve of the gate voltage versus the drain current of the memory cell 12 without erasing operation and programming operation, and ERS is the curve of the gate voltage versus the drain current of the memory cell 12 after the erasing operation , PGM is a curve of the gate voltage versus the drain current when the memory cell 12 is programmed. The erasing operation uses -FN (Fowler-Nordheim) hole injection, which can make the threshold voltage of the memory cell 12 after the erasing operation lower. The programming operation uses +FN electron injection, which can make the threshold voltage of the memory cell 12 higher after the programming operation. It can be seen from FIG. 4 that when the threshold value of the sensing current of a sense amplifier coupled to the drain of the memory cell 12 is 6uA, the memory cell 12 that has been erased (that is, not programmed) The sense amplifier can sense a current greater than 6uA when the gate voltage of the memory cell 12 is lower than -6.5V, and the sense amplifier can sense the current when the gate voltage of the programmed memory unit 12 is lower than -2.5V. A current greater than 6uA was measured. This means that there will be no leakage current when the gate voltage of the programmed memory cell 12 is 0V. The threshold of the sensing current is used to determine whether the data stored in the memory unit 12 is a first value (eg 1) or a second value (eg 0). For example, during the read operation, when the sense amplifier detects that the drain current of the memory unit 12 is greater than the threshold value of the sensing current, it can be determined that the data stored in the memory unit 12 is the first value; otherwise, When the sense amplifier does not detect that the drain current of the memory unit 12 is greater than the sensing current threshold, it can be determined that the data stored in the memory unit 12 is the second value.

Please refer to FIG. 5 , which is a schematic diagram illustrating the probability distribution of threshold voltages of memory cells according to an embodiment of the present invention. In Fig. 5, the horizontal axis is the threshold voltage, the vertical axis is the probability, ERS is the probability distribution of the threshold voltage of the memory cell 12 after the erasing operation, and PGM is the probability distribution of the threshold voltage of the memory cell 12 after the programming operation . It can be seen from Figure 5 that ERS is centered at -6.5V, and PGM is centered at -2.5V, and the difference between the two is 4V. The gate voltage during read operation can be set to be the middle value between -6.5V and -2.5V, ie -4V.

Please refer to FIG. 6 , which is a schematic diagram of a circuit layout of a 3D flash memory according to an embodiment of the present invention. The first source/drain columns 122 are respectively coupled to a plurality of first signal lines. In one embodiment, the first signal line may be a bit line BL. The second source/drain columns 124 are respectively coupled to a plurality of second signal lines. In an embodiment, the second signal line may be a source line SL. The first signal line and the second signal line are respectively coupled to a plurality of sense amplifiers (not shown). It should be noted that since FIG. 6 is a top view, it cannot be seen that the gate layer 126 of the memory cell is coupled to multiple gate control lines. In one embodiment, the first signal line, the second signal line and the gate are respectively configured as a bit line (BL), a source line (SL) and a word line (WL). Subsequent descriptions will be based on the above correspondence. Even so, in another embodiment, the first signal line, the second signal line and the gate are respectively configured as source lines, bit lines and word lines.

Please refer to FIG. 7 , which is a schematic diagram of a 3D flash memory according to an embodiment of the present invention. The circuit structure in FIG. 7 can be regarded as an equivalent circuit of the circuit layout in FIG. 6 . The gates of adjacent memory cells in the X direction share the same word line, the adjacent memory cells in the Y direction share the same source line and bit line, and the adjacent memory cells in the Z direction share the same word line. Use the same source and bit lines. For example, memory cells C1, C2, C3, and C4 share word line WL1; memory cells C5, C6, C7, and C8 share word line WL2; memory cells C9, C10, C11, and C12 share word line WL3; memory cells C13, C14, C15, and C16 share word line WL4. Memory cells C1, C5, C9, and C13 share source line SL1 and bit line BL1, memory cells C2, C6, C10, and C14 share source line SL2 and bit line BL2, and memory cells C3, C7, C11, and C15 share The source line SL3 and the bit line BL3, and the memory cells C4, C8, C12, and C16 share the source line SL4 and the bit line BL4. Next, the reading operation, erasing operation and programming operation will be described in detail based on FIG. 7 .

During the read operation, assuming that the memory cell C11 to be read is to be read, a first read selection bias (for example-4V) is applied to the word line WL3 corresponding to the memory cell C11 to be read, and a first read selection bias is applied. Read the non-selection bias (for example 0V) on the remaining word lines, apply a second read selection bias (for example 0V) to the source line SL3 corresponding to the memory cell C11 to be read, and the remaining source lines Line floating, apply a third read selection bias (for example -1.8V) to the bit line BL3 corresponding to the memory cell C11 to be read, and the rest of the bit lines are floating. It should be noted that the first read selection bias is more negative than the second read selection bias.

The erase operation can be performed in units of a sector including multiple memory units. Assuming that the blocks to be erased include memory cells C9-C16, a first erase selection bias (for example-8V) is applied to the word lines WL3 and WL4 corresponding to the memory cells C9-C16 to be erased, and a The first erasing non-selection bias (such as 0V) is applied to the remaining word lines, and a second erasing selection bias (such as 10V) is applied to the source lines SL1-SL4 corresponding to the memory cells C9-C16 to be erased , apply a second erase selection bias (for example, 10V) to the corresponding Bit lines BL1-BL4 of the memory cells C9-C16 to be erased. It should be noted that the first erase selection bias is negative, and the second erase selection bias is positive. Since this embodiment is a P-type channel, there is no consideration of over erase. Therefore, the erasing operation does not use Incremental Step Pulse Programming (ISPP), but performs one-shot erasing. In this way, the time required for the erase operation can be effectively shortened. In this embodiment, since the erasing operation takes a block as a unit, the same bias voltage is applied to the bit lines BL1 - BL4 and the source lines SL1 - SL4 in the same block. And the bit lines and source lines belonging to the blocks not selected for erasing can be applied with the same bias voltage as the bit lines BL1-BL4 and the source lines SL1-SL4. However, in alternative embodiments, bit lines and source lines belonging to blocks not selected for erasure may be biased differently from bit lines BL1-BL4 and source lines SL1-SL4.

During the programming operation, assuming that the memory cell C11 to be programmed is applied, a first programming selection bias voltage (for example, 5V~12V) with an upper limit and a lower limit is applied to the character corresponding to the memory cell C11 to be programmed by means of ISPP. Line WL3, apply a first programming non-selection bias (such as 0V) to the remaining word lines, and apply a second programming selection bias (such as -8V) to the source line SL3 corresponding to the memory cell C11 to be programmed , applying a second programming non-selection bias (for example 2V) to the remaining source lines, applying a second programming selection bias (for example-8V) to the bit line BL3 corresponding to the memory cell C11 to be programmed, applying the second 2. Program the non-selection bias (eg, 2V) on the remaining bit lines. It should be noted that the first programming selection bias is positive, the second programming selection bias is negative, and the second programming non-selection bias is positive. Performing the programming operation in the ISPP mode can make the probability distribution of the threshold voltage of the programmed memory cell The cloth is narrow. In this example, the programmed memory cells are biased at about 20V, while the non-programmed memory cells are biased at -2V or 10V.

To sum up, the 3D flash memory according to the present invention has high integration, and the first source/drain column and the second source/drain column are made of P-type doped materials without considering excessive wiping. The problem of erasing, so that the erasing operation can be performed in a single pulse, thereby shortening the time required for erasing.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10:3D flash memory

101a, 101b: grooves

103a, 103b: direction

122: The first source/drain column

124: Second source/drain column

116: isolation column

112:Charge storage structure

110: ring channel column

114: insulating material

Claims (8)

A 3D flash memory, comprising: a gate stack structure disposed on a dielectric substrate, and including a plurality of gate layers electrically isolated from each other; a ring channel column disposed on the dielectric substrate and passing through the gate Pole stack structure; a first source/drain column and a second source/drain column are arranged on the dielectric substrate, and at least a part is located in the annular channel column and passes through the gate stack structure, the first source/drain column and the second source/drain column are respectively coupled to the annular channel column and are separated from each other; and a charge storage structure is disposed on each of the gate layer and the Between the annular channel columns, the material of the first source/drain column and the second source/drain column is P-type doped semiconductor, and the first source/drain column, the second The source/drain column, the charge storage structure, the annular channel column and the gate layers form a plurality of memory cells, wherein the gate layer of each memory cell is electrically connected to a gate control line, The first source/drain column is electrically connected to a first signal line, the second source/drain column is electrically connected to a second signal line, and a first read selection bias is applied to the and applying a second read selection bias to the first signal line corresponding to the memory cell to be read, wherein the first read selection bias is more negative The bias voltage is selected for the second read. The 3D flash memory according to claim 1, wherein the material of the first source/drain column and the second source/drain column is boron doped. The 3D flash memory according to claim 1, wherein the first source/drain column and the second source/drain column are electrically separated from each other by an insulating column. The 3D flash memory according to claim 3, wherein the insulating column is a silicon nitride layer. The 3D flash memory as described in Claim 1, wherein the gate layers are electrically isolated from each other by a plurality of insulating layers, and the charge storage structure is arranged on the gate layers and the ring channel pillar and the interface between these insulating layers. The 3D flash memory according to claim 1, wherein the first source/drain column and the second source/drain column are located within the circular channel column. A 3D flash memory, comprising: a gate stack structure disposed on a dielectric substrate, and including a plurality of gate layers electrically isolated from each other; a ring channel column disposed on the dielectric substrate and passing through the gate Pole stack structure; A first source/drain column and a second source/drain column are disposed on the dielectric substrate, at least a part of which is located within the annular channel column and passes through the gate stack structure, the first A source/drain column and the second source/drain column are respectively coupled to the annular channel column and are separated from each other; and a charge storage structure is disposed on each of the gate layer and the annular channel column Between, wherein the material of the first source/drain column and the second source/drain column is P-type doped semiconductor, and the first source/drain column, the second source/drain column The pole column, the charge storage structure, the annular channel column type and the gate layers form a plurality of memory cells, wherein the gate layer of each memory cell is electrically connected to a gate control line, and the first source The pole/drain column is electrically connected to a first signal line, the second source/drain column is electrically connected to a second signal line, and a first erase selection bias is applied to the memory corresponding to the memory to be erased. The gate control line of the cell; apply a second erase selection bias to the first signal line corresponding to the memory cell to be erased; and apply the second erase selection bias to the memory cell corresponding to the erase The second signal line of the memory unit, wherein the first erase selection bias is negative, and the second erase selection bias is positive. A 3D flash memory, comprising: A gate stack structure is arranged on a dielectric substrate and includes a plurality of gate layers electrically isolated from each other; a ring channel column is arranged on the dielectric substrate and passes through the gate stack structure; a first source The /drain column and a second source/drain column are arranged on the dielectric substrate, at least a part of which is located in the annular channel column, and passes through the gate stack structure, the first source/drain column The pole column and the second source/drain column are respectively coupled to the annular channel column and are separated from each other; and a charge storage structure is disposed between each of the gate layers and the annular channel column, wherein the The material of the first source/drain column and the second source/drain column is P-type doped semiconductor, and the first source/drain column, the second source/drain column, the charge The storage structure, the circular channel column and the gate layers form a plurality of memory cells, wherein the gate layer of each memory cell is electrically connected to a gate control line, and the first source/drain column electrically connected to a first signal line, the second source/drain column is electrically connected to a second signal line, and applies a first program selection bias to the gate control line corresponding to the memory cell to be programmed ; applying a second programming selection bias to the first signal line corresponding to the memory cell to be programmed; and applying the second programming selection bias to the second signal line corresponding to the memory cell to be programmed, Wherein the first program select bias applies incremental step pulse programming (ISPP) and is positive, and the second program select bias is negative.

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