TWI795967B - Configurable computing unit within memory - Google Patents

Abstract

A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line, wherein the first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line, wherein the second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

Description

Configurable Arithmetic Units in Memory

The present invention relates to a computing unit, and more particularly to a configurable computing unit in memory.

Computing in memory (CIM) technology is regarded as one of the effective technologies to solve the memory wall (memory wall). It uses computing in memory to reduce the number of data transfers, which can greatly increase the computing speed compared to traditional architectures. hundreds or even thousands of times. Today's large-scale artificial intelligence (AI) networks (such as Deep Neural Networks (DNN)) consume a large part of the energy in data transfer, but the technology of in-memory computing can also greatly Reducing the energy wasted due to data transfer can be said to be a potential technology for future artificial intelligence that can increase computing power and reduce power consumption.

The potential of in-memory computing has led many manufacturers and research institutes to invest in and publish many novel technologies, most of which are to change the computing unit to an analog type, and judge the analog accumulation value of the number of openings as data and weight for multiplication and accumulation operation (Multiply Accumulate, MAC) results, where static random access memory (SRAM) mostly uses the discharge time after charging the bit line (BL) to judge the value of the multiply-accumulate operation. For example, if the number of turned-on cells is larger, the discharge speed is faster; the number of turned-on cells is smaller, and the discharge speed is slower. Therefore, after measuring the remaining power of the bit line at a fixed time, the value of the current multiply-accumulate operation can be reversed.

However, because the amount of charge that can be stored on the bit line itself is not much, when the number of cells turned on at the same time is too large, it will be difficult to judge in a fixed time due to the fast leakage speed. It is impossible to simultaneously open too many data channels (data channels) to input data in the memory operation of the SRAM to perform the operation in the C memory. In this way, although the operation speed of the SRAM is extremely fast, it is difficult to improve the parallelism, and if the memory cells are to be changed, the yield rate of the memory may decrease and other problems.

Another novel technology is to use resistive memory (such as resistive random-access memory (RRAM)) to carry out the multiply-accumulate operation of the operation in the memory, and use the equivalent resistance of different open numbers to The value of the current is used as the value of the multiplication and accumulation operation. This method can increase the number of data channels that can be opened at the same time. However, due to the fact that the equivalent resistance will decrease rapidly after the cells are connected in parallel (R/N ratio), when the equivalent resistance decreases to a certain level, the parasitic resistance on the trace will become the dominant value, so that if you want to turn on enough The number of cells, the resistance value of the cell must be high enough, usually up to hundreds of thousands of ohms (ten k) level, this is the case for resistive memory, magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), etc. Resistive memory is not easy to achieve. Therefore, the purpose The previous technology of in-memory computing in resistive memory is still at the computing level of dozens of data channels.

The invention provides a configurable computing unit in the memory, which can achieve the function of multiplication and accumulation without changing the memory array.

The configurable operation unit in the memory of the present invention includes a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor. The first input transistor has a first terminal, a control terminal coupled to the first input bit line, and a second terminal. The first weight transistor has a first terminal coupled to the second terminal of the first input transistor, a control terminal receiving the first weight bit, and a second terminal coupled to the first readout bit line. The first resistor is coupled between the first terminal of the first input transistor and the common signal line. The second input transistor has a first terminal, a control terminal coupled to the second input bit line, and a second terminal. The second weight transistor has a first terminal coupled to the second terminal of the second input transistor, a control terminal receiving the first weight bit, and a second terminal coupled to the first readout bit line. The second resistor is coupled between the first terminal of the second input transistor and the common signal line. The resistance value of the second resistor is different from the resistance value of the first resistor.

The configurable computing unit in the memory of the present invention includes: a first weight transistor, at least one first input transistor, and at least one second input transistor. The first weight transistor has a first terminal coupled to the first readout bit line, a control terminal receiving the first weight bit, and a second terminal. At least one first input transistor has coupling The first end of the second end of the first weight transistor, the control end coupled to the first input bit line, and the second end coupled to the common signal line. At least one second input transistor has a first terminal coupled to the second terminal of the first weight transistor, a control terminal coupled to a second input bit line, and a second terminal coupled to the common signal line. The quantity of the at least one first input transistor is different from the quantity of the at least one second input transistor.

Based on the above, the configurable computing unit of the embodiment of the present invention realizes the function of multiplying and accumulating computing by connecting weight transistors, input transistors and resistors in series and setting the resistance values of different resistors. In this way, since the configurable operation unit is an additional functional block, the multiply-accumulate operation (MAC) of the data bit and the weight bit can be realized without changing the memory array. Alternatively, the function of multiply-accumulate operation can be achieved by connecting weight transistors in series with different numbers of input transistors.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

10: Memory subarray

100, 200, 300, 400, 500, 600, 700, 800: configurable computing unit

GBL<0>: global bit line

GBLB<0>: Global Inverted Phase Element Line

HWL: Manage Character Lines

INBL_0~INBL_3: input bit lines

LBL: local bit line

LBLB: Local Inverted Phase Line

M0-M33, M0a-M0n, M1a-M1n, M2a-M2n, M3a-M3n, M4a-M4n, M5a-M5n, M6a-M6n, M7a-M7n, M8a-M8n, M9a-M9n, M20a-M20n, M21a- M21n, M22a-M22n, M23a-M23n, M24a-M24n, M25a-M25n, T1~T6: Transistor

R_RBL<0>: the first read bit line

R_RBL<1>: Second read bit line

R01, R02, R11~R14, R21, R22, R01a-R01n, R02a-R02n, R11a-R11n, R12a-R12n: resistors

Rx: external resistor

Vdd: high voltage power line

VSS: low voltage power line

W0: the first weight bit

W1: the second weight bit

Wn: the nth weight bit

WBC_1~WBC_n: weight memory cell

WL: character line

FIG. 1 is a schematic circuit diagram of a configurable computing unit coupled to a weight memory cell according to a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a configurable arithmetic unit according to a second embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of a configurable arithmetic unit according to a third embodiment of the present invention picture.

FIG. 4 is a schematic circuit diagram of a configurable arithmetic unit according to a fourth embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a configurable computing unit coupled to a weight memory cell according to a fifth embodiment of the present invention.

FIG. 6 is a schematic circuit diagram of a configurable arithmetic unit according to a sixth embodiment of the present invention.

FIG. 7 is a schematic circuit diagram of a configurable arithmetic unit according to a seventh embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of a configurable computing unit according to an eighth embodiment of the present invention.

The concept of the present invention is to use the functional blocks required for internal operations in the traditional memory to convert the traditional memory from digital data to analog data for CIM operations, and use resistors of different impedance values to achieve The calculation sum current for different calculations reduces the drift of the process and increases the parallelism of calculations, so that the technology of the present invention can simultaneously have the fast operation of its own memory, and the high parallelism computing capability of the internal memory operation, which is very suitable for edge Inferential use of operations.

In other words, the concept of the present invention is to disclose a framework for computing in memory (artificial intelligence, AI), which can be output by a sense amplifier (SA) of a traditional memory or by using a bit line (BL) to lead out the storage data to the weight reader block, combined with the provided The output operation cell is used as the operation value through the total current of the operation cell with the input transistor and the weight transistor turned on at the same time, so as to achieve the operation function of the internal operation multiplication and accumulation operation in the memory. Among them, the concept of the present invention only needs to increase the peripheral circuit of the operation cell in the memory cell without changing the structure of the memory cell, so as to reduce the risk of read drift.

FIG. 1 is a schematic circuit diagram of a configurable computing unit coupled to a weight memory cell according to a first embodiment of the present invention. Please refer to FIG. 1. In this embodiment, the memory sub-array 10 and the configurable computing unit 100 are configured in a memory (not shown), and the configurable computing unit 100 includes at least transistors M0-M5 and resistors. R01 (corresponding to the first resistor) and resistor R11 (corresponding to the second resistor).

Transistor M2 (corresponding to the first input transistor) has a first end coupled to one input bit line (such as INBL_0~INBL_3) of a plurality of input bit lines (for example, input bit line INBL_2 here, corresponding to The control end of the first input bit line), and the second end. The transistor M3 (corresponding to the first weight transistor) has a first terminal coupled to the second terminal of the transistor M2, a control terminal receiving the first weight bit W0 from the memory sub-array 10, and a first readout terminal coupled to The second end of the bit line R_RBL<0>, wherein the first read bit line R_RBL<0> is coupled to the high voltage power line Vdd through an external resistor Rx. The resistor R01 is coupled between the first end of the transistor M2 and the common signal line, wherein the common signal line can be used as one of the global inverting phase element line GBLB<0> or the low-voltage power line VSS according to the operation. Depending on the circuit design.

Transistor M5 (corresponding to the second input transistor) has a first end coupled to another input bit line (in this case, input bit line INBL_3 is taken as an example) among a plurality of input bit lines (such as INBL_0~INBL_3). corresponding to the control terminal of the second input bit line), and the second end. The transistor M4 (corresponding to the second weight transistor) has a first end coupled to the second end of the transistor M5, a control end receiving the first weight bit W0, and a first readout bit line R_RBL<0> the second end of . The resistor R11 is coupled between the first end of the transistor M5 and the common signal line (shown as GBLB<0>/VSS).

In this embodiment, the resistance value of the resistor R11 is different from the resistance value of the resistor R01, so the total current flowing through the first read bit line R_RBL<0> reflects the first weight bit W0 and the input bit The sum of the weighted product of the bits (ie, logic levels) transmitted by the line INBL_2 and the weighted product of the first weighted bit W0 and the bits (ie, logic levels) transmitted by the input bit line INBL_3 . According to the above, the configurable operation unit 100 is an additional functional block, so the multiply-accumulate operation (MAC) of 2 data bits and 1 weight bit can be realized without changing the memory array.

In the embodiment of the present invention, the resistance value of the resistor R11 may be n times of the resistance value of the resistor R01 , where n is a positive integer greater than or equal to 1. For example, the resistance value of the resistor R11 may be twice the resistance value of the resistor R01, but this embodiment of the present invention is not limited thereto.

In this embodiment, the transistors M0 and M2 control whether the memory sub-array 10 is written based on the management word line HWL, that is, determine whether the bit transmitted by the global bit line GBL<0> is written into the memory sub-array. The weight memory cells in the array 10 (such as WBC_1~WBC_n). Further, the transistor M0 has a first end coupled to the global bit line GBL<0>, a control end coupled to the management word line HWL, and a second end coupled to the local bit line LBL of the memory sub-array 10 Two ends. Transistor M1 has a coupled As the first end of the common signal line of the global inversion cell line GBLB<0>, the control end coupled to the management word line HWL, and the second end of the local inversion cell line LBLB coupled to the memory sub-array 10 end.

In this embodiment, the memory sub-array 10 includes, for example, a plurality of weight memory cells WBC_1~WBC_n, wherein the weight memory cells are, for example, static random access memory (Static Random Access Memory, SRAM), but the present invention The embodiments are not limited thereto. In this embodiment, the weight memory cells (take WBC_1 as an example) include transistors T1-T6, for example. The transistor T1 has a first terminal coupled to the local bit line LBL, a control terminal coupled to the word line WL, and a second terminal. The transistor T2 has a first terminal coupled to the high voltage power line Vdd, a control terminal, and a second terminal coupled to the second terminal of the transistor T1. The transistor T3 has a first terminal coupled to the second terminal of the transistor T1 , a control terminal coupled to the control terminal of the transistor T2 , and a second terminal coupled to the ground line.

The transistor T4 has a first terminal coupled to the high voltage power line Vdd, a control terminal coupled to the second terminal of the transistor T1 , and a second terminal coupled to the control terminal of the transistor T2 . The transistor T5 has a first terminal coupled to the control terminal of the transistor T2 , a control terminal coupled to the second terminal of the transistor T1 , and a second terminal coupled to the ground line. The transistor T6 has a first terminal coupled to the control terminal of the transistor T2 , a control terminal coupled to the word line WL, and a second terminal coupled to the local inversion cell line LBLB.

FIG. 2 is a schematic circuit diagram of a configurable arithmetic unit according to a second embodiment of the present invention. Please refer to FIG. 1 and FIG. 2, wherein the same or similar components use the same or similar labels, the configurable computing unit 200 is roughly the same as the configurable computing unit 100, the difference is that the configurable computing unit 200 further includes a transistor M6 -M9, resistor R02 (corresponding to the third resistor) and resistor R12 (corresponding to the fourth resistor).

Transistor M6 (corresponding to the third input transistor) has a first end coupled to another input bit line (input bit line INBL_0 is taken as an example here) among a plurality of input bit lines (such as INBL_0~INBL_3). , corresponding to the control terminal and the second terminal of the third input bit line). The transistor M7 (corresponding to the third weight transistor) has a first end coupled to the second end of the transistor M6, a control end receiving the first weight bit W0, and a second readout bit line R_RBL<1> the second end of . The resistor R02 is coupled between the first end of the transistor M6 and the common signal line (shown as GBLB<0>/VSS).

Transistor M9 (corresponding to the fourth input transistor) has a first end coupled to another input bit line (input bit line INBL_1 is taken as an example here) among a plurality of input bit lines (such as INBL_0~INBL_3). , corresponding to the control terminal and the second terminal of the fourth input bit line). The transistor M8 (corresponding to the fourth weight transistor) has a first end coupled to the second end of the transistor M9, a control end receiving the first weight bit W0, and a second readout bit line R_RBL<1> the second end of . The resistor R12 is coupled between the first end of the transistor M9 and the common signal line (shown as GBLB<0>/VSS).

Wherein, the resistance value of the resistor R12 is different from the resistance value of the resistor R02, and the configurable operation unit 200 can implement a multiply-accumulate operation (MAC) of 4 data bits and 1 weight bit. In the embodiment of the invention, the resistance value of the resistor R11 is n times of the resistance value of the resistor R01, the resistance value of the resistor R12 is the n times of the resistance value of the resistor R02, and n is A positive integer greater than or equal to 1. The resistance value of the resistor R11 may be the same as that of the resistor R12, and the resistance value of the resistor R02 may be the same as that of the resistor R02.

FIG. 3 is a schematic circuit diagram of a configurable arithmetic unit according to a third embodiment of the present invention. Please refer to FIG. 2 and FIG. 3, wherein the same or similar components use the same or similar labels, the configurable computing unit 300 is roughly the same as the configurable computing unit 200, the difference is that the configurable computing unit 300 further includes a transistor M10 -M19, resistor R13 (corresponding to the fifth resistor), resistor R21 (corresponding to the sixth resistor), resistor R14 (corresponding to the seventh resistor) and resistor R22 (corresponding to the eighth resistor). The transistors M10 and M11 can refer to the transistors M0 and M1 , which will not be repeated here.

Transistor M12 (corresponding to the fifth input transistor) has a first end coupled to one input bit line (such as INBL_0~INBL_3) of a plurality of input bit lines (for example, input bit line INBL_2 here, corresponding to The control end of the first input bit line), and the second end. The transistor M13 (corresponding to the fifth weight transistor) has a first end coupled to the second end of the transistor M12, a control end receiving the second weight bit W1 from the memory sub-array 10, and a first read-out Second terminal of bit line R_RBL<0>. The resistor R13 is coupled between the first end of the first input transistor M12 and the common signal line (shown as GBLB<0>/VSS).

The transistor M15 (corresponding to the sixth input transistor) has a first end coupled to another input bit line (for example, the input bit line INBL_3 is used here as an example) among the plurality of input bit lines (such as INBL_0~INBL_3). Corresponding to the control terminal of the second input bit line) and the second terminal. The transistor M14 (corresponding to the sixth weight transistor) has a first end coupled to the second end of the transistor M15, a control end receiving the second weight bit W1, and a first readout bit line R_RBL<0> the second end of . Resistor R21 is coupled to the Between the first end of the sixth input transistor M15 and the common signal line (shown as GBLB<0>/VSS). Wherein, the resistance value of the resistor R21 is different from the resistance value of the resistor R13, but the resistance value of the resistor R13 may be the same as that of the resistor R11.

Transistor M16 (corresponding to the seventh input transistor) has a first end coupled to another input bit line (input bit line INBL_0 is taken as an example here) among a plurality of input bit lines (such as INBL_0~INBL_3). , corresponding to the control terminal and the second terminal of the third input bit line). The transistor M17 (corresponding to the seventh weight transistor) has a first end coupled to the second end of the transistor M16, a control end receiving the second weight bit W1, and a second readout bit line R_RBL<1> the second end of . The resistor R14 is coupled between the first end of the transistor M16 and the common signal line (shown as GBLB<0>/VSS).

Transistor M19 (corresponding to the eighth input transistor) has a first end coupled to another input bit line (input bit line INBL_1 is taken as an example here) among a plurality of input bit lines (such as INBL_0~INBL_3) , corresponding to the control terminal and the second terminal of the fourth input bit line). The transistor M18 (corresponding to the eighth weight transistor) has a first end coupled to the second end of the transistor M19, a control end receiving the second weight bit W1, and a second readout bit line R_RBL<1> the second end of . The resistor R22 is coupled between the first terminal of the transistor M19 and the common signal line (shown as GBLB<0>/VSS). Wherein, the resistance value of the resistor R22 is different from that of the resistor R14, but the resistance value of the resistor R14 may be the same as that of the resistor R12.

According to the above, the configurable operation unit 200 can realize the multiply-accumulate operation (MAC) of 4 data bits and 2 weight bits, that is, the first readout bit line Each of R_RBL<0> and the second sense bit line R_RBL<1> is an accumulation of two multiply-accumulate operations.

In the embodiment of the present invention, the resistance value of the resistor R12 is different from the resistance value of the resistor R02, and in the embodiment of the invention, the resistance value of the resistor R11 is n times the resistance value of the resistor R01, The resistance value of the resistor R12 is n times the resistance value of the resistor R02 to the power of 2, and n is a positive integer greater than or equal to 1. The resistance value of the resistor R11 may be the same as that of the resistor R12, and the resistance value of the resistor R02 may be the same as that of the resistor R02.

In the embodiment of the present invention, the resistance value of the resistor R21 is n times the resistance value of the resistor R13, and the resistance value of the resistor R22 is n times the resistance value of the resistor R14. And, the resistance value of the resistor R13 is n times of the resistance value of the resistor R01, the resistance value of the resistor R21 is the n times of the resistance value of the resistor R11, and the resistance value of the resistor R14 is The resistance value of the resistor R02 is the nth power of 2, and the resistance value of the resistor R22 is the nth power of 2 the resistance value of the resistor R12.

In the embodiment of the present invention, the ratio of the resistance value of the resistor R11 to the resistance value of the first resistor R01 may be different from the ratio of the resistance value of the resistor R21 to the resistance value of the resistor R13, and the resistance value of the resistor R12 The ratio to the resistance value of resistor R02 may be different from the ratio of the resistance value of resistor R22 to the resistance value of resistor R14.

FIG. 4 is a schematic circuit diagram of a configurable arithmetic unit according to a fourth embodiment of the present invention. Please refer to FIG. 2 and FIG. 4, in this embodiment, the computing unit 400 can be configured Including at least transistors M0a-M0n, M1a-M1n, M2a-M2n, M3a-M3n, M4a-M4n, M5a-M5n, M6a-M6n, M7a-M7n, M8a-M8n, M9a-M9n, resistors R01a-R01n, R02a-R02n, R11a-R11n, R12a-R12n. The configurable computing unit 400 can be regarded as a combination of multiple configurable computing units 200, that is, transistors M0a-M0n, M1a-M1n, M2a-M2n, M3a-M3n, M4a-M4n, M5a-M5n, M6a-M6n, M7a -M7n, M8a-M8n, M9a-M9n, resistors R01a-R01n, R02a-R02n, R11a-R11n, R12a-R12n can refer to the coupling relationship of transistors M0~M9, resistors R01, 02, The coupling relationship between R11 and R12 will not be repeated here.

In this embodiment, the configurable operation unit 400 can realize the multiply-accumulate operation (MAC) of 4 data bits and n weight bits (that is, the first weight bit W0 to the nth weight bit Wn), that is, That is, each of the first read bit line R_RBL<0> and the second read bit line R_RBL<1> is an accumulation of n multiply-accumulate operations. Also, each row may be a different weight combination, for example, the resistance value of the resistor R11a may be different from that of the resistor R11b and/or the resistance value of the resistor R01a may be different from that of the resistor R01b.

FIG. 5 is a schematic circuit diagram of a configurable computing unit coupled to a weight memory cell according to a fifth embodiment of the present invention. Please refer to FIG. 1 and FIG. 5 , wherein the same or similar components use the same or similar symbols. In this embodiment, the configurable arithmetic unit 500 in the memory includes transistors M0, M1, M20, two M21, and M22. The coupling relationship of transistors M0 and M1 can be shown in FIG. repeat.

Transistor M20 (corresponding to the first weight transistor) has a coupling to the first readout A first end of the bit line R_RBL<0>, a control end receiving the first weight bit W0, and a second end. The transistor M22 (corresponding to the first input transistor) has a first end coupled to the second end of the transistor M20, and coupled to one input bit line (herein referred to as The input bit line INBL_2 is taken as an example, corresponding to the control end of the first input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS). Each transistor M21 (corresponding to the second input transistor) has a first end coupled to the second end of the transistor M20, and coupled to another input bit line (such as INBL_0~INBL_3) among the plurality of input bit lines (such as INBL_0~INBL_3). Taking the input bit line INBL_3 as an example here, it corresponds to the control end of the second input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS).

In this embodiment, the number of transistors M22 is different from the number of transistors M21, so the total current flowing through the first read bit line R_RBL<0> reflects the first weight bit W0 and the input bit line INBL_2 The sum of the weighted product of the transmitted bits (ie, logic levels) and the weighted product of the first weighted bit W0 and the transmitted bits (ie, logic levels) of the input bit line INBL_3 .

In this embodiment, the quantity of the transistor M22 is 1, and the quantity of the transistor M21 is 2, but in other embodiments, the quantity of the transistor M22 can be 2 or other numbers, The number of transistors M21 can be 4 or other numbers. In addition, the number of transistors M21 may be 2 to the nth power of the number of transistors M22.

FIG. 6 is a schematic circuit diagram of a configurable arithmetic unit according to a sixth embodiment of the present invention. Please refer to Figure 5 and Figure 6, where the same or similar components use the same or similar With the same reference numerals, the configurable computing unit 600 is substantially the same as the configurable computing unit 500, the difference being that the configurable computing unit 600 further includes a transistor M23, two M24, and M25.

The transistor M23 (corresponding to the second weight transistor) has a first terminal coupled to the second readout bit line R_RBL<1>, a control terminal receiving the first weight bit W0, and a second terminal. The transistor M25 (corresponding to the third input transistor) has a first end coupled to the second end of the transistor M23, and coupled to another input bit line (such as INBL_0~INBL_3) among the plurality of input bit lines (INBL_0~INBL_3). Taking the input bit line INBL_0 as an example, it corresponds to the control end of the third input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS). The transistor M24 (corresponding to the fourth input transistor) has a first end coupled to the second end of the transistor M23, and coupled to another input bit line (such as INBL_0~INBL_3) among the plurality of input bit lines (in Taking the input bit line INBL_1 as an example, it corresponds to the control end of the fourth input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS).

In this embodiment, the number of transistors M25 is different from the number of transistors M24. And, the quantity of the transistor M25 is 1 as an example, and the quantity of the transistor M24 is 2 as an example, but in other embodiments, the quantity of the transistor M25 can be 2 or other numbers, and the quantity of the transistor M24 Quantity can be 4 or other quantity. In the embodiment of the present invention, the number of transistors M24 may be n times the number of transistors M25.

FIG. 7 is a schematic circuit diagram of a configurable arithmetic unit according to a seventh embodiment of the present invention. Please refer to Figure 6 and Figure 7, where the same or similar components use the same or similar The configurable computing unit 700 is roughly the same as the configurable computing unit 600, the difference is that the configurable computing unit 700 further includes transistors M26, M27, M28, four M29, two M30, M31, four M32, two M33.

The transistor M28 (corresponding to the third weight transistor) has a first terminal coupled to the first read bit line R_RBL<0>, a control terminal receiving the second weight bit W1, and a second terminal. Each transistor M30 (corresponding to the fifth input transistor) has a first end coupled to the second end of the transistor M28, and coupled to one input bit line (such as INBL_0~INBL_3) of a plurality of input bit lines (in Taking the input bit line INBL_2 as an example, it corresponds to the control end of the first input bit line) and the second end coupled to the common signal line (as shown by GBLB<0>/VSS). Each transistor M29 (corresponding to the sixth input transistor) has a first end coupled to the second end of the transistor M28 and coupled to another input bit line (such as INBL_0~INBL_3) among the plurality of input bit lines (such as INBL_0~INBL_3). Taking the input bit line INBL_3 as an example here, it corresponds to the control end of the second input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS).

The transistor M31 (corresponding to the fourth weight transistor) has a first terminal coupled to the second read bit line R_RBL<1>, a control terminal receiving the second weight bit W1, and a second terminal. Each transistor M33 (corresponding to the seventh input transistor) has a first terminal coupled to the second terminal of the transistor M31, coupled to yet another input bit line among the plurality of input bit lines (such as INBL_0~INBL_3) (Here, take the input bit line INBL_0 as an example, which corresponds to the third input bit line) and the second end coupled to the common signal line (shown as GBLB<0>/VSS). The transistor M32 (corresponding to the eighth input transistor) has a first end coupled to the second end of the transistor M31, coupled to multiple The control terminal of another input bit line (in this example, input bit line INBL_1 corresponding to the fourth input bit line) among the two input bit lines (such as INBL_0~INBL_3) and the common signal line coupled (shown as GBLB<0>/VSS) on the second terminal.

In this embodiment, the number of transistors M30 is different from the number of transistors M29. And, the quantity of the transistor M30 is 2 as an example, and the quantity of the transistor M29 is 4 as an example, but in other embodiments, the quantity of the transistor M30 can be 4 or other numbers, and the quantity of the transistor M29 Quantity can be 8 or other quantity. In the embodiment of the present invention, the number of transistors M29 may be n times the number of transistors M30.

In this embodiment, the number of transistors M33 is different from the number of transistors M32. Moreover, the quantity of the transistor M33 is 2 as an example, and the quantity of the transistor M32 is 4 as an example, but in other embodiments, the quantity of the transistor M33 can be 4 or other numbers, and the quantity of the transistor M32 Quantity can be 8 or other quantity. In the embodiment of the present invention, the number of transistors M32 may be n times the number of transistors M33.

In the embodiment of the present invention, the quantity of the transistor M30 may be the nth power times of 2 the quantity of the transistor M22, the quantity of the transistor M29 may be the nth power times of the quantity of the transistor M21, and the transistor M33 The number of transistors M25 may be 2 to the nth power, and the number of transistors M32 may be 2 to the nth power of the transistors M24.

In the embodiment of the present invention, the ratio of the number of transistors M21 to the number of transistors M22 may be different from the ratio of the number of transistors M29 to the number of transistors M30 The ratio, and the ratio of the number of transistors M24 to the number of transistors M25 may be different from the number of transistors M32 to the number of transistors M33.

FIG. 8 is a schematic circuit diagram of a configurable computing unit according to an eighth embodiment of the present invention. Please refer to FIG. 6 and FIG. 8, wherein the same or similar components use the same or similar labels. In this embodiment, the configurable computing unit 800 includes at least transistors M0a-M0n, M1a-M1n, M20a-M20n, M21a- M21n, M22a-M22n, M23a-M23n, M24a-M24n, M25a-M25n. The configurable computing unit 800 can be regarded as a combination of multiple configurable computing units 600, namely transistors M0a-M0n, M1a-M1n, M20a-M20n, M21a-M21n, M22a-M22n, M23a-M23n, M24a-M24n, M25a - The coupling relationship of M25n can refer to the coupling relationship of the transistors M0, M1, M20, M21, M22, M23, M24, M25 shown in FIG. 2, which will not be repeated here.

In this embodiment, the configurable operation unit 800 can realize the multiply-accumulate operation (MAC) of 4 data bits and n weight bits, that is, the first read bit line R_RBL<0> and the second read bit line R_RBL<0> Each of the bit lines R_RBL<1> is an accumulation of n multiply-accumulate operations. Moreover, each row may be a different combination of weights, for example, the number of transistors M21a may be different from that of transistors M21b and/or the number of transistors M22a may be different from that of transistors M22b.

To sum up, the configurable computing unit of the embodiment of the present invention realizes the function of multiplying and accumulating by connecting the weight transistor, the input transistor, and the resistor in series and setting the resistance values of different resistors. In this way, since the configurable arithmetic unit is an additional functional block, it can be used without changing the memory array, Realize the multiply-accumulate operation (MAC) of data bits and weight bits. Alternatively, the function of multiply-accumulate operation can be achieved by connecting weight transistors in series with different numbers of input transistors.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: memory subarray 100: Configurable arithmetic unit GBL<0>: global bit line GBLB<0>: global inverse phase element line HWL: Manage Character Lines INBL_0~INBL_3: input bit lines LBL: local bit line LBLB: Local Inverted Bound Line M0-M5, T1~T6: Transistor R_RBL<0>: the first read bit line R01, R11: resistors Rx: external resistor Vdd: High voltage power line VSS: Low Voltage Power Line W0: the first weight bit WBC_1~WBC_n: weight memory cells WL: word line

Claims (16)

A configurable computing unit in a memory, comprising: a first input transistor having a first terminal, a control terminal coupled to a first input bit line, and a second terminal; a first weight transistor having a first end coupled to the second end of the first input transistor, a control end receiving a first weight bit, and a second end coupled to a first readout bit line; a A first resistor, coupled between the first end of the first input transistor and a common signal line; a second input transistor, with a first end, coupled to a second input bit line A control terminal, and a second terminal; a second weight transistor, having a first terminal coupled to the second terminal of the second input transistor, a control terminal receiving the first weight bit, and coupling connected to a second end of the first readout bit line; and a second resistor coupled between the first end of the second input transistor and the common signal line, wherein the second resistor The resistance value of is different from the resistance value of the first resistor. The configurable computing unit according to claim 1, wherein the resistance value of the second resistor is n times the resistance value of the first resistor, and n is a positive integer greater than or equal to 1. The configurable computing unit as described in claim 1, further comprising: a third input transistor having a first end coupled to a third input bit line a control terminal of the third input transistor, and a second terminal; a third weight transistor having a first terminal coupled to the second terminal of the third input transistor, a control terminal receiving the first weight bit, and A second end coupled to a second readout bit line; a third resistor coupled between the first end of the third input transistor and the common signal line; a fourth input transistor , having a first end, a control end coupled to a fourth input bit line, and a second end; a fourth weight transistor, having a first end coupled to the second end of the fourth input transistor one terminal, a control terminal receiving the first weight bit, and a second terminal coupled to the second readout bit line; and a fourth resistor coupled to the fourth input transistor Between the first terminal and the common signal line, wherein the resistance value of the fourth resistor is different from the resistance value of the third resistor. The configurable computing unit as described in claim item 3, wherein the resistance value of the second resistor is n times the resistance value of the first resistor, and the resistance value of the fourth resistor is the third The resistance value of the resistor is n times of 2, and n is a positive integer greater than or equal to 1. The configurable computing unit as described in claim 3, further comprising: a fifth input transistor having a first end, a control end coupled to the first input bit line, and a second end; a first five-weight transistor, with the second end coupled to the fifth input transistor A first end of a first end, a control end receiving a second weight bit, and a second end coupled to the first readout bit line; a fifth resistor, coupled to the fifth input transistor Between the first end and the common signal line; a sixth input transistor having a first end, a control end coupled to the second input bit line, and a second end; a sixth weight Transistor, having a first terminal coupled to the second terminal of the sixth input transistor, a control terminal receiving the second weight bit, and a second terminal coupled to the first readout bit line and a sixth resistor coupled between the first terminal of the sixth input transistor and the common signal line, a seventh input transistor with a first terminal coupled to the third input bit A control terminal and a second terminal of the element line; a seventh weight transistor having a first terminal coupled to the second terminal of the seventh input transistor and a control terminal receiving the second weight bit , and a second end coupled to the second read bit line; a seventh resistor, coupled between the first end of the seventh input transistor and the common signal line; an eighth input A transistor having a first end, a control end coupled to the fourth input bit line, and a second end; an eighth weight transistor having a second end coupled to the eighth input transistor a first terminal, a control terminal receiving the second weight bit, and coupled to the second a second end of the read bit line; and an eighth resistor coupled between the first end of the eighth input transistor and the common signal line, wherein the sixth resistors have different resistance values the resistance value of the fifth resistor, and the resistance value of the eighth resistor is different from the resistance value of the seventh resistor. The configurable computing unit as described in claim item 5, wherein the resistance value of the second resistor is n times the resistance value of the first resistor, and the resistance value of the fourth resistor is the third The resistance value of the resistor is n times of 2, the resistance value of the sixth resistor is n times of the resistance value of the fifth resistor, and the resistance value of the eighth resistor is the first The resistance value of the seven resistors is n times of 2, and n is a positive integer greater than or equal to 1. The configurable computing unit as described in claim item 5, wherein the resistance value of the fifth resistor is n times the resistance value of the first resistor, and the resistance value of the sixth resistor is the second The resistance value of the resistor is n times of 2, the resistance value of the seventh resistor is n times of the resistance value of the third resistor, and the resistance value of the eighth resistor is the first The resistance value of the four resistors is n times of 2, and n is a positive integer greater than or equal to 1. The configurable arithmetic unit as claimed in claim 5, wherein the ratio of the resistance value of the second resistor to the resistance value of the first resistor is different from the resistance value of the sixth resistor to the resistance of the fifth resistor and the ratio of the resistance value of the fourth resistor to the resistance value of the third resistor is different from the resistance value of the eighth resistor to the resistance value of the seventh resistor. A configurable operation unit in a memory, comprising: a first weight transistor, having a first end coupled to a first readout bit line, a control end receiving a first weight bit, and a first Two terminals; at least one first input transistor, having a first terminal coupled to the second terminal of the first weight transistor, a control terminal coupled to a first input bit line, and a common signal coupled a second end of the line; and at least one second input transistor having a first end coupled to the second end of the first weight transistor, a control end coupled to a second input bit line, and Coupling to a second end of the common signal line; wherein the quantity of the at least one first input transistor is different from the quantity of the at least one second input transistor. The configurable computing unit as described in Claim 9, wherein the number of the at least one second input transistor is the nth power of 2 the number of the at least one first input transistor, and n is a positive integer greater than or equal to 1 . The configurable computing unit as described in Claim 9, further comprising: a second weight transistor, having a first end coupled to a second readout bit line, and a control end receiving the first weight bit , and a second end; at least one third input transistor, having a first end coupled to the second end of the second weight transistor, a control end coupled to a third input bit line, and coupled connected to a second end of the common signal line; and at least one fourth input transistor having a first end coupled to the second end of the second weight transistor, a fourth input bit line coupled to control terminal, and coupling A second end of the common signal line; wherein the quantity of the at least one third input transistor is different from the quantity of the at least one fourth input transistor. The configurable computing unit as described in claim 11, wherein the number of the at least one second input transistor is n times the number of the at least one first input transistor, and the at least one fourth input transistor The quantity is the nth power times of 2 of the quantity of the at least one third input transistor, and n is a positive integer greater than or equal to 1. The configurable computing unit as described in claim 11, further comprising: a third weight transistor having a first end coupled to the first readout bit line and a control end receiving a second weight bit , and a second end; at least one fifth input transistor, having a first end coupled to the second end of the third weight transistor, a control end coupled to the first input bit line, and a coupling connected to a second end of the common signal line; and at least one sixth input transistor, having a first end coupled to the second end of the third weight transistor, a first end coupled to the second input bit line a control terminal and a second terminal coupled to the common signal line; a fourth weight transistor having a first terminal coupled to the second readout bit line and receiving a control of a second weight bit terminal, and a second terminal; at least one seventh input transistor, having a first terminal coupled to the second terminal of the fourth weight transistor, a control terminal coupled to the third input bit line, and a second terminal coupled to the common signal line; and at least one eighth input transistor having the first terminal coupled to the fourth weight transistor A first end of the two terminals, a control end coupled to the fourth input bit line, and a second end coupled to the common signal line; wherein the number of the at least one fifth input transistor is different from that of the at least one The quantity of the sixth input transistor, and the quantity of the at least one seventh input transistor is different from the quantity of the at least one eighth input transistor. The configurable computing unit as described in claim 13, wherein the number of the at least one second input transistor is n times the number of the at least one first input transistor, and the at least one fourth input transistor The number of the at least one third input transistor is n times the number of 2, and the number of the at least one sixth input transistor is the n times of the number of the at least one fifth input transistor, And the quantity of the at least one eighth input transistor is the nth power times of 2 of the quantity of the at least one seventh input transistor, and n is a positive integer greater than or equal to 1. The configurable computing unit as claimed in item 13, wherein the number of the at least one fifth input transistor is n times the number of the at least one first input transistor, and the at least one sixth input transistor The number of the at least one second input transistor is n times the number of 2, and the number of the at least one seventh input transistor is the n times of the number of the at least one third input transistor, And the quantity of the at least one eighth input transistor is the nth power times of 2 of the quantity of the at least one fourth input transistor, and n is a positive integer greater than or equal to 1. The configurable computing unit according to claim 13, wherein the ratio of the number of the at least one second input transistor to the number of the at least one first input transistor is different from the ratio of the number of the at least one sixth input transistor to the number of the at least one sixth input transistor At least one fifth input power The ratio of the number of crystals, and the ratio of the number of the at least one fourth input transistor to the number of the at least one third input transistor is different from the number of the at least one eighth input transistor to the at least one seventh input transistor the number of crystals.

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