TWI794094B - Method for preparing semiconductor structure having fins - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure having fins. The method includes providing a semiconductor substrate including a plurality of initial fin structures. The method also includes forming an isolation material covering the plurality of initial fin structures. The method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. The method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.

Description

Method for fabricating semiconductor structure with fins

This application claims priority to US Patent Application Nos. 17/573,759 and 17/573,787 (ie, the priority date is "January 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having one or more fins.

With the rapid development of the electronics industry, the development of semiconductor components has achieved high performance and miniaturization. As the dimensions of semiconductor devices, such as dynamic random access memory (DRAM) devices, shrink, the line widths of conductive features within the semiconductor devices also decrease, which may increase manufacturing difficulty and reduce manufacturing yield.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor structure, including a semiconductor substrate and an isolation structure. The semiconductor base includes a first fin. The isolation structure defines the first fins. The isolation structure includes a first portion and a second portion located on two opposite sides of the first fin. The difference between the top surface elevation of the first portion and the top surface elevation of the second portion is greater than 0 and less than about 5 nanometers.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form the plurality of fins. The manufacturing method further includes performing an isotropic etching operation on the isolation material to form an isolation structure to surround the plurality of fins.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method also includes performing a first removal operation on the plurality of initial fin structures and the isolation material to form the plurality of fins and an isolation layer surrounding the plurality of fins. The height difference between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nm. The manufacturing method further includes performing a second removal operation on the isolation layer to form an isolation structure to surround the plurality of fins, wherein the top surface of the isolation structure is about 20° lower than the top surface of the plurality of fins. nm to about 40 nm.

In a method of fabricating a semiconductor structure, forming the fins and defining the isolation structures of the fins includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material, and moreover for removing the isolation material (or part of the isolation layer) to define the fin height wet etch operation. The fluidity of the etchant liquid phase of the wet etch operation may allow the etchant to penetrate small features (eg, an isolated portion between two relatively close fins). As a result, the uniformity of etching is significantly improved, and therefore, the height or amount of isolation between fins that can be etched away is substantially the same as etc., so the uniformity of the height of the formed fins can be significantly improved. In addition, the time for performing wet etching can be relatively short, and over-etching of structures and/or elements other than the isolation material (or isolation layer) can be more prevented.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1: Semiconductor structure

1A-1A': section line

2A-2A': line

2B-2B': line

10: Semiconductor substrate

20: Isolation structure

20A: Isolation material

20A1: Auxiliary line

20B: isolation layer

20C: Isolation structure

30: Conductive element

30A: Groove

3A-3A': line

3B-3B': line

4A-4A': line

4B-4B': line

5A-5A': line

5B-5B': line

70: Preparation method

80: Preparation method

110: fins

110A: Initial fin structure

110A': structure

110a1: Auxiliary line

120: fins

120A: Initial fin structure

120a: top surface

120A': structure

120a1: auxiliary line

130: fins

130A: Initial fin structure

130A': structure

140: fins

140A: Initial fin structure

140A': structure

140a: top surface

150: fins

150A: Initial fin structure

150A': structure

160A: Initial fin structure

170A: Initial fin structure

201B: top surface

201B1: Auxiliary line

210: part

210a: top surface

210C: part

220: part

220a: top surface

220C: part

230: part

230a: top surface

240: part

240a: top surface

D1: difference

D1A: difference

D2: distance

D2A: Distance

D3: Distance

D3A: Distance

D4: Thickness

D5: Elevation difference

D6: Thickness

D7: Thickness

D8: Elevation difference

E1: remove operation

E2: remove operation

HM: patterned hard mask

S71: Operation

S72: Operation

S73: Operation

S74: Operation

S81: Operation

S82: Operation

S83: Operation

S84: Operation

T1: Distance

T1A: Distance

T2: Distance

T2A: Distance

T3: Thickness

T4: Thickness

T3A: Thickness

T4A: Thickness

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components.

FIG. 1 is a top view illustrating a semiconductor structure of some embodiments of the present disclosure.

FIG. 1A is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure.

FIG. 2 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

2A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

2B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

3 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

3A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

3B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

4 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

4A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

4B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

5 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

5A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

5B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

6 is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 7 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 8 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is hereby intended. to any of the described embodiments Any changes or modifications, and any further applications of the principles described herein, should be considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numerals may be repeated throughout the embodiments, but it is not intended that features of one embodiment apply to another, even if they share the same reference numeral.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections, but these elements, components, regions, layers or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1 is a top view illustrating a semiconductor structure 1 of some embodiments of the present disclosure, and FIG. 1A is a cross-sectional view illustrating a semiconductor structure 1 of some embodiments of the present disclosure. In some embodiments, FIG. 1A is a cross-sectional view along line 1A-1A' of FIG. 1 . The semiconductor structure 1 includes a semiconductor substrate 10 , an isolation structure 20 , and one or more conductive elements 30 . It should be understood that some elements may be omitted for clarity.

The semiconductor substrate 10 may include one or more active regions. Semiconductor substrate 10 One or a plurality of fins (eg, fins 110, 120, 130, 140, and 150) may be included. The active region of the semiconductor substrate 10 may include fins and doped regions. The doped regions may be source/drain regions. The number of fins of the semiconductor substrate 10 may vary according to practical applications, and is not limited thereto.

In some embodiments, the fins 110 , 120 , 130 , 140 , and 150 of the semiconductor substrate 10 are adjacent to and defined by the isolation structure 20 . In some embodiments, fins 110 , 120 , 130 , 140 , and 150 are separated from each other by portions of isolation structure 20 . In some embodiments, the distance D2 between the fins 110 and 120 is less than the distance D3 between the fins 120 and 130 . In some embodiments, distance D2A between fin 130 and fin 140 is less than distance D3A between fin 150 and fin 130 . In some embodiments, distance D2 is substantially equal to distance D2A. In some embodiments, distance D3 is substantially equal to distance D3A. Semiconductor substrate 10 may be formed of or include materials such as silicon, doped silicon, silicon germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, phosphide Gallium, arsenic phosphide, indium phosphide, indium gallium phosphide, or any other group IV-IV, III-V or I-VI semiconductor material. In some embodiments, the fins 110, 120, 130, 140, and 150 of the semiconductor substrate 10 may be formed of or include one or more silicon-containing materials, such as silicon, doped silicon, or silicon germanium. .

The isolation structure 20 may define the fins 110 , 120 , 130 , 140 and 150 of the semiconductor substrate 10 . The isolation structure 20 may be formed of or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, isolation structure 20 includes a plurality of portions adjacent to fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, isolation structure 20 includes portion 210 and portion 220 on two opposite sides of fin 120 . In some embodiments, fin 110 is spaced apart from fin 120 by portion 210 of isolation structure 20 . In some embodiments, fins 130 is spaced apart from fin 120 by portion 220 of isolation structure 20 . In some embodiments, the width (eg, distance D2 ) of portion 210 of isolation structure 20 is smaller than the width (eg, distance D3 ) of portion 220 of isolation structure 20 . In some embodiments, the thickness T3 of the portion 210 of the isolation structure 20 is less than the thickness T4 of the portion 220 of the isolation structure 20 .

In some embodiments, the isolation structure 20 further includes a portion 230 and a portion 240 on two opposite sides of the fin 140 . In some embodiments, fin 130 is spaced apart from fin 140 by portion 230 of isolation structure 20 . In some embodiments, fin 150 is spaced apart from fin 140 by portion 240 of isolation structure 20 . In some embodiments, the width of portion 230 of isolation structure 20 (eg, distance D2A) is less than the width of portion 240 of isolation structure 20 (eg, distance D3A). In some embodiments, the thickness T3A of the portion 230 of the isolation structure 20 is less than the thickness T4A of the portion 240 of the isolation structure 20 . In some embodiments, thickness T3 is substantially equal to thickness T3A. In some embodiments, thickness T4 is substantially equal to thickness T4A.

In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is greater than 0 and less than about 5 nm. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 3 nanometers. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 2 nanometers. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 1 nanometer.

In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is greater than 0 and less than about 5 nanometers. In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is equal to or less than about 3 nanometers. In some embodiments, the elevation of the top surface 230a of the portion 230 The difference D1A from the elevation of the top surface 240a of the portion 240 is equal to or less than about 2 nm. In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is equal to or less than about 1 nanometer. In some embodiments, distance D1 is substantially equal to distance D1A.

In some embodiments, the distance T1 between the top surface 120a of the fin 120 and the top surface 210a of the portion 210 of the isolation structure 20 is smaller than the distance T1 between the top surface 120a of the fin 120 and the top surface 220a of the portion 220 of the isolation structure 20 The distance T2. In some embodiments, the elevation of the top surface 210a of the portion 210 is higher than the elevation of the top surface 220a of the portion 220 .

In some embodiments, the distance T1A between the top surface 140a of the fin 140 and the top surface 230a of the portion 230 of the isolation structure 20 is smaller than the distance T1A between the top surface 140a of the fin 140 and the top surface 240a of the portion 240 of the isolation structure 20 The distance T2A. In some embodiments, the elevation of the top surface 230a of the portion 230 is higher than the elevation of the top surface 240a of the portion 240 . In some embodiments, distance T1 is substantially equal to distance T1A. In some embodiments, distance T2 is substantially equal to distance T2A.

The conductive element 30 may be disposed on the semiconductor substrate 10 and the isolation structure 20 . In some embodiments, semiconductor substrate 10 and isolation structure 20 collectively define one or more trenches 30A, and fins 110 , 120 , 130 , 140 , and 150 are in trenches 30A. In some embodiments, conductive elements 30 are disposed on fins 110 , 120 , 130 , 140 , and 150 in trenches 30A. In some embodiments, conductive elements 30 are conformally formed on fins 110 , 120 , 130 , 140 , and 150 in trenches 30A. In some embodiments, the semiconductor structure 1 includes a plurality of conductive elements 30 in a plurality of trenches 30A. In some embodiments, conductive element 30 includes a conductive material, such as doped polysilicon, metal, or metal silicide. The metal can be, for example, aluminum, copper, tungsten, cobalt, or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, the conductive element 30 may be or include a wordline.

In some embodiments, the fin height of fins 110 , 120 , 130 , 140 , and 150 in trench 30A is defined by the difference in elevation between fins 110 , 120 , 130 , 140 , and 150 and isolation structure 20 . According to some embodiments of the present disclosure, portions 210 and The difference D1 in elevation between sections 220 is relatively small, so the height of the fins is relatively uniform. Therefore, the semiconductor structure 1 can avoid including regions where two fins are relatively close to each other, and an isolation portion formed therebetween undesirably reduces the height of the fins. Accordingly, the semiconductor structure 1 (eg, a transistor comprising fins) may have satisfactory performance, eg, have satisfactory switching sensitivity and/or functionality.

2 , 2A, 2B, 3 , 3A, 3B, 4 , 4A, 5 , 5A, and 5B illustrate various stages of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure.

Referring to FIG. 2, FIG. 2A and FIG. 2B, FIG. 2 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 2A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 2B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 2A is a cross-sectional view along line 2A-2A' of FIG. 2 , and FIG. 2B is a cross-sectional view along line 2B-2B' of FIG. 2 .

A semiconductor substrate 10 including a plurality of initial fin structures (eg, initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A) may be provided. The semiconductor substrate 10 can be made of, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, indium phosphide, phosphorus gallium chloride Indium, or any other Group IV-IV, III-V, or I-VI semiconductor material. The number of initial fin structures of the semiconductor substrate 10 may vary according to practical applications, and is not limited thereto.

Photolithography can be performed to pattern the semiconductor substrate 10 to define the positions of the plurality of initial fin structures 110A, 120A, 130A, 140A, 150A, 160A and 170A. Etching may be performed after the lithography process to form a plurality of trenches in the semiconductor substrate 10 .

After being etched to form trenches in semiconductor substrate 10 , isolation material 20A may be formed to cover initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A. The isolation material 20A can be deposited to fill the plurality of trenches of the semiconductor substrate 10 . The isolation material 20A may include, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

A patterned hard mask HM may be disposed on the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10 . A hard mask can be deposited over the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10, which can then be patterned according to a patterned photoresist layer , to form a patterned hard mask HM having a plurality of openings to expose portions of the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10 . The patterned hard mask HM may have a predetermined pattern for forming a plurality of trenches (eg, , followed by the formation of the trench 30A of the conductive element 30, which will be discussed below). The openings of the patterned hard mask HM correspond to trenches (e.g., shaped into the position of the groove 30A) of the conductive element 30.

In some embodiments, the patterned hard mask HM may include a dual anti-reflective coating (DARC), a carbon layer on the DARC, and a nitride layer on the carbon layer. The DARC and carbon layer can be patterned according to a patterned photoresist layer, transferring a predetermined pattern from the patterned photoresist layer to the DARC and carbon layer. Next, the patterned photoresist layer may be removed, and the nitride layer is patterned according to the patterned DARC and patterned carbon layer, transferring a predetermined pattern from the DARC and carbon layer to the nitride layer. In some embodiments, the patterned DARC, the patterned carbon layer, and the patterned nitride layer together constitute the patterned hard mask HM.

In some embodiments, FIG. 2A is a cross-section where the opening of the patterned hard mask HM is located, and FIG. 2B is a cross-section where the patterned hard mask HM is located.

Referring to FIG. 3, FIG. 3A and FIG. 3B, FIG. 3 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 3A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 3B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 3A is a cross-sectional view along line 3A- 3A' of FIG. 3 , and FIG. 3B is a cross-sectional view along line 3B-3B' of FIG. 3 .

The removal operation E1 may be performed on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of trenches 30A. In some embodiments, the removal operation is performed on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of fins (eg, fins 110A) in the trenches 30A. , 120, 130, 140 and 150) and an isolation layer 20B surrounding a plurality of fins. In some embodiments, the elevation difference D5 between the top surface (eg, top surface 120a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 10 nm. in some embodiments Herein, the elevation difference D5 between the top surface (eg, top surface 120 a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 5 nm. In some embodiments, the elevation difference D5 between the top surface (eg, top surface 120a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 3 nm.

In some embodiments, the removal operation E1 may be or include performing an anisotropic etching operation on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of Groove 30A. In some embodiments, the removal operation E1 may be or include performing an anisotropic etching operation on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form Fins 110, 120, 130, 140 and 150 are formed in 30A.

In some embodiments, the anisotropic etch operation is performed according to the patterned hard mask HM. In some embodiments, the anisotropic etching operation includes a dry etching operation. In some embodiments, the dry etching process includes, for example, plasma etching or reactive ion etching. In some embodiments, the dry etching process may use HBr and O2 as etching gases. In some embodiments, the dry etching process may use CF4/O2/Ar as the etching gas. In some embodiments, an anisotropic etch operation removes portions of initial fin structures 110A, 120A, 130A, 140A, and 150A to form fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the anisotropic etch operation removes a portion of isolation material 20A to form isolation layer 20B.

As shown in FIG. 3A , auxiliary line 20A1 may indicate the elevation or location of the top surface of isolation material 20A prior to removal operation E1, while auxiliary lines 110a1 and 120a1 may indicate the elevation or location of the top surface of initial fin structures 110A and 120A. . In some embodiments, the portion of isolation material 20A removed by removal operation E1 has a thickness D6. In some embodiments, the portion of the initial fin structure 110A removed by removal operation E1 and the initial fin structure removed by removal operation E1 Portion 120A has thickness D4.

As shown in FIG. 3B , after removal operation E1 , the remainder of the initial fin structures 110A, 120A, 130A, 140A, and 150A under the patterned hard mask HM may form structures 110A′, 120A′, 130A′ , 140A' and 150A'.

Referring to FIG. 4, FIG. 4A and FIG. 4B, FIG. 4 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 4A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 4B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 4A is a cross-sectional view along line 4A-4A' of FIG. 4 and FIG. 4B is a cross-sectional view along line 4B-4B' of FIG. 4 .

The removal operation E2 may be performed on the isolation layer 20B to form the isolation structure 20 surrounding the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, the top surface of the isolation structure 20 is about 20 nm to about 40 nm lower than the top surface of the fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the top surface of isolation structure 20 is about 25 nm to about 35 nm lower than the top surface of fins 110 , 120 , 130 , 140 , and 150 .

In some embodiments, the elevation difference D5 between the top surfaces of the fins 110 , 120 , 130 , 140 , and 150 and the top surface 201B of the isolation layer 20B is less than about 5 nm prior to the removal operation E2 . In some embodiments, the top surface of the isolation structure 20 is lower than the top surfaces of the plurality of fins 110 , 120 , 130 , 140 and 150 by about 20 nm to about 40 nm after the removal operation E2 . In some embodiments, the top surface of the isolation structure 20 is lower than the top surfaces of the plurality of fins 110 , 120 , 130 , 140 and 150 by about 25 nm to about 35 nm after the removal operation E2 .

In some embodiments, the removing operation E2 may be or include performing an isotropic etching operation on the isolation layer 20B to form the isolation structure 20 . In some embodiments, isotropy The etching operation includes a wet etching operation. In some embodiments, the etchant of the wet etching operation includes a fluorine-containing etchant. In some embodiments, hydrofluoric acid is used as an etchant in wet etching operations. In some embodiments, dilute hydrofluoric acid (DHF 200:1) is used as the etchant for the wet etching operation. In some embodiments, the wet etching operation (ie, removal operation E2 ) is highly selective to fins 110 , 120 , 130 , 140 , and 150 relative to isolation layer 20B. In some embodiments, fins 110 , 120 , 130 , 140 , and 150 are hardly or even substantially not removed or etched by removal operation E2 .

In some embodiments, the isotropic etching operation (ie, removal operation E2 ) removes a portion of the isolation layer 20B to form the isolation structure 20 exposing the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for about 10 seconds to about 40 seconds. In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for about 20 seconds to about 30 seconds. In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for less than about 60 seconds. In some embodiments, the execution time of the isotropic etching operation (ie, removal operation E2 ) is shorter than that of the anisotropic etching operation (ie, removal operation E1 ). In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed long enough to determine the fin heights of the fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for a period of time short enough to prevent over-etching of structures and/or elements other than isolation layer 20B.

In some embodiments, the removal operation E2 is performed after the removal operation E1. In some embodiments, the anisotropic etching operation (ie, removal operation E2 ) is performed after the anisotropic etching operation (ie, removal operation E1 ). In some embodiments, both anisotropic etching operation (ie, removal operation E1 ) and isotropic etching operation (ie, removal operation E2 ) are performed according to the patterned hard mask HM.

As shown in FIG. 4A , the auxiliary line 201B1 may indicate the elevation or position of the top surface of the isolation layer 20B before the removal operation E2. In some embodiments, the portion of isolation layer 20B removed by removal operation E2 has a thickness D7. In some embodiments, thickness D7 is about 20 nm to about 40 nm. In some embodiments, thickness D7 is about 25 nm to about 35 nm. In some embodiments, the thickness D7 is substantially equal to a predetermined fin height. In some embodiments, removal operation E2 removes a portion of isolation layer 20B, determining the fin heights of fins 110 , 120 , 130 , 140 , and 150 in trenches 30A.

Referring to FIG. 5, FIG. 5A and FIG. 5B, FIG. 5 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 5A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method, and FIG. 5B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 5A is a cross-sectional view along line 5A-5A' of FIG. 5 and FIG. 5B is a cross-sectional view along line 5B-5B' of FIG. 5 .

In some embodiments, one or a plurality of conductive elements 30 may be formed on the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, one or a plurality of conductive elements 30 may be formed on the fins 110 , 120 , 130 , 140 and 150 in the trench 30A. In some embodiments, one or a plurality of conductive elements 30 may be formed on the isolation structure 20 of the trench 30A.

According to some embodiments of the present disclosure, the removal operation E1 includes an isotropic etching operation (or an directional operation), so that the fins and isolation layers can form an Top surfaces of substantially the same elevation. Therefore, removal operation E2 can be used to precisely define the height of the fin.

Furthermore, according to some embodiments of the present disclosure, the removal operation E2 includes an isotropic Therefore, the fluidity of the liquid phase of the etchant allows the etchant to penetrate small features (eg, the isolation between two relatively close fins). Therefore, the uniformity of etching is significantly improved, so the height or quantity of the isolation portions between the fins that can be etched away is substantially equal, and thus the uniformity of the height of the formed fins can be significantly improved.

Furthermore, according to some embodiments of the present disclosure, the formation of the fin and isolation structures includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material and further for removing the isolation material (or isolation layer) in a wet etch operation that defines the height of the fin. Therefore, since the wet etching operation is only responsible for removing a relatively small portion of the isolation material (or isolation layer) to determine the height of the fin, the time for performing the wet etching can be relatively short, and it can also prevent the isolation material (or isolation layer). layer) and/or overetching of elements other than

6 is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

In some embodiments, after performing the removal operation E1, an additional removal operation E1 (for example, an anisotropic etching operation) is performed on the structure shown in FIG. 3 , FIG. 3A and FIG. 3B , instead of performing An isotropic operation (or removal operation E2 ), the isolation structure 20C may be formed, and the isolation structure 20C includes a portion 210C and a portion 220C on opposite sides of the fin 120 . In some embodiments, the difference in elevation D8 between the top surface of portion 210C and the top surface of portion 220C may be relatively large due to loading effects. Although the fin height of fins 110 and 120 defined by portion 210C of isolation structure 20C is relatively short, the transistors comprising fins 110 and 120 may be turned on unexpectedly when a relatively low voltage is applied, or Even some negative charges pass between fins 110 and 120 . Therefore, semiconductor structures (eg, transistors including fins 110 and 120) formed by a method including the stages shown in FIG. 6 may not have satisfactory performance, eg, low switching sensitivity

FIG. 7 is a flowchart illustrating a method 70 of fabricating a semiconductor structure according to some embodiments of the present disclosure.

The fabrication method 70 begins with operation S71, wherein a semiconductor substrate including a plurality of initial fin structures is provided.

The manufacturing method 70 proceeds to operation S72, wherein an isolation material covering the plurality of initial fin structures is formed.

The fabrication method 70 proceeds to operation S73 , wherein an anisotropic etching operation is performed on the isolation material and the plurality of initial fin structures to form the plurality of fins.

The fabrication method 70 continues with operation S74 , wherein an isotropic etching operation is performed on the isolation material to form an isolation structure surrounding the plurality of fins.

The preparation method 70 is just an example, and is not intended to limit the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 70, and some of the operations described may be replaced, eliminated, or moved for use in other embodiments of the method. In some embodiments, preparation method 70 may also include operations not depicted in FIG. 7 . In some embodiments, preparation method 70 may include one or more of the operations described in FIG. 7 .

FIG. 8 is a flowchart illustrating a method 80 of fabricating a semiconductor structure according to some embodiments of the present disclosure.

The fabrication method 80 begins with operation S81, wherein a semiconductor substrate including a plurality of initial fin structures is provided.

The manufacturing method 80 continues with operation S82, wherein an isolation material covering the plurality of initial fin structures is formed.

The preparation method 80 proceeds to operation S83, wherein for the plurality of initial fin junctions A first removal operation is performed on the structure and isolation material to form a plurality of fins and an isolation layer surrounding the plurality of fins. In some embodiments, the difference in elevation between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nanometers

The manufacturing method 80 continues with operation S84 , wherein a second removal operation is performed on the isolation layer to form an isolation structure surrounding the plurality of fins. In some embodiments, the top surface of the isolation structure is about 20 nm to about 40 nm lower than the top surface of the plurality of fins.

The preparation method 80 is merely an example, and is not intended to limit the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 80, and some of the operations described may be replaced, eliminated, or moved for use in other embodiments of the method. In some embodiments, preparation method 80 may also include operations not depicted in FIG. 8 . In some embodiments, preparation method 80 may include one or more of the operations described in FIG. 8 .

One aspect of the present disclosure provides a semiconductor structure, including a semiconductor substrate and an isolation structure. The semiconductor base includes a first fin. The isolation structure defines the first fin. The isolation structure includes a first portion and a second portion located on two opposite sides of the first fin. The difference between the top surface elevation of the first portion and the top surface elevation of the second portion is greater than 0 and less than about 5 nanometers.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form the plurality of fins. The manufacturing method further includes performing an isotropic etching operation on the isolation material to form an isolation structure to surround the plurality of fins.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method also includes performing a first removal operation on the plurality of initial fin structures and the isolation material to form the plurality of fins and an isolation layer surrounding the plurality of fins. The height difference between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nm. The manufacturing method further includes performing a second removal operation on the isolation layer to form an isolation structure to surround the plurality of fins, wherein the top surface of the isolation structure is about 20° lower than the top surface of the plurality of fins. nm to about 40 nm.

In a method of fabricating a semiconductor structure, forming the fins and defining the isolation structures of the fins includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material, and moreover for removing the isolation material (or part of the isolation layer) to define the fin height wet etch operation. The fluidity of the etchant liquid phase of the wet etch operation may allow the etchant to penetrate small features (eg, an isolated portion between two relatively close fins). Therefore, the uniformity of etching is significantly improved, and therefore, the height or amount of the isolation portions between the fins that can be etched away is substantially equal, and thus the uniformity of the height of the formed fins can be significantly improved. In addition, the time for performing wet etching can be relatively short, and over-etching of structures and/or elements other than the isolation material (or isolation layer) can be more prevented.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. skill of the craft Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future development processes, machinery, manufacturing, and material compositions that have the same function or achieve substantially the same results as the corresponding embodiments described herein according to this disclosure. , means, method, or steps. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

1: Semiconductor structure

10: Semiconductor substrate

20: Isolation structure

30: Conductive element

110: fins

120: fins

120a: top surface

130: fins

130A: Initial fin structure

140: fins

140a: top surface

150: fins

210: part

210a: top surface

220: part

220a: top surface

230: part

230a: top surface

240: part

240a: top surface

D1: difference

D1A: difference

D2: distance

D2A: Distance

D3: Distance

D3A: Distance

T1: Distance

T1A: Distance

T2: Distance

T2A: Distance

T3: Thickness

T4: Thickness

T3A: Thickness

T4A: Thickness

Claims (10)

A method for preparing a semiconductor structure, comprising: providing a semiconductor substrate, including a plurality of initial fin structures; forming an isolation material to cover the plurality of initial fin structures; performing a process on the plurality of initial fin structures and the isolation material. A first removal operation to form a plurality of fins and an isolation layer surrounding the plurality of fins, wherein the difference in elevation between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nanometers and performing a second removal operation on the isolation layer to form an isolation structure to surround the plurality of fins, wherein the top surface of the isolation structure is lower than the top surface of the plurality of fins by about 20 nm to about 40 nm. The method of claim 1, wherein before the second removing operation, the difference in elevation between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 5 nm. The method of claim 1, wherein the top surface of the isolation structure is lower than the top surfaces of the plurality of fins by about 25 nm to about 35 nm after the second removal operation. The manufacturing method according to claim 1, wherein the first removal operation includes a dry etching operation, and the second removal operation includes a wet etching operation. The manufacturing method according to claim 1, wherein the first removal operation includes an anisotropic etching operation, and the second removal operation includes an isotropic etching operation. The preparation method according to claim 1, wherein the second removing operation is performed after the first removing operation. The preparation method as claimed in claim 5, wherein the second removing operation is performed for about 10 seconds to about 40 seconds. The preparation method as claimed in item 7, wherein the second removing operation is performed for about 20 seconds to about 30 seconds. The manufacturing method as claimed in claim 1, wherein the semiconductor substrate includes silicon, and the isolation material includes silicon oxide. The manufacturing method as claimed in claim 1, further comprising: forming a conductive element on the plurality of fins and the isolation structure.

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