TWI793377B - Resistive random-access memory circuit - Google Patents

Abstract

A resistive random-access memory circuit includes a switching transistor and a variable resistance element. The switching transistor has a first end coupled to a source line, a second end coupled to the external power line, and a control end coupled to a word line. The variable resistance element has a first end coupled to the second end of the switch transistor and a second end coupled to a bit line. When the set current of the variable resistance element is higher than a maximum providing current of the switching transistor, the external power line is coupled to an external power supply circuit when the variable resistance element is set; when the reset current of the variable resistance element is higher than the maximum providing current of the switching transistor, the external power line is coupled to the external power supply circuit when the variable resistance element is reset.

Description

resistive memory circuit

The present invention relates to a memory circuit, and in particular to a resistive memory circuit.

The application of non-volatile memory is more and more extensive: including large-scale data centers, mobile devices, small storage devices, new types of certificates and subscriber identity module (Subscriber Identity Module, SIM) card. Among non-volatile memories, resistive memory (RRAM) is the next-generation memory, because of its fast read and write speed, long life, small single-bit size, and the opportunity to be used in flexible electronic devices. However, when the resistive memory is applied to the display panel, due to the manufacturing process of the display panel, it may not be able to provide enough current, so that the resistive memory may not be able to be driven. Therefore, how to drive the resistive memory normally in the display panel has become a novel subject.

The invention provides a resistive memory circuit, which can make resistive memory body is normally driven in the display panel.

The resistive memory circuit of the present invention includes a switch transistor and a variable resistance element. The switching transistor has a first end coupled to the source line, a second end coupled to the external power line, and a control end coupled to the word line. The varistor element has a first end coupled to the second end of the switch transistor, and a second end coupled to the bit line. When the setting current of the varistor element is higher than the maximum supply current of the switching transistor, the external power line is coupled to the external power supply circuit when setting the varistor element; when the reset current of the varistor element is higher than the maximum supply current of the switching transistor When the current is flowing, the external power line is coupled to the external power circuit when the varistor element is reset.

Based on the above, in the resistive memory circuit of the embodiment of the present invention, when the setting current or reset current of the variable resistance element is large, enough current can be provided through the external power supply circuit, so that the variable resistance memory circuit in the resistive memory circuit The resistive element can be normally driven without being limited by the switching transistor which is a thin film transistor.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

100: memory array

110_1~110_4: resistive memory circuit

210: Substrate

220: lower electrode layer

230: resistance layer

240: barrier layer

250: Upper electrode layer

BL: bit line

L _X : External power cord

R: variable resistance element

SL: source line

T: switching transistor

V _B1 , V _B2 : bit line control voltage

V _S1 , V _S2 : source control voltage

V _W1 , V _W2 : word line selection voltage

V _X1 ~V _X4 : external power supply voltage

WL: character line

FIG. 1 is a schematic circuit diagram of a memory array according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of an impedance element according to an embodiment of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or components, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

FIG. 1 is a schematic circuit diagram of a memory array according to an embodiment of the present invention. Please refer to FIG. 1. In this embodiment, memory array 100 includes resistive memory circuits (such as 110_1~110_4) in multiple array rows, multiple source lines SL, multiple word word lines WL, multiple bit line BL and a plurality of external power lines L _X . Resistive memory circuits (such as 110_1~110_4) each include a switching transistor T and a varistor element R, wherein the switching transistor T can be a thin-film transistor (Thin-Film Transistor, TFT), and the varistor element R can be a metal - Insulator-metal (Metal-insulator-metal, MIM) components.

During programming (such as setting or resetting) and erasing, the source line SL, the word line WL and the bit line BL can be coupled to the control circuit (or driver, not shown) to receive the corresponding control voltage (or signal), for example, the source line SL can receive the corresponding source control voltage V _S1 , V _S2 , the word line WL can receive the corresponding word line selection voltage V _W1 , V _W2 , and the bit line BL can receive the corresponding The bit line control voltages V _B1 , V _B2 , and the external power line L _X can be coupled to an external power circuit (not shown) to receive the corresponding external power voltage V _X1 ~ V _X4 , that is, from the external power circuit (not shown) receives a corresponding driving current. During data reading, the source line SL and the word line WL can be coupled to the control circuit (or driver, not shown) to receive the corresponding control voltage (or signal), and the bit line BL can be coupled to The sense amplifier circuit converts the data voltage on the bit line BL into a corresponding logic level and outputs it to the outside.

In this embodiment, the switching transistor T has a first end coupled to the source line SL, a second end coupled to the external power line _LX , and a control end coupled to the word line WL. The variable resistance element R has a first end coupled to the second end of the switching transistor T, and a second end coupled to the bit line BL. When the variable resistance element R is set to a high impedance state, a set voltage can be provided to both ends of the variable resistance element R, and when the variable resistance element R is reset to a low impedance state, a reset voltage can be provided to both ends of the variable resistance element R , where the polarity of the set voltage is opposite to the reset voltage. For example, when the set voltage is positive, the reset voltage can be negative; when the set voltage is negative, the reset voltage can be positive.

In addition, when the setting current of the variable resistance element R is higher than the maximum current provided by the switching transistor T, the external power line _LX is coupled to an external power supply circuit (not shown) when setting the variable resistance element R; When the setting current of R is less than or equal to the maximum supply current of the switching transistor T, the external power line _LX will not be coupled to the external power supply circuit (not shown) when setting the variable resistance element R, that is, the external power line _LX is automatically The external power supply circuit is disconnected. When the reset current of the varistor element R is higher than the maximum supply current of the switching transistor T, the external power line _LX is coupled to an external power supply circuit (not shown) when the varistor element R is reset; when the varistor element When the reset current of R is less than or equal to the maximum current provided by the switching transistor T, the external power line _LX will not be coupled to the external power circuit (not shown) when resetting the varistor element R, that is, the external power line L _X is disconnected from the external power supply circuit.

Wherein, the setting current is used to set the variable resistance element R, and the reset current is used to reset the variable resistance element R. Moreover, the maximum supply current of the switching transistor T can be understood as the maximum current that the switching transistor T can provide when the switching transistor T is turned on under the control of the corresponding word line selection voltage (such as V _W1 , V _W2 ). current. In an embodiment, the set current value of the varistor element R, the reset current value of the varistor element R, and the maximum supply current value of the switching transistor T can be stored in an external power circuit (not shown) or its Correspondingly control internal storage elements (such as memory, registers, etc.) of the control circuit (not shown) to determine whether the external power line _LX is coupled to the external power circuit (not shown).

For example, the resistive memory circuit 110_4 is taken as an example below. When the setting current of the variable resistance element R is higher than the maximum supply current of the switching transistor T and the variable resistance element R is set, the corresponding word line selection voltage V _W2 can be enabled to turn on the switching transistor T, and the corresponding external power line L _X is coupled to an external power supply circuit (not shown) to receive the corresponding external power supply voltage V _X4 , and the corresponding bit line BL is coupled to the control circuit (or driver, not shown) to receive the corresponding bit line The control voltage V _B2 , wherein the external power supply voltage V _X4 and the bit line control voltage V _B2 are used to form the setting voltage. At this time, the setting current flows through the external power supply circuit (not shown), the variable resistance element R and the control circuit (or driver, not shown). Moreover, the source control voltage V _S2 received by the corresponding source line SL may be substantially equal to the external power supply voltage V _X4 , or the corresponding source line SL may not receive the source control voltage V _S2 (that is, floating).

When the set current of the variable resistance element R is less than or equal to the maximum supply current of the switching transistor T and the variable resistance element R is set, the corresponding word line selection voltage V _W2 can be enabled to turn on the switching transistor T, and the corresponding source line SL is coupled to the control circuit (or driver, not shown) to receive the corresponding source control voltage V _S2 , and the corresponding bit line BL is coupled to the control circuit (or driver, not shown) to receive the corresponding bit The bit line control voltage V _B2 , wherein the source control voltage V _S2 and the bit line control voltage V _B2 are used to form a set voltage. At this time, the corresponding external power line _LX may not be coupled to an external power circuit (not shown) (that is, the corresponding external power line _LX is floating), so that the corresponding external power line _LX will not receive external supply voltage V _X4 .

When the reset current of the varistor element R is higher than the maximum supply current of the switch transistor T and the varistor element R is reset, the corresponding word line selection voltage V _W2 can be enabled to turn on the switch transistor T, and the corresponding external The power line L _X is coupled to an external power circuit (not shown) to receive the corresponding external power voltage V _X4 , and the corresponding bit line BL is coupled to the control circuit (or driver, not shown) to receive the corresponding bit The bit line control voltage V _B2 , wherein the external power supply voltage V _X4 and the bit line control voltage V _B2 are used to form the reset voltage. At this time, the reset current flows through the external power circuit (not shown), the variable resistance element R and the control circuit (or driver, not shown). Moreover, the source control voltage V _S2 received by the corresponding source line SL may be substantially equal to the external power supply voltage V _X4 , or the corresponding source line SL may not receive the source control voltage V _S2 (that is, floating).

When the reset current of the varistor element R is less than or equal to the maximum supply current of the switch transistor T and the varistor element R is reset, the corresponding word line selection voltage V _W2 can be enabled to turn on the switch transistor T, and the corresponding source The pole line SL is coupled to the control circuit (or driver, not shown) to receive the corresponding source control voltage V _S2 , and the corresponding bit line BL is coupled to the control circuit (or driver, not shown) to receive the corresponding The bit line control voltage V _B2 , wherein the source control voltage V _S2 and the bit line control voltage V _B2 are used to form the reset voltage. At this time, the corresponding external power line _LX may not be coupled to an external power circuit (not shown) (that is, the corresponding external power line _LX is floating), so that the corresponding external power line _LX will not receive external supply voltage V _X4 .

In this way, when the set current or reset current of the variable resistance element R is greater than the maximum current provided by the switching transistor T, enough current can be provided through the external power supply circuit to make the resistive memory circuit (such as 110_1~110_4 ) can be normally driven without being limited by the switching transistor T which is a thin film transistor.

FIG. 2 is a schematic cross-sectional view of an impedance element according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2 , in this embodiment, the varistor element R includes a lower electrode layer 220 , a resistance layer 230 , a barrier layer 240 and an upper electrode layer 250 . The lower electrode layer 220 is formed on the substrate 210 as a part of the external power line _LX , wherein the substrate 210 may be a glass substrate. The resistance layer 230 is formed on the lower electrode layer 220 . The barrier layer 240 is formed on the resistive layer 230 . The upper electrode layer 250 is formed on the barrier layer 240 as a part of the bit line BL.

In an embodiment of the present invention, the material of the upper electrode layer 250 includes molybdenum (Mo), the material of the barrier layer 240 includes aluminum oxide (Al ₂ O ₃ ), the material of the resistance layer 230 includes indium gallium zinc oxide (IGZO) and One of titanium oxide (TiO ₂ ), the material of the lower electrode layer 220 includes one of indium tin oxide (ITO) and titanium (Ti). At this time, the reset current of the varistor element R is higher than the set current of the varistor element R.

In an embodiment of the present invention, the material of the upper electrode layer 250 includes indium tin oxide (ITO), the material of the barrier layer 240 includes aluminum oxide (Al ₂ O ₃ ), and the material of the resistance layer 230 includes indium gallium zinc oxide (IGZO ) and titanium oxide (TiO ₂ ), the material of the lower electrode layer 220 includes aluminum (Al). At this time, the set current of the varistor element R is higher than the reset current of the varistor element R.

In one embodiment of the present invention, the upper electrode layer 250 has a thickness of about 1900 Å, the barrier layer 240 has a thickness of about 150 Å, the resistance layer 230 has a thickness of about 220 Å, and the lower electrode layer 220 has a thickness of about 750 Å.

To sum up, in the resistive memory circuit of the embodiment of the present invention, when the set current or reset current of the rheostat element is relatively large, it can be provided by an external power supply circuit. Enough current, so that the variable resistance element in the resistive memory circuit can be driven normally, without being limited by the switching transistor which is a thin film transistor.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: memory array

110_1~110_4: resistive memory circuit

BL: bit line

L _X : External power cord

R: variable resistance element

SL: source line

T: switching transistor

V _B1 , V _B2 : bit line control voltage

V _S1 , V _S2 : source control voltage

V _W1 , V _W2 : word line selection voltage

V _X1 ~V _X4 : external power supply voltage

WL: character line

Claims (3)

A resistive memory circuit, comprising: a switch transistor, having a first end coupled to a source line, a second end coupled to an external power line, and a control end coupled to a word line; and a varistor element, having a first end coupled to the second end of the switch transistor, and a second end coupled to a bit line; when a set current of the varistor element is higher than the switch voltage When the crystal provides a maximum current, the external power line is coupled to an external power supply circuit when setting the varistor element, when the reset current of the varistor element is higher than the maximum supply current of the switching transistor, The external power line is coupled to the external power circuit when the varistor element is reset, wherein the switching transistor is a thin film transistor (TFT), and the varistor element is a metal-insulator-metal (Metal-insulator -metal, MIM) element, wherein the varistor element includes: a lower electrode layer formed on a substrate as part of the external power line; a resistance layer formed on the lower electrode layer; a barrier layer, formed on the resistance layer; and an upper electrode layer, formed on the barrier layer, as a part of the bit line, wherein when the material of the upper electrode layer includes molybdenum (Mo), the barrier The material of the layer includes aluminum oxide (Al ₂ O ₃ ), the material of the resistance layer includes one of indium gallium zinc oxide (IGZO) and titanium oxide (TiO ₂ ), and the material of the lower electrode layer includes indium tin oxide (ITO ) and titanium (Ti), the reset current of the varistor element is higher than the set current of the varistor element, wherein when the material of the upper electrode layer includes indium tin oxide (ITO), the barrier layer When the material of the resistive layer includes aluminum oxide (Al ₂ O ₃ ), the material of the resistance layer includes one of indium gallium zinc oxide (IGZO) and titanium oxide (TiO ₂ ), and the material of the lower electrode layer includes aluminum (Al), The set current of the varistor element is higher than the reset current of the varistor element, wherein the maximum current that the switching transistor can provide, the value of the set current of the varistor element, the reset current of the varistor element The value of the setting current and the value of the highest supply current of the switching transistor are stored in an external power supply circuit or an internal storage element in a corresponding control circuit to determine whether the external power supply line is coupled to the external power supply circuit , wherein the internal storage element includes at least one of a memory and a temporary register, and wherein when the setting current of the varistor element is less than or equal to the maximum supply current of the switching transistor, the external power line is at When setting the varistor element, it is disconnected from the external power supply circuit. When the reset current of the varistor element is less than or equal to the maximum supply current of the switching transistor, the external power line automatically resets the varistor element. The external power supply circuit is disconnected. The resistive memory circuit as described in item 1 of the scope of the patent application, wherein the substrate is a glass substrate. The resistive memory circuit described in claim 1, wherein the setting current is used to set the varistor element to a high impedance state, and the reset current is used to reset the varistor element to a low impedance state.

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