TWI792692B - Tristate high voltage switch circuit - Google Patents

Abstract

A tristate high voltage switch circuit is provided, including a charge pump having an input receiving a first voltage source, an output coupled to a first node and an enable end receiving a select signal including a first and a second signals; a first switch having a first end coupled to ground and a second end coupled to the first node; a second switch having a first end coupled to a second voltage source and a second end coupled to the first node; and a first first-type transistor having a gate coupled to the first node, a first source/drain end, and a second source/drain end coupled to a word line.

Description

Three-state high voltage switch circuit

The present invention relates to a high-voltage switch circuit, and in particular to a three-state high-voltage switch circuit.

FIG. 1A is a circuit diagram of a conventional high voltage switch circuit, and FIG. 1B is an operation waveform diagram of FIG. 1A . The high voltage switch circuit 10 includes a charge pump CP1, a local boost capacitor C2 and other components. When the selection signal SEL is at the low level L, the voltage of the node PASV will be grounded. When the selection signal SEL is at the high level H, the output node PASV will provide enough high voltage V _{PP_G1H} to turn on the transistor N1. Initially, node X1 (coupled to voltage source V _PP ) causes node G1 of charge pump CP1 to be at voltage V _{PP — G1L} . When the clock signal CK1 changes to a high level (ie V _M ), the node G1 starts to rise to V _{PP_G1H} . At the same time, the clock signal CK2 changes to a low level. At this time, although the voltage of the node PASV drops due to the coupling effect of the area accelerating capacitor C2, the voltage of the node G1 rises and the transistor N3 is turned on, so that the node PASV returns to the potential V _{PP_G2L} . When the voltage at node PASV drops, transistor N2 is still turned on. Node X1 will be affected by the reverse current from node G1. When the clock signal CK2 changes to a high level, the node PASV rises to the voltage V _{PP_G2H} through the coupling effect of the capacitor C2 . At the same time, the clock signal CK1 changes to a low level and the voltage of the node G1 is affected by the coupling effect of the capacitor C1. As a result, node G1 finally reaches potential V _{PP — G1L} via transistor N2 .

FIG. 2 shows a conceptual diagram of a high voltage switch and a memory array. As shown in FIG. 2 , the memory array side includes a plurality of word lines LWL[n], select gate lines SGD, SGS, global bit lines GBL, source lines SL, and the like. In addition, the node PASV of the high-voltage switch circuit is coupled to the drive transistors at the memory array end, such as transistor N0 and transistor N[n+1] for driving the select gate line SGD and SGS, and drive word line LWL[n ] Transistor N[n]. The P wells of the transistors connected to the select gate lines SGD, SGS and the word line LWL[n] are connected together, that is, the common P well CPW. The voltage of the node PASV of the high-voltage switch circuit can be provided to drive transistors N0, N[n], N[n+1], etc., to select the desired memory cell on the word line for reading, programming and erasing operations .

In the high-voltage switching circuit shown in Figure 1, when the transistor N2 is turned on, often because the node G1 is at a high voltage, a reverse current will be generated from the charge pump CP1 and flow to the node PASV, which will also cause the node PASV to collapse. effect, causing adverse effects on the operation of high voltage switching circuits.

Therefore, how to improve the problems of reverse current and breakdown, and how to make the high-voltage switch circuit operate in different modes has become a subject of the high-voltage switch circuit.

Based on the above description, the present invention can provide a tri-state high-voltage switch circuit, which can operate in different modes, and can prevent the effect of the charge pump on the reverse current reduction and crash protection of its output node.

According to an embodiment of the present invention, a three-state high-voltage switch circuit is provided. A three-state high-voltage switch circuit includes: a charge pump having an input terminal, an output terminal and an enable terminal, wherein the enable terminal is used to receive a selection signal, and the input The end receives a first voltage source, the output end is coupled to the first node, the selection signal includes a first selection signal and a second selection signal; the first switch has a first end and a second end, and the first The end is coupled to ground, the second end is coupled to the first node; the second switch has a first end and a second end, the first end is coupled to a second voltage source, and the second terminal coupled to the first node, wherein the first voltage source is greater than the second voltage source; and a first first-type transistor having a gate, a first source-drain terminal, and a second source-drain terminal, The gate is coupled to the first node, the second source-drain terminal is coupled to a word line, wherein, based on the first selection signal and the second selection signal, the tri-state high voltage switch The circuit operates in a disabled mode when the first switch is on and the second switch is off, and the charge pump receives the Operates in charge pump mode when enabled by the selection signal, and operates in amplifier mode when the first switch is off and the second switch is on.

According to an embodiment, the tri-state high voltage switch circuit further includes a crash protection circuit disposed between the first node and the input terminal of the charge pump. According to an embodiment, the three-state high-voltage switch circuit further includes a reverse current reduction circuit, and the collapse The collapse protection circuit is coupled and disposed on the input end of the charge pump. According to an embodiment, the reverse current reducing circuit is coupled to the input terminal of the charge pump via a second first-type transistor.

According to an embodiment, the charge pump of the tri-state high voltage switch circuit further includes: an inverter having an input terminal and an output terminal, wherein the output terminal outputs a first clock signal, and the input terminal receives a second clock signal; The fourth first-type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the second source/drain terminal is coupled to the gate; the fifth first-type transistor , having a gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the first node, and the second source/drain terminal is connected to the gate coupled and coupled to the first source/drain terminal of the fourth first-type transistor N4; the first capacitor C1 has a first terminal and a second terminal, wherein the first terminal is coupled to the The output terminal of the inverter I1, the second terminal is coupled to the gate of the fourth first-type transistor N4; and the second capacitor C2 has a first terminal and a second terminal, Wherein the first terminal is coupled to the input terminal of the inverter I1, and the second terminal is coupled to the gate of the fifth first-type transistor N5. Wherein the charge pump receives the selection signal and the clock signal, and generates the second clock signal through a logic circuit.

According to an embodiment, the tri-state high-voltage switch circuit further includes a crash protection circuit, and the crash protection circuit further includes: a first second-type transistor having a gate, a first source/drain terminal, and a second source/drain terminal, Wherein the gate is coupled to the first source/drain terminal and the second source/drain terminal of the fourth first type transistor; the second second type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the gate is coupled To the gate of the first second-type transistor, the first source/drain terminal is coupled to the second source/drain terminal of the first second-type transistor, the first The second-type transistor is connected to the substrate of the first second-type transistor; the third second-type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the first second-type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the first A source/drain terminal is coupled to the gate and the second source/drain terminal of the second second-type transistor, and the base of the third second-type transistor is coupled to the third The second source/drain terminal of the second type transistor; the fourth second type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the gate is coupled to the the first source/drain terminal, the second source/drain terminal is coupled to the first node, the base of the fourth second-type transistor is coupled to the fourth second-type transistor Describe the second source/sink terminal.

According to an embodiment, the tri-state high-voltage switch circuit further includes a reverse current reducing circuit formed by a third first-type transistor. The third first-type transistor has a gate, a first source/drain terminal, and a second source/drain terminal, and the gate is coupled to the gate of the third second-type transistor, so The first source/drain terminal is coupled to the second source/drain terminal of the fourth first type transistor, and the second source/drain terminal is coupled to the input terminal of the charge pump. According to an embodiment, the tri-state high-voltage switch circuit further includes a second first-type transistor having a gate, a first source/drain terminal, and a second source/drain terminal. The gate is coupled to the first node, the first source/drain is coupled to the input of the charge pump, and the second source/drain is coupled to the third The first source/drain terminal of a type transistor.

According to an embodiment, the first switch of the three-state high-voltage switch circuit is formed by a sixth first-type transistor, and the second switch is formed by a seventh first-type transistor.

According to an embodiment, the three-state high voltage switch circuit further includes a potential converter having an input terminal and an output terminal, wherein the input terminal of the potential converter receives the first selection signal, and the output terminal is coupled to the The first end of the first switch and the first end of the second switch. Wherein in the disabled mode, the output terminal is grounded, and the first end of the first switch is grounded. In the amplifier mode, the output end outputs the second voltage source, so that the first end of the second switch is the second voltage source and turned on.

To sum up, according to the tri-state high-voltage switch circuit of the embodiment of the present invention, the high-voltage switch circuit can operate in three different modes through the structure of the first switch, the second switch and the charge pump. In addition, the tri-state high voltage switch circuit of the embodiment of the present invention may further include a crash protection circuit and a reverse current reduction circuit. Through the crash protection circuit, the node at the output end of the charge pump can be prevented from crashing, and the current of the charge pump can also be prevented from flowing to the node. In addition, the reverse current from the charge pump can be prevented by the reverse current reduction circuit.

100: Three-state high-voltage switch circuit

110: Crash protection circuit

120: Reverse current reduction circuit

HVSW1: High Voltage Switch

LS1: potential converter

CP1: charge pump

SW1: first switch

SW2: Second switch

C1: first capacitor

C2: second capacitor

N1~N7: Transistor

P1~P4: Transistor

N0, N[n], N[n+1]: Transistor

I1: Inverter

I2, I4: logic gate

SEL: select signal

SEL1: the first selection signal

SEL2: Second selection signal

VXE, PASV, CL1, G1, G2, X1, Y1: Node

CLK, CK1, CK2: clock signal

V _DD , V _PP , V _PPX , V _SGX , V _{PP_CL1} : voltage

V _M , V _SS , V _{PP_G1L} , V _{PP_G1H} , V _{PP_G2L} , V _{PP_G2H} : Voltage

D1: Diode

GBL: global bit line

CPW: Common P Well

SL: source line

LWL[n]: character line

SGD: select gate transistor

SGS: select gate transistor

FIG. 1A is a circuit diagram of a conventional high voltage switch.

FIG. 1B shows the operation waveform diagram of FIG. 1A .

FIG. 2 shows a conceptual diagram of a high voltage switch and a memory array.

FIG. 3 is a schematic circuit diagram of a tri-state high voltage switch circuit according to an embodiment of the present invention.

4A to 4C respectively illustrate the operation diagrams of the three states of the three-state high-voltage switch circuit shown in FIG. 3 .

FIG. 5 is a detailed circuit diagram of the tri-state high voltage switch circuit shown in FIG. 3 .

FIG. 6 is a circuit state diagram illustrating a disable mode of the tri-state high voltage switch circuit.

7A and 7B are circuit state diagrams illustrating the charge pump mode of the tri-state high voltage switch circuit, and FIG. 7C is a corresponding timing diagram.

FIG. 8 is a circuit state diagram illustrating the amplifier mode of the tri-state high voltage switching circuit.

FIG. 3 is a schematic circuit diagram of a tri-state high voltage switch circuit according to an embodiment of the present invention. As shown in FIG. 3 , the tri-state high voltage switch circuit 100 includes a charge pump CP1 , a first switch SW1 , a second switch SW2 and a driving transistor N1 . The charge pump CP1 has an input terminal IN and an output terminal OUT. The input terminal IN is coupled to the voltage source (first voltage source) V _PP and the output terminal OUT is coupled to the node PASV. The enable terminal EN receives the selection signal SEL. A first terminal of the first switch SW1 is grounded, and a second terminal is coupled to the node PASV. The first terminal of the second switch SW2 is coupled to the voltage source (second voltage source) V _SGX , and the second terminal is coupled to the node PASV and coupled to the second terminal of the first switch SW1 . The gate of the driving transistor N1 is coupled to the node PASV, and is controlled by the voltage of the node PASV. The first source/drain terminal of the drive transistor N1 is connected to the node Y1, and the second source/drain terminal is coupled to the word line LWL1 (refer to FIG. 2, take LWL1 as an example, and the other word lines LWLn are also the same), for When turned on, word line LWL1 is driven. The tri-state high voltage switch circuit 100 can operate in three modes through the operation of the first switch SW1 and the second switch SW2 and the state of the selection signal SEL.

In addition, the above-mentioned voltage source V _PP is a high voltage source, for example, 20V. The node voltage V _PPX of the node PASV is set to a high voltage higher than the voltage source V _PP , so as to provide enough high voltage to turn on the transistor N1 . The voltage source V _SGX can be an intermediate voltage, which is much smaller than the voltage source V _PPX , for example, it can be 4.5V. In the above-mentioned architecture, the voltage source V _PP is coupled to the node X1 (the input terminal IN of the charge pump), and the voltage source V _SGX can be set in a potential shifter (see the description below), for example.

4A to 4C respectively illustrate the operation diagrams of the three states of the three-state high-voltage switch circuit shown in FIG. 3 . As shown in FIG. 4A , it shows the first operation state of the tri-state high voltage switch circuit 100 , that is, the disable mode. At this time, the first switch SW1 is turned on and the second switch SW2 is turned off, which forces the node PASV to be grounded, and the driving transistor N1 is in a floating state. At this time, the selection signal SEL is at the low level L.

FIG. 4B illustrates the second operating state of the tri-state high voltage switch circuit 100 of FIG. 3 , that is, the charge pump mode. At this time, the first switch SW1 is turned off and the second switch SW2 is turned off. The selection signal SEL of the charge pump CP1 is at a high level H, so that the charge pump CP1 operates and provides the voltage of the node PASV. Thereby, the driving transistor N1 can be turned on by the charge pump CP1, whereby the word line LWL1 can be connected to the node Y1, thereby providing a driving signal to the word line LWL (select or not select the word line).

FIG. 4C illustrates the third operating state of the tri-state high voltage switch circuit 100 in FIG. 3 , that is, the amplifier mode. At this time, the first switch SW1 is turned off and the second switch SW2 is turned on. The selection signal SEL of the charge pump CP1 is at a low level H, so that the charge pump CP1 does not operate. The voltage at node PASV is provided by voltage source _VSGX . After that, the driving transistor N1 will not be turned on until the word line LWL1 reaches the voltage V _SGX -Vth.

Above, the three operation modes of the tri-state high voltage switch circuit 100 in FIG. 3 are briefly described. Next, the detailed operation of the tri-state high voltage switch circuit 100 according to the embodiment of the present invention will be described in detail with reference to the circuit diagram of FIG. 5 .

FIG. 5 is a detailed circuit diagram of the tri-state high voltage switch circuit 100 shown in FIG. 3 . As shown in FIG. 5 , the tri-state high-voltage switch circuit 100 mainly includes a first switch SW1 composed of a transistor N6, a first switch SW2 composed of a transistor N7, a driving transistor N1, and a first capacitor C1, a second A charge pump composed of two capacitors C2, an inverter I1, and transistors N4 and N5. The tri-state high voltage switch circuit 100 may further include a level shifter (level shifter) LS1 for providing the voltage of the node VXE.

The transistor N6 (the first switch SW1) has a gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the output of the level shifter LS1, and the gate is coupled to the operation The voltage V _DD , the second source/drain terminal is coupled to the node PASV. The transistor N7 (the second switch SW2) has a gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the output of the level switch LS1, and the gate is coupled to the selection The second source/drain terminal of the signal SEL2 is coupled to the node PASV. After the output of the level switch LS1 is operated, it can provide the ground voltage GND shown in Figure 3 to the node VXE (for the first switch SW1), or the voltage V _SGX shown in Figure 3 to the node VXE in different operating modes (to the second switch SW2). In this embodiment, transistors N6, N7 may be NMOS transistors.

The driving transistor N1 may be an NMOS transistor, and includes a gate, a first source/drain terminal and a second source/drain terminal, wherein the gate is coupled to the node PASV, the first source/drain terminal is coupled to the node, and the second Two source/drain terminals are coupled to the word line LWL1. When the tri-state high voltage switch circuit 100 operates in the charge pump mode, the voltage of the node PASV can drive the transistor N1, so that the node Y1 can be connected to the word line LWL1 to drive the LWL1. This operation will be further explained below.

The charge pump CP1 includes a first capacitor C1, a second capacitor C2, an inverter I1, and transistors N4 and N5. The transistor N4 has a gate, a first source/drain terminal and a second source/drain terminal, wherein the second source/drain terminal is coupled to the gate. The transistor N5 has a gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the node PASV, and the second source/drain terminal is coupled to the gate and is coupled to the circuit First source/drain terminal of crystal N4. The first terminal of the first capacitor C1 is coupled to the output terminal of the inverter I1, and the second terminal is coupled to the gate of the transistor N4. The first terminal of the second capacitor C2 is coupled to the input terminal of the inverter I1, and the second terminal is coupled to the gate of the transistor N5. The output terminal of the inverter I2 outputs a clock signal (first clock signal) CK1, which is obtained by inverting the clock signal (second clock signal) CK2 received by the input terminal of the inverter I2. The charge pump CP1 receives the selection signal SEL (including the first selection signal SEL1 and the second selection signal SEL2 ) and the clock signal CLK, and generates the clock signal CK2 through the logic circuit (such as I2 and I4 shown in FIG. 5 ).

As shown in FIG. 3 and FIG. 5 , the output terminal of the charge pump CP1 is coupled to the node PASV, and the node X1 is connected to the node G1 , which can be regarded as the input terminal of the charge pump CP1 . Festival Point X1 is then coupled to a voltage source (first voltage source) VPP. In addition, as shown in FIG. 5 , the charge pump CP1 further receives the first selection signal SEL1 and the second selection signal SEL, which may be collectively referred to as the selection signal SEL (see FIG. 3 ). Through the first selection signal SEL1 and the second selection signal SEL, the node PASV can have different voltages, so that the tri-state high voltage switch circuit 100 can operate in three different modes.

In addition, as shown in FIG. 5 , the first selection signal SEL1 is input to the level shifter LS1 and the logic gate I2 . The second selection signal SEL2 is input to the logic gate I4, and the logic gate I4 further receives the clock signal CLK. The first selection signal SEL1, the second selection signal SEL2 and the clock signal CLK are processed by the logic gates I2 and I4 to generate the clock signal CK2 to the input terminal of the inverter I1, and the output of the inverter I1 is the same as the clock signal CK2 inverts the clock signal CK1. The first selection signal SEL1 can operate the level shifter LS1 to output ground or voltage V _SGX (charge pump or amplifier mode) at the node VXE (disabled mode), making it equivalent to the circuit diagram shown in FIG. 3 . In addition, the voltage V _SGX must be higher than the operating voltage V _DD of the transistor N6 , so that the transistor N6 can be turned off when the first selection signal SEL1 is at a high level H. In addition, the level switch LS1 and the transistor N7 can be operated in the amplifier mode of the tri-state high voltage switch circuit 100 , and the level switch LS1 can provide power for the amplifier mode.

In addition, according to an embodiment of the present invention, the tri-state high voltage switch circuit 100 may further include a breakdown protection circuit 110 and an inverse current reduction circuit 120 . As shown in Figures 3 and 5, the crash protection circuit 110 is arranged between the node PASV and the input terminal of the charge pump CP1, the reverse current reducing circuit 120 is coupled to the crash protection circuit 110, and is arranged at the charge pump CP1 on the input path.

The crash protection circuit 110 is, for example, composed of transistors P1-P4 connected in series. The gates of the transistors P1 and P2 are coupled to the node G1 (that is, the second source/drain terminal of the transistor N4) and the first gate of the transistor P1. A source/drain terminal, the second source/drain terminal of the transistor P1 is coupled to the first source/drain terminal of the transistor P2. The substrates of the transistor P1 and the transistor P2 are connected together again. That is, the N-well of transistor P2 is connected to the transistor P1 side. The first source/drain terminal of the transistor P3 is coupled to the second source/drain terminal of the transistor P2, and the gate of the transistor P3 is coupled to the first source/drain terminal thereof. The first source/drain of transistor P4 is coupled to the second source/drain of transistor P3, the gate of transistor P4 is coupled to its first source/drain, and the second source/drain of transistor P4 The terminal is coupled to the node PASV. In addition, the base body of the transistor P3 is coupled to the second source/drain terminal of the transistor P3, and the base body of the transistor P4 is coupled to the second source/drain terminal of the transistor P4. As a result, transistors P1 and P2 are connected to each other to form an equivalent back-to-back diode series circuit, and transistors P3 and transistors P3 are connected to each other to form an equivalent forward-connected diode series circuit. In this way, current can be prevented from flowing from the node G1 to the node PASV.

As shown in FIG. 5, the reverse current reducing circuit 120 is composed of a transistor N3. The gate of the transistor N3 is coupled to the gate of the transistor P4, the first source/drain terminal of the transistor N3 is coupled to the node PASV via the transistor N2, and the second source/drain terminal of the transistor N3 is coupled to the node PASV. to node G1. In the charge pump mode, the charge pump CP1 provides the voltage V _PPX to the node PASV, and the gate of the transistor N3 is coupled to the node CL1 in the above-mentioned PMOS string. Therefore, the transistor N3 will not be turned off at any time, so the reverse current flowing from the node G1 can be prevented, thereby reducing the reverse current. In this situation, if the connection between the node G1 and the node X1 is to be disconnected, the transistor N2 needs to be used for disconnection.

FIG. 6 is a circuit state diagram illustrating a disable mode of the tri-state high voltage switch circuit. As shown in FIG. 6 , the first selection signal SEL1 is at low level L, and the second selection signal SEL2 is at any state. At this time, the level switch LS1 provides the ground voltage GND to the node VXE, that is, the first switch SW1 in FIG. 3 is coupled to the ground. In the disabled mode, the first switch SW1 (transistor N6 ) is turned on and the second switch SW2 (transistor N7 ) is turned off, so the voltage of the node PASV is the ground GND. Therefore, transistors N1 and N2 are turned off. In addition, until the V _GS (gate-source voltage) of the transistors N4 and N5<V _TH (threshold voltage), the potentials of the nodes G1 and G1 decrease. In addition, because the transistor N2 is turned off, the node X1 and the node G1 are disconnected, so the voltage source VPP cannot provide the charge pump CP1, so the charge pump CP1 cannot operate at this time. Table 1 below lists the states of the selection signals SEL1 and SEL2 and the nodes VXE and PASV in the disable mode.

7A and 7B are circuit state diagrams illustrating the charge pump mode of the tri-state high voltage switch circuit, and FIG. 7C is a corresponding timing diagram. In the charge pump mode, the first selection signal SEL1 is at a high level H, and the second selection signal SEL2 is at a low level L. At this moment, the level switch LS1 provides the voltage V _SGX to the node VXE. Since the voltage V _SGX is slightly higher than the operating voltage V _DD (gate voltage) of transistor N6 , transistor N6 is turned off. In addition, because the gate of the transistor N7 is applied with a low level voltage (the second selection signal SEL2 is L), the transistor N7 is also turned off. In this mode, the charge pump CP1 is enabled through the first selection signal SEL1 and the second selection signal SEL2 . At this time, the charge pump CP1 boosts the input voltage V _PP to apply a voltage V _PPX to the node PASV. The voltage V _PPX is higher than the voltage V _PP , and the voltage is high enough to turn on the transistors N1 and N2. At this time, the voltage of the node X1 also becomes the voltage V _PP .

As shown in FIG. 7A and FIG. 7C, if the logic gate I4 inputs the clock signal CLK as shown in the figure, when the clock signal CK2 output by the logic gate I2 turns to a low level (voltage V _SS ), the voltage of the node G2 will become V _{PP_G2L} , but the voltage of the node PASV is maintained at the voltage V _PPX . At the same time, the clock signal CK1 (the clock signal CK2 is inverted by the inverter I1 ) is converted to a high level H (voltage V _M ), which makes the voltage of the node G1 become V _{PP_G1H} . Here, the voltage V _M can be set approximately equal to the operating voltage V _DD , for example, V _M =V _DD =1.8V. During the programming operation, the voltage of the node X1 is equal to the voltage VPP (for example, a high voltage of 20V). In addition, although the transistor N2 is completely turned on at the falling edge of CK2 of the initial clock signal, but because the voltage of the node CL1 is VPP_CL1, the transistor N3 will be turned off, so the reverse current from the node G1 is stopped at the transistor N3 , will not flow to transistor N2, but affect node X1.

In addition, the highest voltages VPP_G1H and VPP_G2H of the nodes G1 and G2 depend on the first capacitor C1 and the second capacitor C2, and the voltage V _{PP_G1L} can be set as the voltage of the node X1 minus the threshold voltage V _TH of the transistor N2 (that is, V _{PP_G1L} = V _PP -V _{TH_N2} ).

As shown in FIG. 7B and FIG. 7C , when the clock signal CK2 turns to a high level H, the voltage of the node G1 becomes VPP_G2H, and the voltage of the node PASV becomes V _PPX . At the same time, the clock signal CK1 changes from the high level H to the low level L (as shown in FIG. 8C , from the voltage V _M to the voltage V _SS ), which causes the voltage of the node G1 to drop. As shown in FIG. 8C , when the voltage of the node G1 drops below V _{PP_G1L} , the transistor N3 is turned on and returns to V _{PP_G1L} . When the voltage of the node G1 is getting closer to V _{PP_G1L} , the transistor N3 will gradually turn off.

In addition, the transistor strings P1 ˜ P4 of the crash protection circuit 110 are here used for crash protection of the node PASV. The transistors P1-P4 are turned on only when the voltage of the node PASV is much higher than the voltage of the node G1, so as to prevent the current from flowing from the node G1 to the node PASV. In addition, as mentioned above, in order to prevent the forward bonding current from flowing to the node PASV through the transistors P1 ˜ P4 , the N-well of the transistor P2 is connected to the side of the transistor P1 . Table 2 below lists the states of the selection signals SEL1 and SEL2 and the nodes VXE and PASV in the charge pump mode.

FIG. 8 is a circuit state diagram illustrating the amplifier mode of the tri-state high voltage switching circuit. As shown in FIG. 8 , the first selection signal SEL1 is at a high level H, and the second selection signal SEL2 is at a high level H. At this time, the level switch LS1 provides the voltage V _SGX to the node VXE, that is, the second switch SW2 in FIG. 3 is coupled to the voltage source V _SGX . In the amplifier mode, since the voltage V _SGX is higher than the operation voltage VDD of the transistor N6, the transistor N6 is turned off, and the transistor N7 (the second switch SW2 ) is turned on. Thereby, the voltage of the node PASV becomes the voltage V _SGX . In the amplifier mode, the charge pump CP1 is disabled and cannot operate. In addition, in order not to turn on (or float) the transistors N4 and N5 of the charge pump CP1, the voltage of the node X1 needs to be set equal to or lower than the voltage V _SGX , and the voltage of the node Y1 needs to be set equal to or greater than the voltage V _SGX . The potential of the word line LWL1 needs to be V _SG0 (ie, V _SGX −V _{TH_N1} ). Thereby, the tri-state high voltage switch circuit 100 is operated in the amplifier mode. In addition, in this mode, the crash protection circuit 110 (P1-P4) does not operate. Table 3 below lists the states of the selection signals SEL1 and SEL2 and the nodes VXE and PASV in the amplifier mode.

To sum up, according to the tri-state high-voltage switch circuit of the embodiment of the present invention, the high-voltage switch circuit can operate in three different modes through the structure of the first switch, the second switch and the charge pump. In addition, the tri-state high voltage switch circuit of the embodiment of the present invention may further include a crash protection circuit and a reverse current reduction circuit. Through the crash protection circuit, the node at the output end of the charge pump can be prevented from crashing, and the current of the charge pump can also be prevented from flowing to the node. In addition, the reverse current from the charge pump can be prevented by the reverse current reduction circuit.

100: Three-state high-voltage switch circuit

SW1: first switch

SW2: Second switch

CP1: charge pump

V _PP : Voltage source

V _SGX : Voltage source

PASV:Node

IN: The input terminal of the charge pump

OUT: The output terminal of the charge pump

EN: Enable terminal of the charge pump

N1: Transistor

Y1: node

SEL: select signal

LWL1: character line

HVSW1: High Voltage Switch

Claims (10)

A tri-state high-voltage switch circuit, comprising: a charge pump having an input terminal, an output terminal and an enabling terminal, wherein the enabling terminal is used to receive a selection signal, the input terminal receives a first voltage source, and the output terminal is coupled to a first node, the selection signal includes a first selection signal and a second selection signal; a first switch has a first terminal and a second terminal, the first terminal is coupled to ground, and the second terminal is coupled to The first node; the second switch has a first end and a second end, the first end is coupled to a second voltage source, and the second end is coupled to the first node, wherein the first end a voltage source greater than the second voltage source; and a first first-type transistor having a gate, a first source-drain terminal, and a second source-drain terminal, the gate is coupled to the first node, the The second source-drain terminal is coupled to a word line, wherein, based on the first selection signal and the second selection signal, the tri-state high-voltage switch circuit is turned on when the first switch is turned on and the second When the switch is closed, it operates in a disabled mode, and when the first switch is closed and the second switch is closed, and the charge pump is enabled by receiving the selection signal, it operates in a charge pump mode , and operating in amplifier mode when the first switch is off and the second switch is on. The tri-state high-voltage switch circuit according to claim 1 further includes a crash protection circuit disposed between the first node and the input terminal of the charge pump. The tri-state high-voltage switch circuit as described in claim item 2, further includes reverse current A reduction circuit is coupled to the crash protection circuit and disposed on the input terminal of the charge pump. The tri-state high-voltage switch circuit as claimed in claim 3, wherein the reverse current reducing circuit is coupled to the input terminal of the charge pump via a second first-type transistor. The tri-state high-voltage switch circuit as described in Claim 1, wherein the charge pump further includes: an inverter having an input terminal and an output terminal, wherein the output terminal outputs a first clock signal, and the input terminal receives a first clock signal Two clock signals; the fourth first-type transistor has a gate, a first source/drain terminal and a second source/drain terminal, wherein the second source/drain terminal is coupled to the gate; fifth A first-type transistor having a gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the first node, and the second source/drain terminal is coupled to the first node. coupled with the gate and coupled to the first source/drain terminal of the fourth first-type transistor; a first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to connected to the output terminal of the inverter, the second terminal coupled to the gate of the fourth first-type transistor; and a second capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the input terminal of the inverter, and the second terminal is coupled to the gate of the fifth first-type transistor, Wherein the charge pump receives the selection signal and the clock signal, and generates the second clock signal through a logic circuit. The tri-state high-voltage switch circuit as described in claim item 5 further includes a crash protection circuit, and the crash protection circuit further includes: a first second-type transistor having a gate, a first source/drain terminal and a second source/drain terminal drain terminal, wherein the gate is coupled to the first source/drain terminal and the second source/drain terminal of the fourth first type transistor; the second second type transistor has a gate , a first source/drain terminal and a second source/drain terminal, wherein the gate is coupled to the gate of the first second-type transistor, and the first source/drain terminal is coupled to the The second source/drain terminal of the first second-type transistor, the base of the first second-type transistor and the first second-type transistor are connected to each other; the third second-type transistor, having a gate, a first source/drain and a second source/drain, wherein the first source/drain is coupled to the gate and the second source of the second second-type transistor /Drain terminal, the substrate of the third second-type transistor is coupled to the second source/drain terminal of the third second-type transistor; the fourth second-type transistor has a gate, a first transistor A source/drain terminal and a second source/drain terminal, wherein the gate is coupled to the first source/drain terminal, the second source/drain terminal is coupled to the first node, and the first source/drain terminal is coupled to the first node. The substrates of the four second-type transistors are coupled to the second source/drain terminals of the fourth second-type transistors. The tri-state high-voltage switch circuit as described in Claim 6 further includes a reverse current reduction circuit, which is composed of a third first-type transistor, wherein the third first-type transistor has a gate, a first source/drain terminal and a second source/drain terminal, the gate is coupled to the gate of the third second-type transistor, The first source/drain terminal is coupled to the second source/drain terminal of the fourth first-type transistor, and the second source/drain terminal is coupled to the input terminal of the charge pump . The tri-state high-voltage switch circuit as claimed in item 7, further comprising a second first-type transistor having a gate, a first source/drain terminal, and a second source/drain terminal, wherein the gate is coupled to the the first node, the first source/drain terminal is coupled to the input terminal of the charge pump, and the second source/drain terminal is coupled to the first transistor of the third first type One source/sink terminal. The tri-state high-voltage switch circuit according to claim 1, wherein the first switch is composed of a sixth first-type transistor, and the second switch is composed of a seventh first-type transistor. The tri-state high-voltage switch circuit as described in claim 1 further includes a potential converter having an input terminal and an output terminal, wherein the input terminal of the potential converter receives the first selection signal, and the output terminal is coupled to connected to the first end of the first switch and the first end of the second switch, wherein in the disabled mode, the output end is grounded, so that the first end of the first switch The first end is grounded, and in the amplifier mode, the output end outputs the second voltage source, so that the first end of the second switch is the second voltage source and turned on .

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