TWI792441B - Electronic device testing apparatus having multi-layer testing module - Google Patents
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Abstract
本發明係有關於一種具備多層架構測試模組之電子元件檢測設備,主要包括供料及分料模組、晶片移載模組、多層架構測試模組及主控制器,而供料及分料模組與多層架構測試模組係分設於晶片移載模組之周遭。其中,晶片移載模組受控自供料及分料模組移載待測電子元件到多層架構測試模組,且受控自多層架構測試模組移載完測電子元件到供料及分料模組。據此,供料及分料模組、晶片移載模組及多層架構測試模組係三個彼此分離的模組,可彈性配置,且多層架構測試模組呈現立體化的多層架構配置,藉此可顯著提高檢測量能,且容易實現多樣化檢測。The present invention relates to an electronic component testing device with a multi-layer structure test module, which mainly includes a feeding and distributing module, a chip transfer module, a multi-layer structure testing module and a main controller, and the feeding and distributing module It is separated from the multi-layer structure test module and located around the chip transfer module. Among them, the wafer transfer module is controlled to transfer the electronic components to be tested from the feeding and distributing module to the multi-layer structure testing module, and is controlled to transfer the tested electronic components from the multi-layer structure testing module to the feeding and distributing module . Accordingly, the feeding and distributing module, the wafer transfer module and the multi-layer structure test module are three separate modules that can be flexibly configured, and the multi-layer structure test module presents a three-dimensional multi-layer structure configuration, thereby The detection capacity can be significantly improved, and diversified detection can be easily realized.
Description
本發明係關於一種具備多層架構測試模組之電子元件檢測設備,尤指一種檢測電子元件良窳之電子元件檢測設備。The invention relates to an electronic component testing device with a multi-layer structure testing module, especially an electronic component testing device for testing the quality of electronic components.
現有的半導體晶片檢測機台的配置都是採用平面化的配置,即如圖1所示,在整個設備一側配置晶片檢測區Zt,另一側則配置晶片進出料區Zc,而且還會配置至少一個用於搬運晶片的晶片取放裝置Dp。Existing semiconductor wafer inspection machines are configured in a planar configuration, that is, as shown in Figure 1, a wafer inspection area Zt is arranged on one side of the entire equipment, and a wafer feeding and unloading area Zc is arranged on the other side. At least one wafer pick and place device Dp for handling wafers.
進一步說明,晶片檢測區Zt內會設置多個晶片檢測模組11,其係用來實際進行晶片測試,例如系統級測試(System Level Testing,SLT);而晶片進出料區Zc則包括多個可裝載晶片萃盤的容器,其包括進料匣12、良品匣13以及不良品匣14等;其中,進料匣12內所容納的晶片萃盤上都是待測晶片,在正式被進行測試之前,裝載待測晶片的晶片萃盤會被移載到一萃盤載台15。接著,晶片取放裝置Dp再從萃盤載台15上搬運待測晶片到晶片檢測模組11上進行測試。最後,當完成測試後,晶片取放裝置Dp會根據測試結果,而從晶片檢測模組11上把完測晶片移載到良品匣13或不良品匣14上的晶片萃盤。To further illustrate, a plurality of
然而,隨著待測晶片功能越趨強大,且所需要檢測的項目越來越多,導致檢測時間也越來越久,也就是待測晶片停留在晶片檢測模組11上的時間越來越久,例如功能強大的圖形處理晶片之檢測時間甚至需要長達數小時。據此,受限於現有機台的平面化配置,晶片檢測模組11的數量受限,所以難免會出現移載裝置的等待時間,無法充分發揮設備的最佳運轉效率。However, as the function of the wafer to be tested becomes more and more powerful, and more and more items need to be inspected, the inspection time becomes longer and longer, that is, the time for the wafer to be inspected to stay on the
另一方面,現有晶片檢測機台的配置方式所能檢測的待測晶片僅限於一種,也就是說單一機台檢測單一晶片,因為受限於晶片檢測模組11的數量,無法在單一機台上實現測試多種待測晶片的功效。再者,受限於現有機台的平面化配置,空間上的利用性較差,導致空間場地的成本也相對較大。On the other hand, the configuration of existing wafer testing machines can detect only one type of wafer to be tested, that is to say, a single machine can detect a single wafer. Because of the limited number of
由此可知,一種可大幅提升檢測效率和場地空間的利用性,又可實現多用途、多元測試項目之電子元件檢測設備,實為產業界、及社會大眾所殷殷期盼者。It can be seen from this that an electronic component testing equipment that can greatly improve the testing efficiency and site space utilization, and can realize multi-purpose and multiple testing items, is really eagerly awaited by the industry and the general public.
本發明之主要目的係在提供一種具備多層架構測試模組之電子元件檢測設備,其可大幅提高電子元件的檢測量能,且可減少裝置或設備的閒置時間,即可顯著提升檢測效率,又可擴充待測物種類以提升測試規模。The main purpose of the present invention is to provide an electronic component testing equipment with a multi-layer structure test module, which can greatly improve the detection capacity of electronic components, and can reduce the idle time of devices or equipment, which can significantly improve the detection efficiency, and The type of test object can be expanded to increase the test scale.
為達成上述目的,本發明提供一種具備多層架構測試模組之電子元件檢測設備,其主要包括一供料及分料模組、一晶片移載模組、至少一多層架構測試模組以及一主控制器;主控制器係電性連接至供料及分料模組、晶片移載模組及多層架構測試模組;其中,供料及分料模組與至少一多層架構測試模組係分設於晶片移載模組之周遭;主控制器控制晶片移載模組自供料及分料模組移載一待測電子元件到至少一多層架構測試模組,並控制晶片移載模組自至少一多層架構測試模組移載一完測電子元件到供料及分料模組;其中,至少一多層架構測試模組包括一層架及複數測試單元;而該層架包括複數容置空間,其係直立式排列於層架;且複數測試單元係分別設置於複數容置空間。In order to achieve the above object, the present invention provides an electronic component testing device with a multi-layer structure test module, which mainly includes a feeding and distribution module, a chip transfer module, at least one multi-layer structure test module and a main Controller; the main controller is electrically connected to the feeding and distributing module, the chip transfer module and the multi-layer structure testing module; wherein, the feeding and distributing module is separated from at least one multi-layer structure testing module Around the wafer transfer module; the main controller controls the wafer transfer module to transfer an electronic component to be tested from the feeding and dispensing module to at least one multi-layer structure test module, and controls the wafer transfer module to transfer from at least one A multi-layer structure test module transfers a tested electronic component to the feeding and distributing module; wherein, at least one multi-layer structure test module includes a shelf and a plurality of test units; and the shelf includes a plurality of accommodating spaces, It is vertically arranged on the shelf; and the plurality of test units are respectively arranged in the plurality of accommodating spaces.
據此,將習知電子元件檢測設備的晶片進出料區、晶片檢測區及晶片取放裝置拆分成三個彼此分離的模組,亦即供料及分料模組、晶片移載模組以及多層架構測試模組,更便利於因應實際需求而彈性地配置各模組之數量和彼此間的相對位置;且多層架構測試模組係呈現立體化的多層架構配置,藉此可大幅增加測試單元的數量,除了可顯著提高檢測量能,藉此增進檢測效率與產能,更可升級為多測試規格之多樣化檢測。Accordingly, the wafer feeding and unloading area, the wafer inspection area and the wafer pick-and-place device of the conventional electronic component testing equipment are split into three separate modules, i.e. feeding and distributing module, wafer transfer module and The multi-layer structure test module is more convenient to flexibly configure the number of modules and the relative positions between each other according to actual needs; and the multi-layer structure test module presents a three-dimensional multi-layer structure configuration, thereby greatly increasing the number of test units In addition to significantly improving the detection capacity, the detection efficiency and production capacity can be improved, and it can be upgraded to a variety of detection with multiple test specifications.
較佳的是,本發明之多層架構測試模組可包括至少一溫控模組,其可設置於層架之一側,而溫控模組係連接至複數測試單元之壓接頭、測試座及晶片梭車中至少一者;且溫控模組可透過壓接頭、測試座及晶片梭車中至少一者調控待測電子元件之溫度,並使之維持於一特定溫度。換言之,本發明之多層架構測試模組可另外配置溫控模組,且其可設置層架之一側,不佔用測試單元之容置空間,可將達成空間利用性之最佳化。Preferably, the multi-layer structure test module of the present invention can include at least one temperature control module, which can be arranged on one side of the shelf, and the temperature control module is connected to the crimping head, the test socket and the plurality of test units. At least one of the wafer shuttles; and the temperature control module can regulate the temperature of the electronic components to be tested through at least one of the crimping head, the test socket and the wafer shuttle, and maintain it at a specific temperature. In other words, the multi-layer structure test module of the present invention can be equipped with a temperature control module, and it can be installed on one side of the shelf, without occupying the test unit's accommodating space, which can achieve the optimization of space utilization.
另外,本發明之複數測試單元可包括一第一測試單元及一第二測試單元;當第一測試單元檢測該完測電子元件後判斷為一不良品時,主控制器可控制晶片移載模組將之移載到第二測試單元進行測試;若當第二測試單元判斷完測電子元件為良品時,主控制器標註第一測試單元;當第一測試單元獲得第二次標註時,主控制器停止第一測試單元之運作。換言之,當檢測結果為不良品時,本發明可對該不良品移載至另一測試單元作重測,透過至少兩次的重複測試,藉此用以確保前一測試單元判斷為正確;然而,如果同一測試單元發生兩次誤判情形時,該測試單元即被標示為故障,即刻暫停該測試單元之測試作業。In addition, the plurality of test units of the present invention may include a first test unit and a second test unit; when the first test unit detects the finished electronic component and judges it to be a defective product, the main controller can control the chip transfer module The group transfers it to the second test unit for testing; if the second test unit judges that the tested electronic component is a good product, the main controller marks the first test unit; when the first test unit is marked for the second time, the main controller The controller stops the operation of the first test unit. In other words, when the test result is a defective product, the present invention can transfer the defective product to another test unit for retesting, and repeat the test at least twice to ensure that the previous test unit is judged as correct; , if two misjudgments occur in the same test unit, the test unit will be marked as a failure, and the test operation of the test unit will be suspended immediately.
再者,本發明之供料及分料模組可包括一上層模組及一下層模組,而上層模組及下層模組係上下層疊;且上層模組及下層模組可各自包括至少一供料匣、至少一出料匣、及至少一空料匣,供料匣可存放待測料盤,出料匣可存放完測料盤,空料匣可存放空料盤;而待測料盤上可放置待測電子元件,完測料盤上可放置完測電子元件。換言之,本發明之供料及分料模組亦可採立體化之多層架構,即可多層供料和分料,藉此可提高待測及完測電子元件之容納量,以提升運作續航時間;亦可藉此擴充待測物種類以提升測試規模。Furthermore, the feeding and distributing modules of the present invention may include an upper module and a lower module, and the upper module and the lower module are stacked up and down; and the upper module and the lower module may each include at least one supply Material box, at least one output box, and at least one empty material box, the feeding box can store the material tray to be tested, the output box can store the tested material tray, and the empty material box can store the empty material tray; The electronic components to be tested can be placed, and the tested electronic components can be placed on the finished test material tray. In other words, the feeding and distributing module of the present invention can also adopt a three-dimensional multi-layer structure, that is, multi-layer feeding and distributing, so as to increase the capacity of the electronic components to be tested and completed, so as to improve the operating life; It can also be used to expand the types of test objects to increase the test scale.
本發明具備多層架構測試模組之電子元件檢測設備在本實施例中被詳細描述之前,要特別注意的是,以下的說明中,類似的元件將以相同的元件符號來表示。再者,本發明之圖式僅作為示意說明,其未必按比例繪製,且所有細節也未必全部呈現於圖式中。Before the detailed description of the electronic component testing device with the multi-layer structure testing module of the present invention, it should be noted that in the following description, similar components will be denoted by the same component symbols. Furthermore, the drawings of the present invention are for illustrative purposes only, and may not be drawn to scale, and not all details may be presented in the drawings.
請先參閱圖2,其係本發明電子元件檢測設備一較佳實施例之示意圖。如圖中所示,本實施例之電子元件檢測設備主要包括一供料及分料模組2、一晶片移載模組3、二多層架構測試模組4以及一主控制器5;主控制器5係電性連接至供料及分料模組2、晶片移載模組3及多層架構測試模組4。又,二多層架構測試模組4分設於晶片移載模組3之二相對應側,而供料及分料模組2則設置於晶片移載模組3之另一側,也就是位於二多層架構測試模組42的一側端之間,藉此構成一U型配置,即晶片移載模組3係設置於該U型配置之中間位置。Please refer to FIG. 2 first, which is a schematic diagram of a preferred embodiment of the electronic component testing equipment of the present invention. As shown in the figure, the electronic component testing equipment of this embodiment mainly includes a feeding and distributing module 2, a wafer transfer module 3, two multi-layer structure testing modules 4 and a main controller 5; The device 5 is electrically connected to the feeding and distributing module 2, the wafer transfer module 3 and the multi-layer structure testing module 4. Also, the two multi-layer structure test modules 4 are located on two corresponding sides of the wafer transfer module 3, and the feeding and distribution module 2 are arranged on the other side of the wafer transfer module 3, that is, they are located on the other side of the wafer transfer module 3. A U-shaped configuration is formed between one side of the two multi-layer
請一併參閱圖3,其係本發明多層架構測試模組4一較佳實施例之示意圖;在本實施例中,每一多層架構測試模組4包括一層架41、六個測試單元42以及二溫控模組6,溫控模組6請見圖2。其中,層架41包括六個容置空間40,其係兩兩分層直立地排列於層架41,而六個測試單元42係分別設置於該六個容置空間40內。Please also refer to Fig. 3, which is a schematic diagram of a preferred embodiment of the multi-layer structure test module 4 of the present invention; in this embodiment, each multi-layer structure test module 4 includes a
又請一併參閱圖4A、4B,圖4A係本發明多層架構測試模組一較佳實施例之晶片梭車位於第一位置之示意圖,圖4B係本發明多層架構測試模組一較佳實施例之晶片梭車位於第二位置之示意圖。在本實施例中,每一測試單元42包括一壓接頭421、一測試座422及一晶片梭車423,壓接頭421係設置於測試座422上方,晶片梭車423係可選擇地位於一第一位置P1或一第二位置P2。其中,第一位置P1係指晶片梭車423位於壓接頭421與測試座422之間的位置,也就是供壓接頭421取料和置料之位置,即如圖4A所示;而第二位置P2係指晶片梭車423遠離壓接頭421與測試座422之間,並供晶片移載模組3取放待測電子元件IC1與完測電子元件IC2之位置,即如圖4B所示。Please also refer to Fig. 4A and 4B together. Fig. 4A is a schematic diagram of a preferred embodiment of the multi-layer structure test module of the present invention where the wafer shuttle car is located at the first position. Fig. 4B is a preferred implementation of the multi-layer structure test module of the present invention A schematic diagram of an example of a wafer shuttle in the second position. In this embodiment, each
更進一步說明,本實施例之壓接頭421包括多個負壓吸嘴424;而當晶片梭車423位於第一位置P1時,壓接頭421下降並趨近晶片梭車423,並以負壓吸嘴424吸取待測電子元件IC1,或以負壓吸嘴424放置完測電子元件IC2於晶片梭車423;通常是先將完測電子元件IC2放置於晶片梭車423後,晶片梭車423略為滑移,以讓壓接頭421去吸取待測電子元件IC1。To further illustrate, the crimping
再者,當壓接頭421吸取待測電子元件IC1之後,晶片梭車423遠離壓接頭421與測試座422之間,也就是該第二位置P2;此時,壓接頭421下降並趨近測試座422以放置待測電子元件IC1於測試座422內,並持續下壓待測電子元件IC1而進行檢測待測電子元件IC1,如圖4B所示。Furthermore, after the crimping
另一方面,又如圖2所示,在層架41二側各設有一溫控模組6,其係連接至每一測試單元42之壓接頭421;該溫控模組6係提供高溫或低溫之溫控流體給壓接頭421,以調控待測電子元件IC1之溫度,並使之維持於一特定溫度來進行高溫測試或低溫測試。當然,本發明之溫控模組6並非以只提供溫控流體給壓接頭421為限,亦可同步提供給測試座422,以營造完整的溫控環境;抑或,一併提供溫控流體給晶片梭車423,以預先對待測電子元件IC1升溫或降溫,來減少單靠壓接頭421進行溫控至該特定溫度所耗的等待時間。On the other hand, as shown in Figure 2, a temperature control module 6 is respectively arranged on both sides of the
請一併參閱圖2及圖5,圖5係本發明供料及分料模組2一較佳實施例之示意圖;本實施例之供料及分料模組2包括一上層模組22及一下層模組23;也就是說,本實施例之供料及分料模組2亦採立體化之多層架構,即可多層供料和分料,藉此可提高待測及完測電子元件之容納量,以提升運作續航時間;亦可藉此擴充待測物種類以提升測試規模。Please refer to Fig. 2 and Fig. 5 together, Fig. 5 is a schematic diagram of a preferred embodiment of the present invention's feeding and distributing module 2; the feeding and distributing module 2 of this embodiment includes an
進一步說明,本實施例之上層模組22及下層模組23各自包括一供料匣24、六出料匣25、一空料匣26、一搬運梭台27、一供分料移載單元28以及一料盤移載單元29;供料匣24係用於存放待測料盤241,而待測料盤241則是用於裝載待測電子元件IC1;出料匣25係用於存放完測料盤251,而完測料盤251用於裝載完測電子元件IC2,也就是說,六出料匣25可以依照不同測試結果分別存放完測電子元件IC2;又,空料匣26則係用於存放空料盤261,亦即空的待測料盤241。To further illustrate, the
另外,請繼續參閱圖2及圖5,本實施例之搬運梭台27係可選擇地移動於一內部位置Pin及一外部位置Pout,內部位置Pin係上層模組22及下層模組23內部進行供料和分料之位置,而外部位置Pout則是搬運梭台27凸伸出供料及分料模組2本體之外以供晶片移載模組3取放待測電子元件IC1與完測電子元件IC2之位置。In addition, please continue to refer to Fig. 2 and Fig. 5, the transfer shuttle platform 27 of the present embodiment can be selectively moved between an internal position Pin and an external position Pout, and the internal position Pin is carried out inside the
詳言之,本實施例之搬運梭台27包括二晶片容置槽271,其分別供存放待測電子元件IC1和完測電子元件IC2。另外,供分料移載單元28則係用於移載待測電子元件IC1於待測料盤241與位於內部位置Pin之搬運梭台27之晶片容置槽271之間,也就是供料作業;另一方面,供分料移載單元28又可用於移載完測電子元件IC2於位於內部位置Pin之搬運梭台27之晶片容置槽271與完測料盤251之間,也就是分料作業。In detail, the transfer shuttle table 27 of this embodiment includes two
至於,料盤移載單元29係用於自供料匣24移載空的待測料盤241至空料匣26,以作為空料盤261;而且,料盤移載單元29還用於從空料匣26移載空料盤261到出料匣25,作為完測料盤251,以補充已經滿載之完測料盤251。另一方面,當搬運梭台27滑移到外部位置Pout時,搬運梭台27係供晶片移載模組3取放待測電子元件IC1及完測電子元件IC2。As for, the
以下簡單描述本實施例之晶片移載作業;首先,主控制器5控制供分料移載單元28從待測料盤241移載一待測電子元件IC1到位於內部位置Pin之搬運梭台27之晶片容置槽271;接著,供分料移載單元28也從另一晶片容置槽271吸取一完測電子元件IC2,並依照該完測電子元件IC2的檢測結果而將之移動到對應的完測料盤251。The following briefly describes the wafer transfer operation of this embodiment; first, the main controller 5 controls the material distribution and
同時,控制器5控制搬運梭台27移動到外部位置Pout;接著,晶片移載模組3取走該待測電子元件IC1,並將之移載到多層架構測試模組4中其中一個測試單元42。又進一步說明,晶片移載模組3將該待測電子元件IC1放置到位於第二位置P2之晶片梭車423,並接著取走晶片梭車423上的完測電子元件IC2。再者,晶片移載模組3將該完測電子元件IC2移載到供分料移載單元28,也就是位於外部位置Pout之搬運梭台27的晶片容置槽271內;接著便以此方式循環進行供料和分料作業。Simultaneously, the controller 5 controls the transport shuttle 27 to move to the external position Pout; then, the wafer transfer module 3 takes away the electronic component IC1 to be tested, and transfers it to one of the test units in the multi-layer structure test module 4 42. It is further explained that the wafer transfer module 3 places the electronic component IC1 to be tested on the
另外,補充說明,本實施例亦有提供測試單元自我檢查的功能,也就是針對測試結果為不良品之待測電子元件IC1重複測試,以確定是否真為真實檢測結果抑或測試設備故障所致。舉例說明,請見圖3,六個測試單元42中暫時指定一第一測試單元42A及一第二測試單元42B;當第一測試單元42A檢測該完測電子元件IC2後判斷為一不良品時,主控制器5控制晶片移載模組3將之移載到第二測試單元42B進行測試,也就是所謂重測;若當該完測電子元件IC2經第二測試單元42B測試後卻被判斷為良品時,主控制器51標註第一測試單元42A,也就是對第一測試單元42A作註記;若第一測試單元42A獲得第二次標註時,也就是上述情形重複發生時,主控制器51則判斷第一測試單元42A之運作出現異常,而停止第一測試單元42A之運作。In addition, it is added that this embodiment also provides the function of self-inspection of the test unit, that is, repeats the test for the electronic component under test IC1 whose test result is a defective product, to determine whether it is a real test result or caused by a test equipment failure. For example, please refer to Fig. 3, among the six
再且,在本發明的其他實施例中,為了更慎重起見,當第一測試單元42A與第二測試單元42B對同一待測電子元件IC1的檢測結果出現歧異的情形時,亦可再進行另一次重測,也就是交由第三測試單元42C重測該完測電子元件IC2,藉以判斷究竟是第一測試單元42A抑或第二測試單元42B出現異常。Moreover, in other embodiments of the present invention, in order to be more prudent, when the
此外,本實施例另外提供不同模組間位置的自動校準方法,也就是供料及分料模組2、晶片移載模組3以及二多層架構測試模組4等四者間的彼此之位置座標的校準。進一步說明,長久以來,在機台安裝時,不同組件的位置配置和校準一直以來都是很繁瑣的任務,而一但出現誤差時將會導致晶片移載模組3無法順利取放晶片,嚴重者將致使整個設備停擺。然而,本實施例提供以下自動校準機制,將可順利解決上述問題。In addition, this embodiment also provides an automatic calibration method for the positions between different modules, that is, the positions of the feeding and distributing module 2, the wafer transfer module 3, and the two-layer structure testing module 4. Coordinate calibration. To further explain, for a long time, the position configuration and calibration of different components have always been very cumbersome tasks during machine installation, and once errors occur, it will cause the wafer transfer module 3 to fail to pick and place wafers smoothly, seriously Otherwise, the entire equipment will stop. However, the present embodiment provides the following automatic calibration mechanism, which will successfully solve the above problems.
請同時參閱圖2及圖6,圖6係本發明校準元件一較佳實施例之立體圖,在本實施例中,供料及分料模組2及二多層架構測試模組4各自包括一校準元件7,其係一平板,且向上凸伸有一圓形凸台71,而晶片移載模組3包括一雷射測距單元31,其所運用的原理是向待測距的物體發射雷射脈衝並開始計時,而接收到反射光時停止計時,藉此這段時間即就可以經過換算而轉換為雷射測距單元31與目標之間的距離。Please refer to Fig. 2 and Fig. 6 at the same time, Fig. 6 is the perspective view of a preferred embodiment of the calibration element of the present invention, in the present embodiment, feeding and distributing module 2 and two multi-layer structure testing module 4 respectively comprise a calibration Component 7 is a flat plate with a
具體實施方式為,由主控制器5控制晶片移載模組3之雷射測距單元31分別掃描供料及分料模組2及二多層架構測試模組4之校準元件7上圓形凸台71的位置座標,該主控制器5以該等位置座標分別作為供料及分料模組2及二多層架構測試模組4之校準座標;其中,上面提到的圓形凸台71的位置座標即為該等圓形凸台71的圓心座標,其具體求取方式請見後述。The specific implementation method is that the main controller 5 controls the
首先,主控制器5控制晶片移載模組3沿著第一方向D1以該雷射測距單元31掃描校準元件7上之圓形凸台71,當雷射測距單元31掃描至圓形凸台71時,記錄因高度突升所產生之一第一凸台起始位置P11,又記錄因高度突降所產生之一第一凸台終點位置P12。接著,控制單元運算求取沿著第一方向D1延伸之第一凸台起始位置P11與第一凸台終點位置P12的一第一中點位置P1C。First, the main controller 5 controls the wafer transfer module 3 to scan the
另外,主控制器5又控制雷射測距單元31沿著第二方向D2掃描該校準元件7上之圓形凸台71;而當雷射測距單元31掃描至圓形凸台71時,記錄因高度突升所產生之一第二凸台起始位置P21,以及高度突降所產生之一第二凸台終點位置P22。再且,主控制器5運算求取沿著第二方向D2延伸之第二凸台起始位置P21與第二凸台終點位置P22的一第二中點位置P2C。最後,主控制器5求取第一中點位置P1C沿著第二方向D2延伸線段與第二中點位置P2C沿著第一方向D1延伸線段之交點以作為交點圓心位置Pc,即該等圓形凸台71的圓心座標,也就是供料及分料模組2及二多層架構測試模組4之校準座標。In addition, the main controller 5 controls the
也就是說,主控制器51可以根據該等校準座標作為供料及分料模組2及二多層架構測試模組4之定位原點座標,亦即對晶片移載模組3、供料及分料模組2及二多層架構測試模組4四者之間位置的校準定位;而控制晶片移載模組3便可根據該等校準座標自該供料及分料模組2精準移載該待測電子元件IC1到多層架構測試模組4,同樣可精準控制晶片移載模組3自多層架構測試模組4移載完測電子元件IC2到供料及分料模組2。據此,上述自動校準機制可省去傳統設備安裝時各組件之繁瑣對位校準流程,不僅可大幅提升安裝效率,且又可提供相當精準的定位、校準,讓晶片移載模組3可以進行相當精準的取料和放料。That is to say, the main controller 51 can use these calibration coordinates as the positioning origin coordinates of the feeding and distributing module 2 and the two-layer structure testing module 4, that is, for the wafer transfer module 3, feeding and distributing module 3 Calibration and positioning of the position between the material module 2 and the second multi-layer structure test module 4; and the control chip transfer module 3 can accurately transfer the wafer from the feeding and distributing module 2 according to the calibration coordinates. The electronic component IC1 to be tested to the multi-layer structure test module 4 can also precisely control the chip transfer module 3 to transfer the tested electronic component IC2 from the multi-layer structure test module 4 to the feeding and distributing module 2 . Accordingly, the above-mentioned automatic calibration mechanism can save the cumbersome alignment calibration process of each component during traditional equipment installation, not only can greatly improve the installation efficiency, but also provide quite accurate positioning and calibration, so that the wafer transfer module 3 can be carried out Quite precise retrieving and unloading.
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。The above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments.
2:供料及分料模組 3:晶片移載模組 4:多層架構測試模組 5:主控制器 6:溫控模組 7:校準元件 11:晶片檢測模組 12:進料匣 13:良品匣 14:不良品匣 15:萃盤載台 22:上層模組 23:下層模組 24:供料匣 25:出料匣 26:空料匣 27:搬運梭台 28:供分料移載單元 29:料盤移載單元 31:雷射測距單元 40:容置空間 41:層架 42:測試單元 42A:第一測試單元 42B:第二測試單元 42C:第二測試單元 71:圓形凸台 241:待測料盤 251:完測料盤 261:空料盤 271:晶片容置槽 421:壓接頭 422:測試座 423:晶片梭車 424:負壓吸嘴 D1:第一方向 D2:第二方向 Dp:晶片取放裝置 IC1:待測電子元件 IC2:完測電子元件 P1:第一位置 P2:第二位置 P11:第一凸台起始位置 P12:第一凸台終點位置 P1C:第一中點位置 P21:第二凸台起始位置 P22:第二凸台終點位置 P2C:第二中點位置 Pc:交點圓心位置 Pin:內部位置 Pout:外部位置 Zc:晶片進出料區 Zt:晶片檢測區 2: Feeding and distributing module 3: Chip transfer module 4: Multi-layer architecture test module 5: Main controller 6: Temperature control module 7: Calibration components 11: Wafer inspection module 12: Feed box 13: Good product box 14: Defective product box 15: Extraction tray carrier 22: Upper module 23: Lower module 24: Feed box 25: Output box 26: Empty Magazine 27: Transport shuttle table 28: Feeding and distributing transfer unit 29: Tray transfer unit 31:Laser ranging unit 40:Accommodating space 41: shelf 42:Test unit 42A: The first test unit 42B: The second test unit 42C: Second test unit 71: circular boss 241: Tray to be tested 251: Complete test tray 261: empty tray 271: Wafer holding tank 421: crimping head 422: Test seat 423: wafer shuttle car 424: Negative pressure nozzle D1: the first direction D2: Second direction Dp: wafer pick and place device IC1: electronic component under test IC2: Finished testing electronic components P1: first position P2: second position P11: The initial position of the first boss P12: End position of the first boss P1C: first midpoint position P21: The starting position of the second boss P22: End position of the second boss P2C: second midpoint position Pc: Center position of intersection point Pin: internal position Pout: external position Zc: Wafer in and out area Zt: Wafer detection zone
圖1係習知半導體晶片檢測機台之立體示意圖。 圖2係本發明電子元件檢測設備一較佳實施例之示意圖。 圖3係本發明多層架構測試模組一較佳實施例之示意圖。 圖4A係本發明多層架構測試模組一較佳實施例之晶片梭車位於第一位置之示意圖。 圖4B係本發明多層架構測試模組一較佳實施例之晶片梭車位於第二位置之示意圖。 圖5係本發明供料及分料模組一較佳實施例之示意圖。 圖6係本發明校準元件一較佳實施例之立體圖。 FIG. 1 is a three-dimensional schematic diagram of a conventional semiconductor wafer testing machine. Fig. 2 is a schematic diagram of a preferred embodiment of the electronic component testing equipment of the present invention. Fig. 3 is a schematic diagram of a preferred embodiment of the multi-layer structure test module of the present invention. FIG. 4A is a schematic diagram of a preferred embodiment of the multi-layer structure test module of the present invention where the wafer shuttle is located at the first position. FIG. 4B is a schematic diagram of a wafer shuttle in a second position of a preferred embodiment of the multi-layer structure testing module of the present invention. Fig. 5 is a schematic diagram of a preferred embodiment of the feeding and distributing module of the present invention. Fig. 6 is a perspective view of a preferred embodiment of the calibration element of the present invention.
2:供料及分料模組 3:晶片移載模組 4:多層架構測試模組 5:主控制器 6:溫控模組 7:校準元件 24:供料匣 25:出料匣 26:空料匣 27:搬運梭台 31:雷射測距單元 71:圓形凸台 241:待測料盤 251:完測料盤 261:空料盤 271:晶片容置槽 Pin:內部位置 Pout:外部位置 2: Feeding and distributing module 3: Chip transfer module 4: Multi-layer architecture test module 5: Main controller 6: Temperature control module 7: Calibration components 24: Feed box 25: Output box 26: Empty Magazine 27: Transport shuttle table 31:Laser ranging unit 71: circular boss 241: Tray to be tested 251: Complete test tray 261: empty tray 271: Wafer holding tank Pin: internal position Pout: external position
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