TWI791920B - Methods of forming semiconductor devices - Google Patents

Abstract

A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Description

Manufacturing method of semiconductor device

Embodiments of the present invention relate to semiconductor manufacturing technology, in particular to semiconductor devices and manufacturing methods thereof.

As the size of the integrated circuit becomes smaller and the speed of the integrated circuit becomes higher and higher, the transistor requires a higher driving current and has a smaller size. Therefore, Fin Field-Effect Transistors (FinFETs) have been developed. FinFETs consist of vertical semiconductor fins on a substrate. Semiconductor fins are used to form source and drain regions, and to form channel regions between the source and drain regions. A shallow trench isolation (STI) region is formed to define the semiconductor fins. The FinFET also includes a gate stack formed on the sidewalls and top surface of the semiconductor fin.

In the formation of the shallow trench isolation region and the formation of the fin field effect transistor, the shallow trench isolation region is first formed, for example, using a flowable oxide, and then using ultraviolet (Ultra-Violet, UV) curing or in oxygen-containing Thermal oxidation in ambient for post-processing. Then, the corresponding wafers are annealed.

According to some of the embodiments of the present invention, a semiconductor device manufacturing method is provided Law. The method comprises: etching a semiconductor substrate to form a trench; depositing a dielectric layer using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition cycle comprises pulsing hexachlorodisilane to the semiconductor substrate; purging hexachlorodisilane; pulsing triethylamine to the semiconductor substrate; and purging triethylamine; and annealing the dielectric layer.

According to some other embodiments among the embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises depositing a dielectric layer on a semiconductor strip, wherein the deposition of the dielectric layer comprises a cycle, and the cycle comprises: attaching silicon and chlorine atoms to oxygen atoms on the semiconductor strip; substituting nitrogen atoms and alkyl groups a chlorine atom; and a first portion replacing the nitrogen atom and the alkyl group with an oxygen atom; a second portion removing the nitrogen atom and the alkyl group with an OH bond; and annealing the dielectric layer to form a Si-O-Si bond.

According to still other embodiments among the embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method includes forming a first semiconductor strip; depositing a dielectric layer comprising silicon oxide doped with carbon, wherein the dielectric layer comprises: a horizontal portion; and a vertical portion connected to one end of the horizontal portion, wherein the vertical portion contacting the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes above the top surface of the vertical portion to form a semiconductor fin; and forming a gate stack extending over the sidewall and top surface of the semiconductor fin.

10:Wafer

20: base

22: Well area

26: Semiconductor strip

28: Pad oxide layer

30: hard mask layer

32: Groove

32A: narrow groove

32B: wide groove

34,40: Dielectric layer

34A: top surface

36: interface

38: Gap

42:Shallow trench isolation area

44: fins

46: dummy fins

48: Gate dielectric

50: Gate electrode

52:Gate stack

54:Fin Field Effect Transistor

56: Contact etch stop layer

58:Interlayer dielectric

110: substrate layer

112, 114, 116, 118: structure

130,132,134,202,204,206,208,210,212,214,216,218,220,222,224: process

136,138: Atomic Layer Deposition Cycle

200: Process flow

310,312,314,316: value

318,320: line

D1, D2: Depth

T1, T2: Thickness

W1, W2: width

The contents of the embodiments of the present invention can be better understood by referring to the following detailed description and accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, many features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

Figures 1, 2A, 2B, and 3-9 illustrate forming shallow trench isolation (Shallow Trench Isolation) according to some embodiments. Schematic cross-sectional view of the Trench Isolation (STI) region and the intermediate stages of the FinFET.

FIG. 10 illustrates an Atomic Layer Deposition (ALD) cycle for forming a SiNOCH film, according to some embodiments.

Figures 11A and 11B illustrate the chemical structures and symbols of hexachlorodisilane and triethylamine, respectively, according to some embodiments.

Figure 12 depicts a schematic chemical structure of a SiNOCH film, according to some embodiments.

Figure 13 schematically depicts a seam separating two parts of a SiNOCH film, according to some embodiments.

FIG. 14 depicts a schematic chemical structure of a SiNOCH film after a wet annealing process, according to some embodiments.

Figures 15 and 16 schematically illustrate a bond at a seam after a low temperature wet anneal process and a high temperature wet anneal process, respectively, according to some embodiments.

FIG. 17 shows a schematic chemical structure of silicon oxide after a dry annealing process, according to some embodiments.

Figure 18 schematically depicts cross-linking at seams, according to some embodiments.

FIG. 19 illustrates the effect of converting Si—N bonds to Si—OH bonds through a low temperature wet annealing process, according to some embodiments.

FIG. 20 shows the carbon concentration as a function of depth for different low temperatures used in the wet annealing process, according to some embodiments.

FIG. 21 illustrates the effect of wet annealing conditions on nitrogen concentration, carbon concentration, and expansion ratio in a deposited dielectric film, according to some embodiments.

FIG. 22 illustrates a process flow for forming STIs and FinFETs, according to some embodiments.

The following provides a number of different embodiments, or examples, for implementing different components of an embodiment of the invention. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these are just examples, not intended to limit the embodiments of the present invention. For example, if it is mentioned in the description that the first component is formed on or over the second component, it may include an embodiment where the first component is in direct contact with the second component, or it may include an additional component formed between the first component and the second component. An embodiment in which the first part and the second part are not in direct contact between the two parts. In addition, the embodiments of the present invention may repeatedly use reference numerals and/or letters in different examples. This repetition is for simplicity and clarity and does not imply a specific relationship between the different embodiments and/or configurations discussed.

In addition, this text may use spatially relative terms such as "under", "below", "below", "above", " Above" and similar terms, these spatially relative terms are used to describe the relationship between one (some) element or component and another (some) element or component as shown in the drawings. These spatially relative terms encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

A shallow trench isolation region, a fin field effect transistor and a forming method thereof are provided. Intermediate stages in the formation process of STIs and FinFETs are shown according to some embodiments. Some variations of some embodiments are discussed. Throughout the various schematic diagrams and illustrative embodiments, like reference numerals are used to refer to like elements. According to some of the embodiments of the present invention, the shallow trench isolation region is formed by forming a SiNOCH film, and then performing an annealing process to convert the Si-N-C bonds in the SiNOCH film into Si-OH bonds, and then convert them into Si-OH bonds. O-Si bond. Through these processes, the resulting shallow trench isolation regions have no or There are generally no gaps and seams.

Embodiments will be described with a specific background, namely, a STI formation process by forming a conformal STI layer. The concepts of the discussed embodiments can also be applied to the construction and processing of other structures, including but not limited to any other gap-fill process where silicon oxide is to be filled. The embodiments discussed herein will provide examples to enable the subject matter of the embodiments of the invention to be made or used, and those of ordinary skill in the art to which the invention pertains will readily appreciate modifications that can be made while remaining within the intended scope of the various embodiments Inside. Like reference numerals and symbols in the following figures indicate like components. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Figures 1, 2A, 2B and 3-9 illustrate schematic cross-sectional views of intermediate stages of forming STIs and portions of FinFETs according to some of the embodiments of the present invention. The corresponding process is also schematically shown in the process flow 200 shown in FIG. 22 .

In Figure 1, a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk (bulk) semiconductor substrate, a semiconductor-on-insulator (Semiconductor-On-Insulator, SOI) substrate or similar substrates, which can be doped (for example with p-type or n-type dopants ) or unadulterated. The semiconductor substrate (also referred to as the substrate) 20 may be a part of the wafer 10 , such as a silicon wafer. In general, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (Buried Oxide, BOX) layer, a silicon oxide layer or similar film layers. The insulating layer is disposed on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, Contains SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or combination of the foregoing.

Referring further to FIG. 1 , a well region 22 is formed in substrate 20 . The corresponding process is depicted as process 202 in the process flow 200 shown in FIG. 22 . According to some embodiments of the present invention, the well region 22 is a p-type well region formed by implanting p-type impurities into the substrate 20, and the p-type impurities may be boron, indium or similar impurities. According to other embodiments of the present invention, the well region 22 is an n-type well region, which is formed by implanting n-type impurities into the substrate 20, and the n-type impurities may be phosphorus, arsenic, antimony or similar impurities . The formed well region 22 may extend to the top surface of the substrate 20 . The n-type or p-type impurity concentration may be equal to or less than 10 ¹⁸ cm ⁻³ , for example, in the range of about 10 ¹⁷ cm ⁻³ to about 10 ¹⁸ cm ⁻³ .

Referring to FIG. 2A , a pad oxide layer 28 and a hard mask layer 30 are formed on a semiconductor substrate 20 . The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some of the embodiments of the present invention, the pad oxide layer 28 is formed in a thermal oxidation process in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30 . The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30 . According to some of the embodiments of the present invention, the hard mask layer 30 is formed of silicon nitride, for example, by Low-Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the embodiments of the present invention, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). A patterned photoresist (not shown) is formed over the hard mask layer 30 . Then, using the patterned photoresist as an etch mask, the hard mask layer 30 and the pad oxide layer 28 are patterned to form a patterned hard mask (also referred to as a hard mask) as shown in FIG. 2A. cover layer)30.

The patterned hard mask layer 30 then acts as an etch mask to etch the pad oxide layer 28 and the substrate 20, thereby forming trenches 32 in the substrate 20, as shown in FIG. 2A. The corresponding process is in the 22nd The process flow 200 shown in the figure is shown as a process 204 . According to some of the embodiments of the present invention, the grooves 32 are formed as groove bars whose length directions are parallel to each other. The portion of semiconductor substrate 20 between trenches 32 is referred to hereinafter as semiconductor strip 26 .

FIG. 2B shows a schematic cross-sectional view of the reference section 2B-2B in FIG. 2A. To simplify the discussion, two semiconductor strips 26 are shown with the trench between them referred to as narrow trench 32A, while there may be a group of closely spaced semiconductor strips 26 separated from each other by narrow trench 32A. According to some embodiments, narrow trench 32A has a small width W1, which may be less than about 250 Å, or in the range of about 100 Å to about 250 Å. For example, there may also be wide trenches on the opposite outer sides of closely arranged groups of semiconductor strips 26 . The width W2 of the wide trench 32B is greater than the width W1 , eg, the ratio W2 / W1 is greater than about 2.0. Width W2 may also be greater than about 150Å. Trenches (also referred to as narrow trenches) 32A and (also referred to as wide trenches) 32B are collectively referred to as trenches 32 . According to some of the embodiments of the present invention, the depth D1 of the narrow trench 32A is smaller than the depth D2 of the wide trench 32B.

3 and 4 illustrate intermediate stages in the growth/deposition of the dielectric layer 34 . The corresponding process is depicted as process 206 in process flow 200 shown in FIG. 22 . At the beginning of the deposition process, the wafer 10 is placed in an Atomic Layer Deposition (ALD) chamber (not shown), where ALD cycles are performed to grow the dielectric layer 34 conformally. FIG. 3 shows the initial growth of the dielectric layer 34 , which is conformal and the thickness T1 of the horizontal portion of the dielectric layer 34 is equal to the thickness T2 of the vertical portion of the dielectric layer 34 .

FIG. 10 schematically depicts the intermediate chemical structure during the growth of the dielectric layer 34 . The intermediate structures shown in Figure 10 are labeled with reference numerals 112, 114, 116 and 118 to distinguish the structures produced by the different stages. Wafer 10 includes base layer 110, which may represent components exposed in FIG. Mask 30, as long as these components are exposed at the beginning of the deposition process. The initial structure in Figure 10 is referred to as structure 112 . In the illustrated example, the substrate layer 110 is illustrated as comprising silicon, which may be in the form of crystalline silicon, amorphous silicon, polycrystalline silicon, or silicon in compounds. According to some of the embodiments of the present invention, Si—OH bonds are formed on the surface of the silicon-containing layer (also referred to as substrate layer) 110 due to the formation of native oxide and exposure to moisture. The substrate layer 110 may include other types of silicon-containing materials, such as silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, or similar materials. As shown in FIG. 3 , dielectric layer 34 may also be deposited on other non-silicon-containing layers, such as liner layer 28 and hard mask 30 .

Referring again to FIG. 10, in process 130, Hexachlorodisilane (HCD) is introduced/pulsed into the ALD chamber in which wafer 10 (FIG. 3) is placed. The corresponding process is depicted as process 208 in process flow 200 shown in FIG. 22 . HCD has the chemical formula (SiCl ₃ ) ₂ . Figure 11A depicts the chemical formula of the HCD molecule, according to some embodiments. The chemical formula shows that the HCD molecule contains a chlorine atom bonded to two silicon atoms. When the HCD is pulsed into the atomic layer deposition chamber, the wafer 10 is heated to a temperature of, for example, about 550°C to about 670°C. The OH bonds as shown in structure 112 are broken and the silicon atoms bond to the oxygen atoms along with the chlorine atoms bonded to them to form O-Si-Cl bonds. The resulting structure is referred to as structure 114. According to some of the embodiments of the present invention, when the HCD is introduced, the plasma is not turned on. The HCD gas may be maintained in the atomic layer deposition chamber for a period of about 20 seconds to about 25 seconds. According to some embodiments, the pressure of the atomic layer deposition chamber may range from about 100 Pascal (Pa) to about 150 Pa.

Next, the HCD is purged from the ALD chamber. The corresponding process is also shown as process 208 in the process flow 200 shown in FIG. 22 . In process 132, a process gas comprising nitrogen atoms bonded to an alkyl group may be pulsed into the atomic layer deposition chamber. For example, triethylamine can be pulsed. The corresponding process is depicted as process 210 in the process flow 200 shown in FIG. 22 . Triethylamine may have the formula N(CH ₂ CH ₃ ) ₃ , which includes a nitrogen atom bonded to three ethyl groups (CH ₂ CH ₃ ). Figure 11B depicts the chemical formula of triethylamine according to some embodiments. The chemical formula shows that triethylamine contains a nitrogen atom bonded to three ethyl groups, and each "<" symbol attached to the N atom represents an ethyl group ( _CH2CH3 or a _CH2 molecule bonded to _{a CH3 molecule} ). With the introduction/pulsing of triethylamine, the temperature of wafer 10 also remains elevated, eg, in the range of about 550°C to about 670°C. The temperature can also be kept the same as that of the HCD-introduced process. According to some of the embodiments of the present invention, the plasma is not turned on when triethylamine is introduced. The pressure of the ALD amine chamber may range from about 800 Pa to about 1,000 Pa during the pulse of triethylamine.

Structure 114 is reacted with triethylamine. The resulting structure is referred to as structure 116. The Si-Cl bond in structure 114 is broken so that the nitrogen atom (eg in triethylamine) can bond to the silicon atom. A silicon atom may be bonded to three nitrogen atoms, each of which is also bonded to two ethyl groups. In process 132, triethylamine may be maintained in the ALD chamber for a period of about 5 seconds to about 15 seconds, and then the triethylamine is purged from the ALD chamber.

Next, oxygen (O ₂ ) is pulsed into the ALD chamber as shown in process 134 of FIG. 10 . The corresponding process is depicted as process 212 in the process flow 200 shown in FIG. 22 . In process 212 , structure 116 is reacted with oxygen to produce structure 118 . Alkyl groups such as ethyl in structure 116 help convert Si-N to Si-O bonds, for example, by breaking Si-N bonds in structure 116 and bonding silicon atoms to Oxygen atom. Some nitrogen atoms and the ethyl groups to which they are bonded can also remain bonded to the silicon atom. Some oxygen atoms can bond to two silicon atoms to create crosslinks between some silicon atoms. According to some of the embodiments of the invention, the plasma is not turned on when the oxygen is introduced. During the pulse of oxygen, the pressure of the atomic layer deposition chamber may range from about 800 Pa to about 1,000 Pa. Oxygen may be maintained in the ALD chamber for a period of about 5 seconds to about 15 seconds and then purged from the ALD chamber.

Among the processes discussed above, the combination of processes 130 and 132 may be referred to as an ALD cycle 136, which results in the growth of an atomic layer comprising silicon atoms and correspondingly bonded nitrogen atoms and ethyl groups. Additionally, the combination of processes 130, 132, and 134 may also be referred to as an atomic layer deposition cycle 138, which results in the growth of an atomic layer comprising silicon atoms and corresponding bonded nitrogen atoms and ethyl groups, and bonded oxygen atom. According to some embodiments, the atomic layer produced by atomic layer deposition cycle 138 has a thickness of about 1 Å.

After process 134 is completed, ALD cycle 138 comprising processes 130 , 132 , and 134 is repeated to deposit multiple atomic layers to form dielectric layer 34 , as shown in FIG. 4 . In subsequent ALD cycles, Si-O bonds and Si-N bonds formed in previous ALD cycles can be broken, and Si-Cl bonds can be formed due to the pulse of HCD. The Si-Cl bond can then be replaced with a Si-N bond and the corresponding ethyl group. _O2 can then be used to form Si-O bonds, which replace some Si-N bonds. Figure 12 shows an additional atomic layer as an example. It should be understood that there may be many atomic layers depending on the desired thickness of dielectric layer 34 . The deposited dielectric layer 34 is a SiONCH layer.

The atomic layer deposition cycle 138 is repeated until the resulting dielectric layer 34 has the desired thickness. For example, as shown in FIG. 4 , portions of dielectric layer 34 grown from adjacent semiconductor strips 26 grow toward each other and eventually contact each other to create interface 36 . It should be understood that seams, also referred to as interfaces 36, may be created. Some voids 38 may also be created at the interface 36 , these voids 38 may be due to small grooves on the sidewalls of the semiconductor strips 26 . It should be understood that although portions of dielectric layer 34 grown from adjacent semiconductor strips 26 contact each other, these portions only contact each other without forming crosslinks between them. For example, FIG. 13 schematically depicts a seam/interface 36 formed between a left portion of dielectric layer 34 and a right portion of dielectric layer 34, between boundary atoms of the left and right portions No crosslinks were formed.

According to some of the embodiments of the present invention, after the atomic layer deposition cycle 138, the resulting dielectric layer 34 has a carbon percentage in the range of about 1% to about 15%, and a nitrogen percentage in the range of about 5% to about 20%. % range. The remaining elements in the dielectric layer 34 are mainly silicon and oxygen, and the atomic ratio of silicon to oxygen may be about 1.5:2 to about 1:2.5. The ratio may be, for example, about 1:2.

After the deposition (growth) of the dielectric layer 34, an annealing process is performed. The corresponding process is depicted as process 214 in process flow 200 shown in FIG. 22 . According to some embodiments of the embodiments of the present invention, the annealing process includes a low-temperature wet annealing process (process 216 ), a high-temperature wet annealing process (process 218 ), and a dry annealing process (process 220 ). The low temperature process and the high temperature wet annealing process can be performed using steam (H ₂ O) as the process gas. The dry annealing process may use nitrogen (N ₂ ), argon or similar gas as a carrier gas. The annealing process is discussed below with reference to FIGS. 14-20.

According to some embodiments of the embodiments of the present invention, a low-temperature wet annealing process is performed first. The corresponding process is depicted as process 216 in process flow 200 shown in FIG. 22 . The low temperature wet annealing process is performed at a relatively low temperature of about 300°C to about 450°C. The low temperature wet annealing process may last for about 3 hours to about 5 hours. The pressure during low temperature annealing may be about 1 atmosphere. The low temperature wet annealing process has two functions. The first function is to permeate water/steam ( _H2O ) molecules into the dielectric layer 34, as shown schematically in FIG. 15, where solid dots represent _H2O molecules. The second function is to partially convert Si-NC bonds, Si-NC ₂ H ₅ bonds and Si-N-Si bonds in the dielectric layer 34 into Si-OH bonds. The temperature is controlled to a temperature high enough to cause at least partial conversion.

Fig. 21 shows some experimental results, where the X-axis represents annealing conditions, including annealing temperature and annealing time. The letter "C" for each x-axis value indicates the annealing temperature in degrees Celsius, the letter "M" indicates the annealing time in minutes, and the letter "H" indicates the annealing time in hours. For example, "W200C30M" indicates the corresponding value obtained when the wafer was annealed at 200°C for 30 minutes. There are three Y-axes representing nitrogen ([N]) atomic percent, carbon ([C]) atomic percent, and the expansion rate of the annealed dielectric layer. The results in Figure 21 indicate that the carbon and nitrogen percentages are high prior to the annealing process (corresponding to the x-axis value "NA"). As the annealing process continues and/or uses higher temperatures, the percentages of carbon and nitrogen decrease to some extent, such as less than 1%. This means that the original carbon and nitrogen atoms (shown in Figure 12) start converting to OH, as shown in Figure 14. In addition, as shown in Fig. 21, when the temperature is higher than 450°C, the expansion rate of the dielectric film may increase. Because the surface portion of the dielectric layer 34 expands earlier than the interior, the expansion of the surface portion of the dielectric layer 34 can disadvantageously prevent H ₂ O molecules from penetrating and reaching the interior of the dielectric layer 34 . Therefore, to avoid premature expansion of the surface portion of the dielectric layer 34 , the low temperature wet annealing process is performed at a temperature at which the dielectric layer 34 does not expand (eg, less than about 450° C.). On the other hand, in order to improve conversion efficiency and vapor permeation efficiency, the low temperature wet annealing process is performed at a not too low temperature, and the temperature may range from about 300°C to about 450°C.

Figures 19 and 20 show the results measured from the samples and show similar results for the low temperature wet annealing processes at 300°C and 450°C. FIG. 19 plots etch rate (of dielectric layer 34 ) as a function of depth into dielectric layer 34 . The etch rate is indicative of the composition of the dielectric layer 34, eg how many C and N atoms are replaced by OH groups. The values 310 and 312 are the results of annealing at 300°C for 4 hours. The values 314 and 316 are the results of annealing at 450°C for 4 hours. The samples were also annealed under the same higher annealing temperature conditions (600°C for 2 hours) and the same dry annealing temperature conditions (600°C for 1 hour). Figure 19 shows that although the low temperature wet annealing processes were performed at different temperatures, their etch rates at different depths of the samples were similar, which indicated that the low temperature wet annealing temperatures of 300°C and 450°C did not affect the H ₂ O The penetration of molecules makes the difference.

FIG. 20 plots carbon concentration as a function of depth into dielectric layer 34 . Line 318 is also the result of a low temperature wet anneal at 300°C for 4 hours. Line 320 is the result of a low temperature wet anneal at 450°C for 4 hours. The samples corresponding to lines 318 and 320 were also annealed under the same higher annealing temperature conditions (600°C for 2 hours) and the same dry annealing temperature conditions (600°C for 1 hour). Figure 20 shows that although the low temperature wet annealing process was performed at different temperatures, the carbon percentage, which is an indicator of the conversion rate (from CN to OH) of the samples at different depths, is similar. These results indicate that adopting 300°C or 450°C as the temperature of the low-temperature annealing process does not cause a difference in the penetration of H ₂ O molecules.

After the low temperature wet annealing process, a high temperature wet annealing process is performed. The corresponding process is depicted as process 218 in process flow 200 shown in FIG. 22 . The high temperature wet annealing process is performed at a relatively high temperature of about 450°C to about 650°C. The high temperature wet annealing process may last for about 1.5 hours to about 2.5 hours. The pressure of the high temperature annealing process may be about 1 atmosphere. As shown in FIG. 16, the temperature is high enough to effectively convert the Si-N bonds in the dielectric layer 34 to Si-OH bonds. On the other hand, the temperature must not be so high as to cause excessive oxidation of the semiconductor material. For example, when the semiconductor strip 26 comprises SiGe, the temperature of the high temperature annealing process should be lower than about 650°C. Otherwise, SiGe may be oxidized. Silicon can also be oxidized at temperatures above about 650°C, although at a lower rate. Accordingly, the temperature of the high temperature wet annealing process may be in the range of about 500°C to about 650°C or in the range of about 500°C to about 600°C.

The high temperature wet annealing process causes Si-N bonds and Si-O bonds to break. An alkyl group attached to the N atom is also disconnected from the nitrogen atom. The OH group attaches to the broken bond. The resulting chemical structure can be schematically depicted in Figure 14. Fig. 16 shows the structure at the interface 36 (also refer to Fig. 4). The Si—OH bonds formed in the portions of the dielectric layer 34 on both sides of the interface 36 are closely disposed, and the portions of the dielectric layer 34 on both sides of the interface 36 may be in contact with each other. but does not form crosslinks. During the high temperature wet annealing process, the dielectric layer 34 expands, and the rate of expansion in volume can be as high as about 10%. As a result of the expansion, portions of the dielectric layer 34 on both sides of the interface 36 are in close contact with each other and can be eliminated. Remove seam 36 (Figs. 4 and 15) and void 38 (Fig. 4). This makes the subsequent cross-linking process possible.

After the high temperature wet annealing process, a dry annealing process is performed to cross-link. The corresponding process is depicted as process 220 in the process flow 200 shown in FIG. 22 . An oxygen-free process gas such as nitrogen (N ₂ ), argon, or the like can be used as the process gas. Dry annealing temperature can not be too high or too low. If the temperature is too low, the OH bonds may not be broken and crosslinking may not be achieved. If the temperature is too high, the semiconductor (such as SiGe) may mix with the surrounding material. According to some of the embodiments of the present invention, the dry annealing process is performed at a temperature of about 550°C to about 650°C. The dry annealing process may last for about 0.5 hours to about 1.5 hours. The pressure may be about 1 atmosphere. A carrier gas can be used to carry away the generated _H2O vapor. The carrier gas can be nitrogen, argon or similar gas.

During the dry annealing process, OH bonds and Si-O bonds (Figures 14 and 16) are broken, and the broken H and OH combine to form H ₂ O molecules, as shown in Figure 18. Due to the loss of H atoms, these bonds are left dangling and may bond with Si to form silicon oxide (SiO ₂ ). After the dry annealing process is completed, a small amount of carbon and nitrogen atoms may remain in the silicon oxide (dielectric layer 34 ), wherein the carbon and nitrogen atomic percentages are less than about 1%, and may be about 0.5% to about 1.0%. This differs from shallow trench isolation regions formed using conventional methods where carbon may not be present.

As shown in Figure 18, the silicon atoms on both sides of the pre-existing interface/seam 36 are cross-linked by oxygen atoms. Crosslinks are thus formed between portions of dielectric layer 34 on both sides of interface 36 . _H2O molecules represented by solid dots are carried away. Figure 5 shows the resulting structure where the seams/interfaces formed during the deposition process have been eliminated and there may no longer be distinguishable interfaces.

According to some embodiments, narrow trenches 32A are completely filled in a previous process. Since the deposition of the dielectric layer 34 is carried out using the atomic layer deposition of the compliant deposition method, when the deposition process is completed , wide trench 32B may not be completely filled. Therefore, as shown in FIG. 5, some portions of wide trench 32B are left unfilled. The portion of dielectric layer 34 in wide trench 32B is compliant.

Referring to FIG. 6 , the remaining wide trenches 32B are filled with a dielectric layer 40 . The corresponding process is depicted as process 222 in process flow 200 shown in FIG. 22 . The dielectric layer 40 can also be a deposited silicon nitride layer, a carbon-containing dielectric or similar materials. The dielectric layer 40 is formed using, for example, atomic layer deposition, high-density plasma chemical vapor deposition (High-Density Plasma Chemical Vapor Deposition, HDPCVD) or Chemical Vapor Deposition (Chemical Vapor Deposition, CVD). The dielectric layer 40 can also be formed of SiOCN by Flowable Chemical Vapor Deposition (FCVD), spin-on coating or similar processes. Dielectric layer 40 is deposited to a height above the top surface of dielectric layer 34 .

Referring to FIG. 7, a planarization process such as a chemical mechanical polish (CMP) process or a mechanical grinding (grinding) process is then performed to remove excess portions of the dielectric material. The remainder of the dielectric material is shallow trench isolation region 42 . The corresponding process is also shown as process 222 in the process flow 200 shown in FIG. 22 . The planarization process can be performed using the hard mask 30 as a CMP stop layer. The shallow trench isolation regions 42 between closely spaced semiconductor strips 26 may be formed of a homogeneous material that extends all the way to the opposing semiconductor strips 26 . Shallow trench isolation regions formed in wide trenches may include compliant dielectric layers 34 and 40 . Although one vertical portion is shown, dielectric layer 34 will have vertical portions on both sides of dielectric region (also referred to as STI region) 42 and contact the two sidewalls of dielectric region 42 .

Then, hard mask 30 and pad oxide layer 28 are etched. As shown in FIG. 8 , the dielectric layer 34 is etched back so that the tops of the semiconductor strips 26 protrude above the top surface 34A of the remainder of the STI region 42 to form protruding fins 44 . The corresponding process is depicted as process 224 in process flow 200 shown in FIG. 22 . Etching may be performed using a dry etching process, such as using HF ₃ and NH ₃ as etching gases. According to an alternative embodiment of the present invention, the etchback of the dielectric layer 34 is performed using a wet etching process. Etching chemicals may include, for example, HF solutions.

During the etch back process, dielectric layer 40 is not etched such that dummy (dielectric) fins 46 protrude above top surface 34A of the remainder of STI region 42 . The dummy dielectric fins 46 are so named because the features (also known as dummy fins) 46 protrude above the adjacent dielectric layer 34, thereby forming fins that are different from the Typical semiconductor fins for transistors, these fins cannot be used to form FinFETs. Due to the compliant deposition of dielectric layer 34 , when narrow trench 32A is filled with dielectric layer 34 , wide trench 32B ( FIG. 2B ) is not completely filled. This enables the filling of the dielectric layer 40 and the formation of the dummy fins 46 . When the size of the FinFET is very small, the generation of dummy fins helps to improve the device performance of the FinFET.

In subsequent formation processes, FinFETs 54 are formed based on the protruding semiconductor fins 44 ( FIG. 9 ). FIG. 9 shows a schematic cross-sectional view of the protruding fin 44 and the gate stack 52 extending over the sidewalls and top surfaces of the protruding semiconductor fin (also referred to as fin) 44 and dummy fin 46 . The sample forming process is briefly discussed in the following paragraphs.

According to some of the embodiments of the present invention, dummy gate stacks (not shown) are formed extending on the sidewalls and top surfaces of the protruding semiconductor fins 44 and dummy fins 46 . Then, gate spacers (not shown) are formed on sidewalls of the dummy gate stacks. Source/drain regions (not shown) are then formed on both sides of the dummy gate stack and the gate spacer, for example by etching the portion of the protruding semiconductor fin 44 not covered by the dummy gate stack, And source/drain regions are epitaxially grown. Then, a contact etch stop layer (Contact Etch Stop Layer, CESL) 56 and an inter-layer dielectric (Inter-Layer Dielectric, ILD) 58 are formed to cover the source/drain regions and the dummy gate stack. However Thereafter, the dummy gate stack is etched to re-expose the protruding semiconductor fins 44 . A gate stack 52 including gate dielectric 48 and gate electrode 50 is then formed in the recess left by the removed dummy gate stack.

Embodiments of the embodiments of the invention have some advantageous features. Traditional STI formation uses flowable chemical vapor deposition, which cannot form a compliant dielectric layer and therefore cannot form dummy dielectric fins. According to some of the embodiments of the present invention, an atomic layer deposition process is used to form a carbon and nitrogen doped film, and the film is then annealed to form a silicon oxide film. Through a series of low temperature wet annealing process, high temperature wet annealing process and dry annealing process, seams and voids generated during the atomic layer deposition process can be eliminated.

According to some of the embodiments of the present invention, a method comprises etching a semiconductor substrate to form a trench; depositing a dielectric layer using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition cycle comprises pulsing hexachlorodisilane to the semiconductor substrate; purging hexachlorodisilane; pulsing triethylamine to the semiconductor substrate; and purging triethylamine; and performing an annealing process on the dielectric layer. In one embodiment, the ALD cycle further includes pulsing oxygen (O ₂ ) to the semiconductor substrate after purging the triethylamine; and purging the oxygen. In one embodiment, the method further includes repeating the ALD cycle including pulsed oxygen. In one embodiment, the method further includes repeating the ALD cycle. In one embodiment, the annealing process includes a low temperature annealing process performed at a first temperature; a high temperature annealing process performed at a second temperature higher than the first temperature; and a third temperature higher than the first temperature. dry annealing process. In one embodiment, the low temperature annealing process is performed at a first temperature, and the first temperature is in a range from about 300°C to about 450°C. In one embodiment, the high temperature annealing process is performed at a second temperature ranging from about 500°C to about 650°C. In one embodiment, the dry annealing process is performed at a third temperature, and the third temperature is in the range of about 500°C to about 650°C.

According to some of the embodiments of the present invention, a method comprises: depositing a dielectric layer on a semiconductor strip, wherein the deposition of the dielectric layer comprises a cycle, and the cycle comprises: attaching silicon and chlorine atoms to the semiconductor strip on the oxygen atom of the oxygen atom; replacing the chlorine atom with a nitrogen atom and an alkyl group; and replacing the nitrogen atom and the first part of the alkyl group with an oxygen atom; removing the nitrogen atom and the second part of the alkyl group with an OH bond; and annealing the dielectric layer to form Si-O-Si bonds. In one embodiment, the cycle comprises an atomic layer deposition (ALD) cycle, and the attachment of silicon and chlorine atoms comprises pulsing hexachlorodisilane; and purging hexachlorodisilane. In one embodiment, the cycle includes an atomic layer deposition cycle, and the substitution of chlorine atoms includes pulsing triethylamine; and purging triethylamine. In one embodiment, the cycle comprises an atomic layer deposition cycle, and the substitution of nitrogen atoms and the first portion of the alkyl group comprises pulsing oxygen ( _O2 ); and purging oxygen. In one embodiment, the annealing of the dielectric layer comprises driving _H2O molecules into the dielectric layer at a first temperature; replacing nitrogen atoms with oxygen atoms and OH molecules at a second temperature higher than the first temperature and an alkyl group; and forming a Si—O—Si bond through a dry annealing process, wherein the dry annealing process is performed at a third temperature higher than the first temperature. In one embodiment, the dielectric layer is formed in the trench, the semiconductor strip is located on one side of the trench, and the method further includes: forming an additional dielectric region, wherein the semiconductor strip and the additional dielectric region contact the dielectric layer sidewalls of a portion of the dielectric layer; etching back the portion of the dielectric layer wherein the tops of the semiconductor strips form semiconductor fins and the tops of the additional dielectric regions form dummy dielectric fins; and forming gate stacks on top of the semiconductor fins and additional dielectric regions are extended.

According to some of the embodiments of the present invention, an integrated circuit structure includes a first semiconductor strip; a dielectric layer including silicon oxide in which carbon is doped, wherein the dielectric layer includes: a horizontal portion; and a vertical portion Partially connected to one end of the horizontal portion, wherein the vertical portion contacts the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip is higher than the top surface of the vertical portion to form a semiconductor fin; and the gate is stacked on the semiconductor fin Extended on the side walls and top surface. In one embodiment, The integrated circuit structure further includes a dielectric region overlapping the horizontal portion, wherein a top of the dielectric region protrudes above a top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack is further formed on a sidewall of the dummy dielectric fin. and extend on the top surface. In one embodiment, the dielectric region and the dielectric layer are formed of different dielectric materials. In one embodiment, the integrated circuit structure further includes an interlayer dielectric overlapping the dummy dielectric fin. In one embodiment, the vertical portion and the horizontal portion have the same thickness. In one embodiment, the integrated circuit structure further includes a second semiconductor strip; and an additional dielectric layer, wherein the additional dielectric layer is formed of the same homogeneous dielectric material as that of the dielectric layer, and wherein the additional There are no seams in the dielectric layer.

According to some of the embodiments of the present invention, a method includes forming a first semiconductor strip; depositing a dielectric layer comprising silicon oxide in which carbon is doped, wherein the dielectric layer comprises: a horizontal portion; and a vertical portion Partially connected to one end of the horizontal portion, wherein the vertical portion contacts the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes above the top surface of the vertical portion to form a semiconductor fin; and forming a gate stack on the semiconductor fin Extends on the sidewalls and top surface of the sheet. In one embodiment, the method further includes forming a dielectric region overlapping the horizontal portion, wherein the top of the dielectric region protrudes above the top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack is further formed on the dummy dielectric. The electrical fins extend on the sidewalls and top surfaces. In one embodiment, the dielectric region and the dielectric layer are formed of different dielectric materials. In one embodiment, the method further includes depositing an ILD overlapping the dummy dielectric fin. In one embodiment, the dielectric layer is deposited using a compliant deposition process. In one embodiment, the method further includes: after depositing the dielectric layer and before forming the gate stack: performing a low temperature wet annealing process at a first temperature; after the low temperature wet annealing process, performing a high temperature wet annealing process at a second temperature; and performing a dry annealing process at a third temperature higher than the first temperature after the high temperature wet annealing process.

The above summarizes the parts of several embodiments, so that there is a general knowledge in the technical field of the invention People with ordinary knowledge can better understand the aspects of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or advantages as the embodiments introduced here. Those with ordinary knowledge in the technical field of the invention should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present invention, and they can be made without departing from the spirit and scope of the embodiments of the present invention. Various changes, substitutions and adjustments.

200: Process flow

202,204,206,208,210,212,214,216,218,220,222,224: process

Claims (14)

A method of manufacturing a semiconductor device, comprising: etching a semiconductor substrate to form a trench; depositing a dielectric layer using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition The cycle includes: pulse hexachlorodisilane to the semiconductor substrate; purge the hexachlorodisilane; pulse triethylamine to the semiconductor substrate; purge the triethylamine; pulsing to the semiconductor substrate; and purging the oxygen; and performing an annealing process on the dielectric layer. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising repeating the atomic layer deposition cycle including pulsed oxygen. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising repeating the atomic layer deposition cycle. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the annealing process includes: a low-temperature annealing process performed at a first temperature; a high-temperature annealing process performed at a second temperature higher than the first temperature process; and a dry annealing process performed at a third temperature higher than the first temperature. The method for manufacturing a semiconductor device as claimed in claim 4, wherein the first temperature is carried out at the first temperature performing the low temperature annealing process, the first temperature is in the range of about 300°C to about 450°C; performing the high temperature annealing process at the second temperature, the second temperature is in the range of about 500°C to about 650°C; and/ Or perform the dry annealing process at the third temperature, the third temperature is in the range of about 500°C to about 650°C. A method of manufacturing a semiconductor device, comprising: depositing a dielectric layer on a semiconductor strip, wherein the deposition of the dielectric layer includes a cycle, and the cycle includes: oxygen attaching silicon and chlorine atoms to the semiconductor strip atomically; replacing the chlorine atom with a nitrogen atom and an alkyl group; and replacing the nitrogen atom and the first plurality of moieties of the alkyl group with an oxygen atom; removing the nitrogen atom and the plurality of second moieties of the alkyl group with an OH bond; and The dielectric layer is annealed to form Si-O-Si bonds. The method for manufacturing a semiconductor device according to claim 6, wherein the cycle includes an atomic layer deposition cycle, and the attachment of the silicon and chlorine atoms includes: pulsed hexachlorodisilane; and purging the hexachlorodisilane; the chlorine atom The substitution comprises: pulsing triethylamine; and purging the triethylamine; and/or the substitution of the nitrogen atoms and the first moieties of the alkyl comprises: pulsing oxygen; and purging the oxygen. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the annealing of the dielectric layer comprises: driving H ₂ O molecules into the dielectric layer at a first temperature; Substituting the nitrogen atoms and alkyl groups with oxygen atoms and OH molecules at a second temperature; and forming the Si—O—Si bond via a dry annealing process, wherein the dry annealing process is at a first temperature higher than the first temperature at three temperatures. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the dielectric layer is formed in a trench, the semiconductor strip is located on one side of the trench, and the method further includes: forming an additional dielectric region, wherein the semiconductor strip and the additional dielectric region contact sidewalls of a portion of the dielectric layer; etching back the portion of the dielectric layer wherein a semiconductor fin is formed on top of the semiconductor strip and the additional dielectric layer forming a dummy dielectric fin on top of the region; and forming a gate stack extending over the semiconductor fin and the additional dielectric region. A method of manufacturing a semiconductor device, comprising: forming a first semiconductor strip; depositing a dielectric layer comprising silicon oxide into which carbon is doped, wherein the deposition of the dielectric layer comprises a cycle, the cycle comprising: attaching silicon and chlorine atoms to oxygen atoms on the first semiconductor strip; replacing the chlorine atoms with nitrogen atoms and alkyl groups; and replacing portions of the nitrogen atoms and alkyl groups with oxygen atoms, and wherein the intermediate The electrical layer includes: a horizontal portion; and a vertical portion connected to one end of the horizontal portion, wherein the vertical portion contacts the first semiconductor sidewalls of the lower portion of the body strip, wherein the top of the first semiconductor strip protrudes above the top surface of the vertical portion to form a semiconductor fin; and forming a gate stack extending over the sidewall and top surface of the semiconductor fin. The method of manufacturing a semiconductor device according to claim 10, further comprising: forming a dielectric region overlapping the horizontal portion, wherein the top of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin sheet, wherein the gate stack further extends on sidewalls and top surfaces of the dummy dielectric fin. The method of manufacturing a semiconductor device according to claim 11, wherein the dielectric region and the dielectric layer are formed of different dielectric materials. The method for manufacturing a semiconductor device according to claim 11 or 12, further comprising depositing an interlayer dielectric overlapping the dummy dielectric fin. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein the dielectric layer is deposited using a conformal deposition process.

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