TWI790563B - Switch circuit - Google Patents

Abstract

A switch circuit includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire.

Description

switch chip

The present invention relates to a multiplexer and demultiplexer, in particular to a bidirectional passive N-circuit that uses a complementary metal oxide semiconductor process (CMOS) and packaged wire (bond wire) to replace the wiring of a die. :M multiplexer and M:N demultiplexer, which are applied to data flow transmission of high-speed signals (where N is greater than M).

While processors often process data in parallel, data is communicated serially from point to point. In the sending end of the communication circuit, the serializer circuit is often used to serialize the parallel data, while in the receiving end, the deserializer circuit is often used to parallelize the serialized data. Two-way communication circuits often use devices that perform serialization and parallelization. This device is called a serializer (serializer) and a deserializer (deserializer), or more commonly called a SerDes.

In some applications, data can be transmitted from one point to another at different data rates, or from one point to any number of other points. SerDes devices used in communication circuits operate at correspondingly different frequencies when data is transmitted at different transmission rates.

The present invention proposes a switch chip (multiplexer/demultiplexer), and uses packaged wires (bond wire) to replace the metal wiring in the die, so that the inductance value between the various components in the die can be improved. Precise control also increases design flexibility. In addition, the conduction loss is reduced due to the low resistance value of the wire, and the wire does not have the dielectric loss of the metal traces in the die. In addition, the use of wires to couple different components in the chip helps to expand the operating bandwidth of the switch chip, so that the switch chip can achieve the purpose of wide operating frequency band, low insertion loss, low return loss and high isolation.

In view of this, the present invention proposes a switch chip. The switch chip includes a first switch element, a first electrostatic discharge protection device and a second electrostatic discharge protection device. The first switch element is electrically coupled between a first pad and a second pad. The first electrostatic discharge protection device is electrically coupled to a third pad, wherein the third pad is electrically coupled to the first pad through a first wire. The second electrostatic discharge protection device is electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the second pad through a second wire.

The present invention further provides a switch chip. The switch chip includes a first switch element, a second switch element, a first ESD protection device, a second ESD protection device and a third ESD protection device. The first switch element is electrically coupled between a first pad and a second pad. The second switch element is electrically coupled between the first pad and a third pad. The first electrostatic discharge protection device is electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the first pad through a first wire. The second ESD protection device is electrically coupled to a fifth pad, wherein the fifth pad is electrically coupled to the second pad through a second wire. The third ESD protection device is electrically coupled to a sixth pad, wherein the sixth pad is electrically coupled to the third pad through a third wire.

The present invention further proposes a switch chip, the switch chip includes a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, a sixth switch element, a first ESD protection device, a second ESD protection device, a third ESD protection device, a fourth ESD protection device and a fifth ESD protection device. The first switch element is electrically coupled between a first pad and a second pad. The second switch element is electrically coupled between the second pad and a third pad. The third switch element is electrically coupled between a fourth pad and a fifth pad. The fourth switch element is electrically coupled between the fifth pad and a sixth pad. The fifth switch element is electrically coupled between a seventh pad and an eighth pad. The sixth switch element is electrically coupled between the eighth pad and a ninth pad. The first electrostatic discharge protection device is electrically coupled to a tenth pad, wherein the tenth pad is electrically coupled to the first pad through a first wire, and is electrically coupled to the first pad through a second wire. The fourth pad is electrically coupled to the seventh pad through a third wire. The second electrostatic discharge protection device is electrically coupled to an eleventh pad, wherein the eleventh pad is electrically coupled to the third pad through a fourth wire, and electrically coupled to the third pad through a fifth wire. connected to the sixth pad and electrically coupled to the ninth pad through a sixth wire. The third ESD protection device is electrically coupled to a twelfth pad, wherein the twelfth pad is electrically coupled to the second pad through a seventh wire. The fourth ESD protection device is electrically coupled to a thirteenth pad, wherein the thirteenth pad is electrically coupled to the fifth pad through an eighth wire. The fifth ESD protection device is electrically coupled to a fourteenth pad, wherein the fourteenth pad is electrically coupled to the eighth pad through a ninth wire.

The present invention further provides a switch chip, and the switch chip includes a first pin, a second pin and a die. The first pin is electrically coupled to a first pad through a first wire. The second pin is electrically coupled to the second pad through a second wire. The die includes a first switch element, one end of the first switch element is coupled to the first pad through a third wire, and the other end of the first switch element is coupled to the second pad through a fourth wire. Pad.

The present invention further provides a switch chip, and the switch chip includes a first pin, a second pin, a third pin and a die. The first pin is electrically coupled to a first pad through a first wire. The second pin is electrically coupled to a second pad through a second wire. The third pin is electrically coupled to a third pad through a third wire. The die includes a first switch element and a second switch element. One end of the first switch element is electrically coupled to the second pad through a fourth wire, and one end of the second switch element is electrically coupled to the third pad through a fifth wire. The first switch The other end of the element and the other end of the second switching element are electrically coupled to the first pad through a sixth wire.

The present invention further provides a switch chip. The switch chip includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a die. The first pin is electrically coupled to a first pad through a first wire. The second pin is electrically coupled to a second pad through a second wire. The third pin is electrically coupled to a third pad through a third wire. The fourth pin is electrically coupled to a fourth pad through a fourth wire. The fifth pin is electrically coupled to a fifth pad through a fifth wire. The die includes a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element and a sixth switch element. One end of the first switch element is electrically coupled to the first pad through a sixth wire. One end of the second switching element is electrically coupled to the second pad through a seventh wire, and the other end of the first switching element and the other end of the second switching element are electrically coupled together through an eighth wire. on the third pad above. One end of the third switching element is electrically coupled to the first pad through a ninth wire. One end of the fourth switching element is electrically coupled to the second pad through a tenth wire, and the other end of the third switching element and the other end of the fourth switching element are electrically coupled together through an eleventh wire. on the fourth pad above. One end of the fifth switch element is electrically coupled to the first pad through a twelfth wire. One end of the sixth switching element is electrically coupled to the second pad through a thirteenth wire, and the other end of the fifth switching element and the other end of the sixth switching element are jointly connected through a fourteenth wire. electrically coupled to the above-mentioned fifth pad in a manner.

The following descriptions are examples of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as a limitation of the present invention. The scope of the present invention should be defined by the scope of the patent application.

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layer, and/or section should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of some embodiments of the present disclosure. and/or sections.

It should be noted that the following disclosure may provide multiple embodiments or examples for practicing different features of the present invention. The specific component examples and arrangements described below are only used to briefly illustrate the spirit of the present invention, and are not intended to limit the scope of the present invention. In addition, the following description may reuse the same symbol or word in multiple examples. However, the purpose of repeated use is only to provide simplified and clear description, not to limit the relationship between the embodiments and/or configurations discussed below. Furthermore, descriptions of one feature described in the following specification as being connected to, coupled to, and/or formed on another feature, etc., may actually include many different embodiments, including those features being in direct contact, or including other additional features. The features are formed between the features, etc., such that the features are not in direct contact.

Multiplexer (MUX) and demultiplexer (DEMUX) are commonly used components in high-speed signal specifications (such as USB, SATA, PCIe, etc.), which are used to change the transmission/reception path and direction of the connected high-speed data stream . Generally speaking, the related circuits of multiplexer and demultiplexer include ESD protection circuit, transistor (MOSFET), gate control signal and metal lines connecting transistor and data stream input and output. The N:M multiplexer and the M:N demultiplexer in the present invention are suitable for transmission of high-speed data streams (such as 1 Gbps or higher), where N is greater than M. Generally speaking, if the parasitic capacitance (Parasitics) produced by the ESD protection circuit and the transistor is not absorbed, it will increase the signal loss of the data stream through the multiplexer and demultiplexer, and affect the signal integrity of the data stream. , thereby reducing the transmission speed of the data stream that can be used by the multiplexer and the demultiplexer. In order to reduce the adverse effects of these parasitic capacitances on the multiplexer and demultiplexer, the common method is to use the thick metal layer on the process provided by the fab to realize the inductor to absorb these parasitic capacitances, thereby reducing these parasitic capacitances. The effect of parasitic capacitance. Another approach is to use a complementary metal-oxide-semiconductor-silicon-on-insulator (CMOS SOI) process. Although the above two methods can reduce the adverse effects of the parasitic capacitance on the multiplexer and the demultiplexer, they also increase the cost of the product.

Since the multiplexer and the demultiplexer are composed of at least one switch element, a switch element will be used for description below. FIG. 1 shows a schematic diagram of a switch chip according to an embodiment. As shown in FIG. 1 , in one embodiment, the switch chip 100 is a packaged chip with a lead frame, wherein the switch chip 100 includes a die 110, a first pin 120 and a second pin. 130 feet. The die 110 includes a first switching element 111 , a first ESD protection device ESD1 , a second ESD protection device ESD2 , a first pad PAD1 , and a second pad PAD2 .

The first switch element 111 is coupled to the first pad PAD1 through the first trace TR1 , and coupled to the second pad PAD2 through the second trace TR2 . The first ESD protection device ESD1 is electrically coupled to the first pad PAD1, and the second ESD protection device ESD2 is electrically coupled to the second pad PAD2. According to an embodiment of the present invention, the first trace TR1 and the second trace TR2 are metal traces in the die 110 . According to an embodiment of the present invention, the third trace TR3 and the fourth trace TR4 are metal traces in the die 110 . The first ESD protection device ESD1 is coupled to the first pad PAD1 through the third trace TR3, and the second ESD protection device ESD2 is coupled to the second pad PAD2 through the fourth trace TR4. The first electrostatic discharge protection device ESD1 and the second electrostatic discharge protection device ESD2 are used to protect the first switch element 111 from the electrostatic discharge received by the first pad PAD1 and the second pad PAD2 .

The distance between the first electrostatic discharge protection device ESD1 to the first pad PAD1 and the second electrostatic discharge protection device ESD2 to the second pad PAD2 is extremely short, so the first electrostatic discharge protection device ESD1 to the first pad is ignored here The effects produced by PAD1 and the traces TR3 and TR4 between the second electrostatic discharge protection device ESD2 and the second pad PAD2 are for simplicity of description.

As shown in FIG. 1, the first pad PAD1 of the die 110 is electrically coupled to the first pin 120 through the first wire BL1, and the second pad PAD2 of the die 110 is electrically coupled through the second wire BL2. Being coupled to the second pin 130 enables the die 110 to be electrically coupled to other external circuits through the first pin 120 and the second pin 130 .

In order to make the switch chip 100 suitable for wide bandwidth and achieve low insertion loss, low return loss and high isolation, the switch chip 100 is It is a passive element, so how to reduce the dielectric loss and conduction loss of the first trace TR1 and the second trace TR2 will become the key to the design.

In addition, since it is difficult to control the precision of the etching process in the manufacturing process of the die 110, the width and length of the first trace TR1 and the second trace TR2 often drift, which affects impedance matching and causes signal loss. .

The present invention proposes a method of using packaged wires instead of metal traces in a die as the connection between both ends of the switching element and the input and output ends of the data stream. In one embodiment, the switching element can be a transistor, and the traces on the drain and source of the transistor will be replaced by packaging bondwires. Because the use of wires as inductors can absorb the parasitic capacitance mentioned earlier better, and wires have a higher Q value than metal traces used in the process, thus reducing the conduction loss of data streams while maintaining It ensures the integrity of the signal under high-speed transmission, and then achieves the design of broadband, low loss and low return loss.

Since the multiplexer and the demultiplexer are composed of at least one switch element, a switch element will be used to describe the present invention below. FIG. 2 is a schematic diagram showing a switch chip according to an embodiment of the present invention. As shown in FIG. 2 , in one embodiment, the switch chip 200 is a package chip with a lead frame, wherein the switch chip 200 includes a die 210 , a first pin 120 and a second pin 130 . Die 210 includes a first switching element 211, a first electrostatic discharge protection device ESD1, a second electrostatic discharge protection device ESD2, a first pad PAD1, a second pad PAD2, a third pad PAD3, a fourth pad PAD4, The third wire BL3 and the fourth wire BL4.

As shown in FIG. 2, the first switch element 211 is electrically coupled between the first pad PAD1 and the second pad PAD2, and the first electrostatic discharge protection device ESD1 is electrically coupled to the third pad PAD3. , the second electrostatic discharge protection device ESD2 is electrically coupled to the fourth pad PAD4. In addition, the first pad PAD1 is electrically coupled to the third pad PAD3 through the third wire BL3 , and the second pad PAD2 is electrically coupled to the fourth pad PAD4 through the fourth wire BL4 .

According to an embodiment of the present invention, the distance between the first switch element 211 and the first pad PAD1 and the second pad PAD2 is extremely short, so the effect of the wiring therebetween can be ignored. According to an embodiment of the present invention, the distance between the first electrostatic discharge protection device ESD1 to the third pad PAD3 and the second electrostatic discharge protection device ESD2 to the fourth pad PAD4 is extremely short, so the first electrostatic discharge is ignored here. The effect produced by the wiring between the protection device ESD1 to the third pad PAD3 and the second electrostatic discharge protection device ESD2 to the fourth pad PAD4. According to many embodiments of the present invention, the first switch element 211 is an N-type transistor or a P-type transistor. According to other embodiments of the present invention, the first switch element 211 can be other electronic elements that can be used as switches.

Comparing the grain 210 in Figure 2 with the grain 110 in Figure 1, the first trace TR1 in Figure 1 is replaced by the third wire BL3, and the second trace TR2 in Figure 1 is replaced by the fourth wire BL4 replaced. According to one embodiment of the present invention, the third wire BL3 and the fourth wire BL4 are metal wires used to connect pads and lead frames in the package, and the first wire BL1 and the second wire BL2 are also metal wires, which are used for Connecting the pads in the die to the pads.

FIG. 3 shows an equivalent circuit diagram of a switch chip according to an embodiment of the present invention. As shown in FIG. 3 , the equivalent circuit 300 is an equivalent circuit of the switch chip 200 . The first wire inductance LBL1, the second wire inductance LBL2, the third wire inductance LBL3, and the fourth wire inductance LBL4 are equivalent inductances of the first wire BL1, the second wire BL2, the third wire BL3, and the fourth wire BL4, respectively, The first ESD protection device capacitor CESD1 and the second ESD protection device capacitor CESD2 are parasitic capacitances generated by the first ESD protection device ESD1 and the second ESD protection device ESD2 respectively.

The first switch element 211 is equivalent to an ideal switch SW, a first (parasitic) capacitance C1 and a second (parasitic) capacitance C2, and the parasitic capacitance of the external circuit board coupled to the first pin 120 can be equivalent to the first The circuit board capacitance CPCB1, the parasitic capacitance of the external circuit board coupled to the second pin 130 can be equivalent to the second circuit board capacitance CPCB2.

According to one embodiment of the present invention, as shown in FIG. 3, the switch chip 200 can be equivalent to an LC-ladder filter, and the operation of the switch chip 200 can be extended by designing the LC-ladder filter. bandwidth. In addition, since the inductance value of the wire is related to its length, it is easier to precisely control the inductance value of the wire than it is difficult to control the width and length of the internal wiring of the chip due to the limitation of the etching process. Moreover, the wire has the characteristic of low impedance, and the use of the wire to replace the internal wiring of the chip helps to reduce the loss of the signal. Therefore, using wires instead of the internal wires of the chip helps the switch chip 200 to more easily achieve the application goals of broadband, low insertion loss, low return loss and high isolation.

FIG. 4 is a schematic diagram showing a 1:2 demultiplexer or a 2:1 multiplexer composed of a plurality of switching elements according to another embodiment of the present invention. As shown in FIG. 4, in one embodiment, the switch chip 400 is a package chip with a lead frame, wherein the switch chip 400 includes a die 410, a first pin 420, a second pin 430 and The third pin 440 .

Die 410 includes a first switching element 411, a second switching element 412, a first electrostatic discharge protection device ESD1, a second electrostatic discharge protection device ESD2, a third electrostatic discharge protection device ESD3, a first pad PAD1, a second pad PAD2 , the third pad PAD3 , the fourth pad PAD4 , the fifth pad PAD5 and the sixth pad PAD6 .

The first switch element 411 is electrically coupled between the first pad PAD1 and the second pad PAD2 , and the second switch element 412 is electrically coupled between the first pad PAD1 and the third pad PAD3 . According to an embodiment of the present invention, the distances between the first switching element 411 and the second switching element 412 and the first pad PAD1, the second pad PAD2, and the third pad PAD3 are extremely short, so the distance between them can be ignored. The effect of wiring. The fourth pad PAD4 is electrically coupled to the first pin 420 through the first wire BL1, the fifth pad PAD5 is electrically coupled to the second pin 430 through the second wire BL2, and the sixth pad is electrically coupled to the second pin 430 through the second wire BL2. PAD6 is electrically coupled to the third pin 440 through the third wire BL3 .

The first ESD protection device ESD1 is electrically coupled to the fourth pad PAD4, the second ESD protection device ESD2 is electrically coupled to the fifth pad PAD5, and the third ESD protection device ESD3 is electrically coupled to the sixth pad PAD6. According to an embodiment of the present invention, since the first electrostatic discharge protection device ESD1 to the fourth pad PAD4, the second electrostatic discharge protection device ESD2 to the fifth pad PAD5, and the third electrostatic discharge protection device ESD3 to the sixth pad PAD6 The distance between them is extremely short, so the first ESD protection device ESD1 to the fourth pad PAD4, the second ESD protection device ESD2 to the fifth pad PAD5, and the third ESD protection device ESD3 to the sixth pad are ignored here. The effect of the traces between pads PAD6.

The first pad PAD1 is electrically coupled to the fourth pad PAD4 through the fourth wire BL4, the second pad PAD2 is electrically coupled to the fifth pad PAD5 through the fifth wire BL5, and the third pad is electrically coupled to the fifth pad PAD5 through the fifth wire BL5. PAD3 is electrically coupled to the sixth pad PAD6 through the sixth wire BL6 .

According to an embodiment of the present invention, the first pin 420 receives the first signal S1. According to an embodiment of the present invention, when the first switch element 411 is turned on and the second switch element 412 is turned off, the switch chip 400 provides the first signal S1 to the second pin 430 . According to another embodiment of the present invention, when the first switch element 411 is off and the second switch element 412 is on, the switch chip 400 provides the first signal S1 to the third pin 440 . At this time, the switch chip 400 is equivalent to a 1:2 demultiplexer (its control terminal is not shown).

According to another embodiment of the present invention, the second pin 430 receives the second signal S2 and the third pin 440 receives the third signal S3. According to an embodiment of the present invention, when the first switch element 411 is turned on and the second switch element 412 is turned off, the switch chip 400 provides the second signal S2 to the first pin 420 . According to another embodiment of the present invention, when the first switch element 411 is off and the second switch element 412 is on, the switch circuit 400 provides the third signal S3 to the first pin 420 . At this time, the switch chip 400 is equivalent to a 2:1 multiplexer (its control terminal is not shown).

In other words, the switch chip 400 can provide the signal received by the first pin 420 to the second pin 430 and/or the third pin 430 according to whether the first switch element 411 and the second switch element 412 are turned on or not. On the other hand, the switch chip 400 can also selectively provide the signal received by the second pin 430 or the signal received by the third pin 440 to the first switch element 411 and the second switch element 412 according to whether they are turned on or not. Pin 420. In one embodiment, the switch chip 400 can be used as one of a serializer and a deserializer, which is used in high-speed transmission signal transmission, such as transmission signals (TX, RX, etc.) in USB, SATA, PCIE and other specifications. ), but not limited to this.

The switch chip 400 in FIG. 4 is used to transmit and/or receive single-ended signals, and two identical switch chips 400 can be used to transmit and/or receive differential signals. In order to simplify the description, here only the transmission and/or reception of single-ended signals is taken as an example for description and explanation, and is not limited thereto in any form.

FIG. 5 is a schematic diagram showing a 2:3 demultiplexer or a 3:2 multiplexer composed of a plurality of switching elements according to another embodiment of the present invention. As shown in FIG. 5, in one embodiment, the switch chip 500 is a packaged chip with a lead frame (lead frame), wherein the switch chip 500 includes a die 510, a first pin 520, a second pin 530, The third pin 540 , the fourth pin 550 and the fifth pin 560 .

Die 510 includes a first switching element 511, a second switching element 512, a third switching element 513, a fourth switching element 514, a fifth switching element 515, a sixth switching element 516, a first pad PAD1, a second pad PAD2 , third pad PAD3 , fourth pad PAD4 , fifth pad PAD5 , sixth pad PAD6 , seventh pad PAD7 , eighth pad PAD8 and ninth pad PAD9 .

The first switch element 511 is electrically coupled between the first pad PAD1 and the second pad PAD2 , and the second switch element 512 is electrically coupled between the second pad PAD2 and the third pad PAD3 . The third switch element 513 is electrically coupled between the fourth pad PAD4 and the fifth pad PAD5 , and the fourth switch element 514 is electrically coupled between the fifth pad and the sixth pad PAD6 . The fifth switch element 515 is electrically coupled between the seventh pad PAD7 and the eighth pad PAD8 , and the sixth switch element 516 is electrically coupled between the eighth pad PAD8 and the ninth pad PAD9 .

According to one embodiment of the present invention, since the distances between the first switch element 511, the second switch element 512, and the third switch element 513 and the respective pads PAD1, PAD2, PAD3, PAD4, and PAD5 are extremely short, the fourth switch The distances between the element 514, the fifth switching element 515, and the sixth switching element 516 and the respective pads PAD5, PAD6, PAD7, PAD8, and PAD9 are extremely short, so the wiring between each switching element and the pads is ignored here. the resulting effect.

As shown in FIG. 5 , the die 510 further includes a tenth pad PAD10 , an eleventh pad PAD11 , a twelfth pad PAD12 , a thirteenth pad PAD13 and a fourteenth pad PAD14 . The tenth pad PAD10 is electrically coupled to the first pin 520 through the first wire BL1 , and the eleventh pad PAD11 is electrically coupled to the second pin 530 through the second wire BL2 . The twelfth pad PAD12 is electrically coupled to the third pin 540 through the third wire BL3, the thirteenth pad PAD13 is electrically coupled to the fourth pin 550 through the fourth wire BL4, and the fourteenth pad is electrically coupled to the fourth pin 550 through the fourth wire BL4. The pad PAD14 is electrically coupled to the fifth pin 560 through the fifth wire BL5 .

As shown in FIG. 5, the die 510 further includes a first ESD protection device ESD1, a second ESD protection device ESD2, a third ESD protection device ESD3, a fourth ESD protection device ESD4 and a fifth ESD protection device ESD5. The first ESD protection device ESD1 is electrically coupled to the tenth pad PAD10, the second ESD protection device ESD2 is electrically coupled to the eleventh pad PAD11, and the third ESD protection device ESD3 is electrically coupled The fourth ESD protection device ESD4 is electrically coupled to the thirteenth pad PAD13 , and the fifth ESD protection device ESD5 is electrically coupled to the fourteenth pad PAD14 .

According to an embodiment of the present invention, since the first ESD protection device ESD1, the second ESD protection device ESD2, the third ESD protection device ESD3, the fourth ESD protection device ESD4 and the fifth ESD protection device ESD5 respectively The distances between the tenth pad PAD10 , the eleventh pad PAD11 , the twelfth pad PAD12 , the thirteenth pad PAD13 and the fourteenth pad PAD14 are extremely short, so the ESD protection devices and the fourteenth pads are ignored here. The effect of traces between pads.

As shown in FIG. 5 , the first pad PAD1 is electrically coupled to the tenth pad PAD10 through the sixth wire BL6 . The second pad PAD2 is electrically coupled to the twelfth pad PAD12 through the seventh wire BL7 . The third pad PAD3 is electrically coupled to the eleventh pad PAD11 through the eighth wire BL8 . The fourth pad PAD4 is electrically coupled to the tenth pad PAD10 through the ninth wire BL9 . The fifth pad PAD5 is electrically coupled to the thirteenth pad PAD13 through the tenth wire BL10 . The sixth pad PAD6 is electrically coupled to the eleventh pad PAD11 through the eleventh wire BL11 .

The seventh pad PAD7 is electrically coupled to the tenth pad PAD10 through the twelfth wire BL12 . The eighth pad PAD8 is electrically coupled to the fourteenth pad PAD14 through the thirteenth wire BL13 . The ninth pad PAD9 is electrically coupled to the eleventh pad PAD11 through the fourteenth wire BL14 .

According to an embodiment of the present invention, when the first pin 520 receives the first signal S1 and the second pin 530 receives the second signal S2, the switching chip 500 according to the first switching element 511, the second switching element 512, the third Whether the switch element 513, the fourth switch element 514, the fifth switch element 515, and the sixth switch element 516 are turned on, and respectively provide the first signal S1 and/or the second signal S2 to the third pin 540, the fourth pin Any one of the pin 550 and the fifth pin 560 . At this time, the switch chip 500 is equivalent to a 2:3 demultiplexer (its control terminal is not shown).

According to another embodiment of the present invention, when the third pin 540 receives the third signal S3, the fourth pin 550 receives the fourth signal S4, and the fifth pin 560 receives the fifth signal S5, the switch chip 500 according to the first Whether the switch element 511, the second switch element 512, the third switch element 513, the fourth switch element 514, the fifth switch element 515, and the sixth switch element 516 are turned on, and the third signal S3, the fourth signal S4, and the At least one of the five signals S5 is provided to the first pin 520 and/or the second pin 530 . At this time, the switch chip 500 is equivalent to a 3:2 multiplexer (its control terminal is not shown).

In one embodiment, the switch chip 500 can be used as one of a serializer and a deserializer, which is applied in high-speed transmission signal transmission, such as USB, SATA, PCIE and other specifications, but it is not limited thereto.

According to other embodiments of the present invention, two identical switch chips 500 can be used to transmit and/or receive differential signals. In order to simplify the description, here only the transmission and/or reception of single-ended signals is taken as an example for description and explanation, and is not limited thereto in any form.

In the switch chips 100 , 200 , 400 , and 500 mentioned above, only the parts related to the present invention are shown, and other irrelevant circuits are not shown.

The present invention proposes a switch chip (multiplexer/demultiplexer), and uses packaged wires (bond wire) to replace the metal wiring in the die, so that the inductance value between the various components in the die can be improved. Precise control also increases design flexibility. In addition, the conduction loss is reduced due to the low resistance value of the wire, and the wire does not have the dielectric loss of the metal traces in the die. In addition, the use of wires to couple different components in the chip helps to expand the operating bandwidth of the switch chip, so that the switch chip can achieve the purpose of wide operating frequency band, low insertion loss, low return loss and high isolation.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification, and anyone with ordinary knowledge in the technical field can implement some In the disclosure content of the examples, it is understood that the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps can be used as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described here. Some examples of this disclosure use . Therefore, the protection scope of the present disclosure includes the above-mentioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes combinations of various patent application scopes and embodiments.

100, 200, 400, 500: switch chip 110, 210, 410, 510: grain 120, 420, 520: the first pin 130, 430, 530: the second pin 111, 211, 411, 511: the first switching element 300: Equivalent circuit 412, 512: the second switching element 513: the third switching element 514: the fourth switching element 515: fifth switching element 516: the sixth switching element 440, 540: the third pin 550: The fourth pin 560: fifth pin ESD1: The first electrostatic discharge protection device ESD2: The second electrostatic discharge protection device ESD3: The third electrostatic discharge protection device PAD1: the first pad PAD2: The second pad PAD3: The third pad PAD4: The fourth pad PAD5: The fifth pad PAD6: The sixth pad PAD7: The seventh pad PAD8: Eighth pad PAD9: ninth pad PAD10: Tenth pad PAD11: Eleventh pad PAD12: The twelfth pad PAD13: the thirteenth pad PAD14: the fourteenth pad BL1: first wire BL2: Second wire BL3: Third wire BL4: Fourth wire BL5: fifth wire BL6: Sixth wire BL7: Seventh wire BL8: Eighth wire BL9: Ninth wire BL10: tenth wire BL11: Eleventh wire BL12: Twelfth wire BL13: Thirteenth wire PAD14: Fourteenth wire TR1: the first trace TR2: the second trace TR3: The third trace TR4: The fourth trace LBL1: first lead inductance LBL2: Second lead inductance LBL3: third lead inductance LBL4: Fourth lead inductance CESD1: Capacitance of the first electrostatic discharge protection device CESD2: Capacitance of the second electrostatic discharge protection device SW: ideal switch C1: First (parasitic) capacitance C2: Second (parasitic) capacitance CPCB1: First circuit board capacitance CPCB2: second circuit board capacitance S1: first signal S2: Second signal S3: The third signal S4: Fourth signal S5: fifth signal

FIG. 1 is a schematic diagram showing a switch chip according to an embodiment; Figure 2 is a schematic diagram showing a switch chip according to an embodiment of the present invention; Figure 3 shows an equivalent circuit diagram of a switch chip according to an embodiment of the present invention; Fig. 4 shows a schematic diagram of a 1:2 demultiplexer or a 2:1 multiplexer composed of a plurality of switching elements according to another embodiment of the present invention; and FIG. 5 is a schematic diagram showing a 2:3 demultiplexer or a 3:2 multiplexer composed of a plurality of switching elements according to another embodiment of the present invention.

200: switch chip

210: grain

211: the first switching element

120: The first pin

130: Second pin

ESD1: The first electrostatic discharge protection device

ESD2: The second electrostatic discharge protection device

PAD1: the first pad

PAD2: The second pad

PAD3: The third pad

PAD4: The fourth pad

BL1: first wire

BL2: Second wire

BL3: Third wire

BL4: Fourth wire

Claims (33)

A switch chip, comprising: a first switch element directly coupled between a first pad and a second pad; a first electrostatic discharge protection device electrically coupled to a third pad, wherein The third pad is electrically coupled to the first pad through a first wire; and a second electrostatic discharge protection device is electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to a fourth pad through a first wire. The two wires are electrically coupled to the second pad. The switch chip according to claim 1, wherein the first switching element, the first electrostatic discharge protection device, the second electrostatic discharge protection device, the first pad, the second pad, the third pad, and the The fourth pad is located in a die. The switch chip as in claim 2, further comprising: a first pin electrically coupled to the third pad through a third wire; and a second pin electrically coupled to the third pad through a fourth wire above the fourth pad. The switch chip according to claim 3, wherein the above-mentioned die, the above-mentioned first pin and the above-mentioned second pin are located in a package. A switch chip, comprising: a first switch element electrically coupled between a first pad and a second pad; a second switch element electrically coupled between the first pad and a third pad; A first electrostatic discharge protection device, electrically coupled to a fourth pad, wherein the fourth pad is electrically coupled to the first pad through a first wire; a second electrostatic discharge protection device, electrically Sexually coupled to a fifth pad, wherein the fifth pad is electrically coupled to the second pad through a second wire; and a third electrostatic discharge protection device is electrically coupled to a sixth pad pad, wherein the sixth pad is electrically coupled to the third pad through a third wire. The switching chip according to claim 5, wherein the first switching element, the second switching element, the first electrostatic discharge protection device, the second electrostatic discharge protection device, and the third electrostatic discharge protection device are located in one die . The switch chip as in claim 6, further comprising: a first pin electrically coupled to the fourth pad through a fourth wire; a second pin electrically coupled to the above pad through a fifth wire a fifth pad; and A third pin is electrically coupled to the sixth pad through a sixth wire. The switch chip according to claim 7, wherein the above-mentioned die, the above-mentioned first pin, the above-mentioned second pin, and the above-mentioned third pin are located in a package. The switch chip according to claim 7, wherein the first pin receives a first signal, wherein when the first switching element is conducting and the second switching element is not conducting, the first signal is provided to the above-mentioned The second pin, wherein when the first switch element is off and the second switch element is on, the first signal is provided to the third pin. The switch chip of claim 7, wherein the second pin receives a first signal, and the third pin receives a second signal, wherein when the first switching element is turned on and the second switching element is When it is not conducting, the above-mentioned first signal is provided to the above-mentioned first pin, wherein when the above-mentioned first switching element is not conducting and the above-mentioned second switching element is conducting, the above-mentioned second signal is provided to the above-mentioned first pin pins. The switch chip according to claim 5, wherein the switch chip is one of a serializer, a deserializer, an N:M multiplexer, and an M:N demultiplexer, wherein N is greater than M. A switch chip, comprising: a first switch element electrically coupled between a first pad and a second pad; a second switch element, electrically coupled between the second pad and a third pad; a third switch element, electrically coupled between a fourth pad and a fifth pad; a fourth switch element electrically coupled between the fifth pad and a sixth pad; a fifth switch element electrically coupled between a seventh pad and an eighth pad; A sixth switch element, electrically coupled between the eighth pad and a ninth pad; a first electrostatic discharge protection device, electrically coupled to a tenth pad, wherein the tenth pad electrically coupled to the first pad through a first wire, electrically coupled to the fourth pad through a second wire, and electrically coupled to the seventh pad through a third wire; a first wire Two electrostatic discharge protection devices, electrically coupled to an eleventh pad, wherein the eleventh pad is electrically coupled to the third pad through a fourth wire, and electrically coupled to the third pad through a fifth wire to the sixth pad and electrically coupled to the ninth pad through a sixth wire; a third electrostatic discharge protection device, electrically coupled to a twelfth pad, wherein the twelfth pad electrically coupled to the second pad through a seventh wire; A fourth ESD protection device electrically coupled to a thirteenth pad, wherein the thirteenth pad is electrically coupled to the fifth pad through an eighth wire; and a fifth ESD protection device The device is electrically coupled to a fourteenth pad, wherein the fourteenth pad is electrically coupled to the eighth pad through a ninth wire. The switch chip according to claim 12, wherein the first switch element to the sixth switch element, the first electrostatic discharge protection device to the fifth electrostatic discharge protection device are located in one die. The switch chip of claim 13 further includes: a first pin electrically coupled to the tenth pad through a tenth wire; a second pin electrically coupled to the tenth pad through an eleventh wire The eleventh pad; a third pin electrically coupled to the twelfth pad through a twelfth wire; a fourth pin electrically coupled to the first pad through a thirteenth wire the thirteenth pad; and a fifth pin electrically coupled to the fourteenth pad through a fourteenth wire. The switch chip according to claim 14, wherein the die, the first pin, the second pin, the third pin, the fourth pin, and the fifth pin are located in a package. The switch chip according to claim 14, wherein the first pin receives a first signal, and the second pin receives a second signal, wherein the switch chip is based on the first switch element, the second switch element, and the second switch element. Whether the third switch element, the fourth switch element, the fifth switch element, and the sixth switch element are turned on, and the first signal and/or the second signal are provided to the third pin and the fourth pin respectively. pin and one of the above-mentioned fifth pins. Such as the switch chip of claim 14, wherein the above-mentioned third pin receives a third signal, the above-mentioned fourth pin receives a fourth signal, and the above-mentioned fifth pin receives a fifth signal, wherein the above-mentioned switch chip is based on The above-mentioned first switch element, the above-mentioned second switch element, the above-mentioned third switch element, the above-mentioned fourth switch element, the above-mentioned fifth switch element and the above-mentioned sixth switch element are turned on, and the above-mentioned third signal, the above-mentioned fourth signal And at least one of the above-mentioned fifth signals is provided to the above-mentioned first pin and/or the above-mentioned second pin. The switch chip according to claim 12, wherein the switch chip is one of an N:M multiplexer and an M:N demultiplexer, wherein N is greater than M. A switch chip, comprising: a first pin electrically coupled to a first pad through a first wire; a second pin electrically coupled to a second pad through a second wire; and A die, including a first switch element, wherein one end of the first switch element is directly coupled to the first pad through a third wire, and the other end of the first switch element is directly coupled through a fourth wire to the second pad above. The switch chip according to claim 19, wherein the first pad, the second pad, the third wire, and the fourth wire are all located in the die. The switch chip according to claim 19, wherein the die further includes: a first electrostatic discharge protection device electrically coupled to the first pad; and a second electrostatic discharge protection device electrically coupled to the first pad Two pads. A switch chip, comprising: a first pin electrically coupled to a first pad through a first wire; a second pin electrically coupled to a second pad through a second wire; A third pin electrically coupled to a third pad through a third wire; and a die including: a first switch element, wherein one end of the first switch element is electrically coupled through a fourth wire coupled to the second pad; and a second switch element, wherein one end of the second switch element is electrically coupled to the third pad through a fifth wire, the other end of the first switch element and the above-mentioned The other end of the second switching element is electrically coupled to the above-mentioned first through a sixth wire. The pad, wherein the above-mentioned first wire, the above-mentioned second wire, the above-mentioned third wire, the above-mentioned fourth wire, the above-mentioned fifth wire and the above-mentioned sixth wire are all metal wires used to connect the pad and the lead frame in a package . The switch chip according to claim 22, wherein the first pad, the second pad, the third pad, the fourth wire, the fifth wire, and the sixth wire are all located in the die. The switch chip according to claim 22, wherein the above-mentioned die further includes: a first electrostatic discharge protection device electrically coupled to the first pad; a second electrostatic discharge protection device electrically coupled to the second the pad; and a third ESD protection device electrically coupled to the third pad. Such as the switch chip of claim 22, wherein the switch chip is any one of a serializer, a deserializer, an N:M multiplexer, and an M:N demultiplexer, wherein N is greater than M . The switching chip according to claim 22, wherein the first pin receives a first signal, wherein when the first switching element is conducting and the second switching element is not conducting, the first signal is provided to the above The second pin, wherein when the first switch element is off and the second switch element is on, the first signal is provided to the third pin. The switch chip according to claim 22, wherein the second pin receives a first signal, and the third pin receives a second signal, wherein when the first pin When a switching element is conducting and the second switching element is non-conducting, the first signal is provided to the first pin, wherein when the first switching element is non-conducting and the second switching element is When turned on, the second signal is provided to the first pin. A switch chip, comprising: a first pin electrically coupled to a first pad through a first wire; a second pin electrically coupled to a second pad through a second wire; A third pin is electrically coupled to a third pad through a third wire; a fourth pin is electrically coupled to a fourth pad through a fourth wire; a fifth pin is electrically coupled to a fourth pad through a fourth wire. electrically coupled to a fifth pad through a fifth wire; and a die including: a first switch element, wherein one end of the first switch element is electrically coupled to the first pad through a sixth wire Pad; a second switch element, wherein one end of the second switch element is electrically coupled to the second pad, the other end of the first switch element and the other end of the second switch element respectively through a seventh wire Commonly electrically coupled to the third pad through an eighth wire; a third switch element, wherein one end of the third switch element is electrically coupled to the first pad through a ninth wire; A fourth switching element, wherein one end of the fourth switching element is electrically coupled to the second pad through a tenth wire, and the other end of the third switching element and the other end of the fourth switching element are jointly connected through a first Eleven wires are electrically coupled to the fourth pad; a fifth switch element, wherein one end of the fifth switch element is electrically coupled to the first pad through a twelfth wire; and a sixth switch component, wherein one end of the sixth switching element is electrically coupled to the second pad through a thirteenth wire, and the other end of the fifth switching element and the other end of the sixth switching element are jointly connected through a fourteenth The wire is electrically coupled to the fifth pad. The switch chip according to claim 28, wherein the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are all located in the die. The switch chip as claimed in claim 28, wherein the above-mentioned die further includes: a first electrostatic discharge protection device electrically coupled to the first pad; a second electrostatic discharge protection device electrically coupled to the second pad; a third ESD protection device electrically coupled to the third pad; a fourth ESD protection device electrically coupled to the fourth pad; and A fifth ESD protection device, electrically coupled to the fifth pad. The switch chip according to claim 28, wherein the switch chip is one of an N:M multiplexer and an M:N demultiplexer, wherein N is greater than M. The switch chip according to claim 28, wherein the first pin receives a first signal, and the second pin receives a second signal, wherein the switch chip is based on the first switch element, the second switch element, and the second switch element. Whether the third switch element, the fourth switch element, the fifth switch element, and the sixth switch element are turned on, and the first signal and/or the second signal are provided to the third pin and the fourth pin respectively. pin and one of the above-mentioned fifth pins. Such as the switch chip of claim 28, wherein the above-mentioned third pin receives a third signal, the above-mentioned fourth pin receives a fourth signal, and the above-mentioned fifth pin receives a fifth signal, wherein the above-mentioned switch chip is based on The above-mentioned first switch element, the above-mentioned second switch element, the above-mentioned third switch element, the above-mentioned fourth switch element, the above-mentioned fifth switch element and the above-mentioned sixth switch element are turned on, and the above-mentioned third signal, the above-mentioned fourth signal And at least one of the above-mentioned fifth signals is provided to the above-mentioned first pin and/or the above-mentioned second pin.

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