TWI790008B - Dynamic random access memory structure - Google Patents

Abstract

A dynamic random access memory structure including at least one memory cell is provided. The memory cell includes a substrate, a gate structure, a first capacitor, a first bit line structure, a second capacitor, and a second bit line structure. The substrate has a first surface and a second surface opposite to each other. The gate structure penetrates through the substrate. The first capacitor is located on the first surface of the substrate. The first bit line structure is located on the second surface of the substrate. The second capacitor is located on the second surface of the substrate. The second bit line structure is located on the first surface of the substrate.

Description

Dynamic Random Access Memory Architecture

The present invention relates to a semiconductor structure, and more particularly to a dynamic random access memory (DRAM) structure.

Currently, a DRAM has been developed, which includes transistors and capacitors. In this DRAM, capacitors are used as storage nodes. However, how to further improve the bit density, electrical performance, and operating speed of the memory device is an ongoing goal.

The invention provides a dynamic random access memory structure, which can effectively improve the bit density, electrical performance and operation speed of memory elements.

The invention proposes a dynamic random access memory structure, which includes at least one memory cell. The memory cell includes a substrate, a gate structure, a first capacitor, a first bit line structure, a second capacitor and a second bit line structure. The base has a first surface and a second surface opposite to each other. The gate structure penetrates through the substrate. The first capacitor is located on the first side of the substrate. The first bit line structure is located on the second surface of the substrate. The second capacitor is located on the second side of the substrate. The second bit line structure is located on the first surface of the substrate.

According to an embodiment of the present invention, in the above DRAM structure, the substrate may include a first channel area and a second channel area. The first channel region is located between the first capacitor and the first bit line structure. The second channel region is located between the second capacitor and the second bit line structure.

According to an embodiment of the present invention, in the above DRAM structure, the memory cells may further include an isolation structure. The isolation structure is located in the substrate. The first channel region may be located at one side of the gate structure, and may be located between the gate structure and the isolation structure. The second channel region can be located on the other side of the gate structure, and can be located between the gate structure and the isolation structure.

According to an embodiment of the present invention, in the above dynamic random access memory structure, the gate structure may include a gate and a dielectric layer. The gate is located in the substrate. The dielectric layer is located between the gate and the substrate.

According to an embodiment of the present invention, in the above dynamic random access memory structure, the top view shape of the gate electrode may be striped or have branches.

According to an embodiment of the present invention, in the above DRAM structure, the dielectric layer may surround the gate.

According to an embodiment of the present invention, in the above dynamic random access memory structure, the first capacitor and the first bit line structure may be located on one side of the gate structure, and the second capacitor and the second bit line The structure can be on the other side of the gate structure.

According to an embodiment of the present invention, in the above dynamic random access memory structure, the first bit line structure may include a first bit line and a first contact window. The first bit line is located on the second surface of the substrate. The first contact window is located between the first bit line and the substrate. The second bitline structure may include a second bitline and a second contact window. The second bit line is located on the first side of the substrate. The second contact window is located between the second bit line and the substrate.

According to an embodiment of the present invention, in the above DRAM structure, the top-view shape of the first bit line and the top-view shape of the second bit line can be linear or zigzag.

According to an embodiment of the present invention, in the above dynamic random access memory structure, the memory cell may further include a first contact window and a second contact window. The first contact window is located between the first capacitor and the substrate. The second contact window is located between the second capacitor and the substrate.

Based on the above, in the DRAM structure proposed by the present invention, the gate structure runs through the substrate, the first capacitor is located on the first surface of the substrate, the first bit line structure is located on the second surface of the substrate, and the second capacitor is located on the second surface of the substrate. Two capacitors are located on the second surface of the substrate, and the second bit line structure is located on the first surface of the substrate. Therefore, a single memory cell can have two bits, thereby increasing the bit density of the memory device. In addition, since the first capacitor and the second capacitor are located on different surfaces of the substrate, it is beneficial to increase the area of the first capacitor and the area of the second capacitor. Thereby, the capacitance of the first capacitor and the capacitance of the second capacitor can be increased, thereby improving the electrical performance of the memory element. In addition, since the two bits in the memory cell share the gate structure (that is, a single gate structure can control two bits), the two bits in the memory cell can be operated simultaneously (for example, read Fetch operation), thereby increasing the operation speed of the memory device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Embodiments are listed below and described in detail with accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In order to facilitate understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustration purposes only and are not drawn to original scale. Additionally, features in perspective views, top views, and features in cross-section are not drawn to the same scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a three-dimensional schematic diagram of a DRAM structure according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view of a DRAM structure according to some embodiments of the present invention. FIG. 3 is a schematic top view of a DRAM structure according to some embodiments of the present invention. In addition, FIG. 2 is a sectional view along the line I-I' in FIG. 3 . FIG. 4 is a schematic top view of a DRAM structure according to other embodiments of the present invention. In addition, in FIG. 1 , FIG. 3 and FIG. 4 , some components in FIG. 2 are omitted to clearly illustrate the positional relationship between the components in FIG. 1 , FIG. 3 and FIG. 4 .

Referring to FIG. 1 to FIG. 4 , the DRAM structure 100 includes at least one memory cell MC. In this embodiment, the DRAM structure 100 is illustrated by taking a plurality of memory cells MC (FIG. 3 and FIG. 4) as an example. The memory cell MC includes a substrate 102 , a gate structure 104 , a capacitor 106 , a bit line structure 108 , a capacitor 110 and a bit line structure 112 . The base 102 has a first surface S1 and a second surface S2 opposite to each other. The substrate 102 can be a semiconductor substrate, such as a silicon substrate.

In addition, the substrate 102 may include a channel area C1 and a channel area C2. Channel region C1 is located between capacitor 106 and bit line structure 108 . The channel region C2 is located between the capacitor 110 and the bit line structure 112 . In addition, the memory cell MC may further include an isolation structure 114 . The isolation structure 114 is located in the substrate 102 . The isolation structure 114 can define an active area AA ( FIGS. 3 and 4 ) in the substrate 102 . In some embodiments, the shape of the active area AA may be a parallelogram ( FIG. 3 ) or a rectangle ( FIG. 4 ), but the invention is not limited thereto. The channel region C1 can be located on one side of the gate structure 104 and can be located between the gate structure 104 and the isolation structure 114 . The channel region C2 can be located on the other side of the gate structure 104 and can be located between the gate structure 104 and the isolation structure 114 . The isolation structure 114 is, for example, a shallow trench isolation (STI). The material of the isolation structure 114 can be, for example, silicon oxide, silicon nitride or a combination thereof.

Referring to FIG. 1 and FIG. 2 , the gate structure 104 penetrates through the substrate 102 . The gate structure 104 can include a gate 116 and a dielectric layer 118 . The gate 116 is located in the substrate 102 . The gate 116 may be a vertical gate. For example, in the channel region C1 , current can flow along a direction D1 perpendicular to the surface of the substrate 102 (eg, the first surface S1 ). In addition, in the channel region C2 , current can flow along a direction D2 perpendicular to the surface of the substrate 102 (eg, the first surface S1 ). The material of the gate 116 is, for example, a conductive material such as metal (eg, tungsten). The dielectric layer 118 is located between the gate 116 and the substrate 102 . The dielectric layer 118 may serve as a gate dielectric layer. In some embodiments, a dielectric layer 118 may surround the gate 116 . The dielectric layer 118 can be a single-layer structure or a multi-layer structure. The material of the dielectric layer 118 is, for example, silicon oxide, silicon nitride or a combination thereof. In addition, the gate structure 104 may further include a barrier layer 120 . The barrier layer 120 is located between the gate 116 and the dielectric layer 118 . In some embodiments, the barrier layer 120 may surround the gate 116 , but the invention is not limited thereto. The material of the barrier layer 120 is, for example, titanium, titanium nitride or a combination thereof.

Referring to FIG. 3 and FIG. 4 , the top view shape of the gate electrode 116 can be a strip ( FIG. 3 ) or have branches ( FIG. 4 ). In the case that the top view of the gate 116 has branches ( FIG. 4 ), the branches of the gate 116 can surround part of the channel region C1 and part of the channel region C2 , thereby increasing the channel width.

Referring to FIGS. 1 to 4 , the capacitor 106 is located on the first surface S1 of the substrate 102 . The capacitor 106 can serve as a storage node of the memory cell MC. The capacitor 106 can be various capacitors suitable for DRAM (eg, cylinder capacitor). In some embodiments, the capacitor 106 may include an electrode 122, an electrode 124, and an insulating layer 126 (FIG. 2). The electrode 122 is located on the first surface S1 of the substrate 102 . The material of the electrode 122 is, for example, titanium, titanium nitride or a combination thereof. Electrode 124 is located on electrode 122 . The electrode 124 can be a single-layer structure or a multi-layer structure. In this embodiment, the electrode 124 can be a multi-layer structure including the electrode 124a and the electrode 124b, but the invention is not limited thereto. Electrode 124a is located on electrode 122 . The material of the electrode 124a is, for example, titanium, titanium nitride or a combination thereof. Electrode 124b is located on electrode 124a. The material of the electrode 124 b is, for example, a doped semiconductor material, such as boron-doped silicon germanium (SiGe) or doped polysilicon. The insulating layer 126 is located between the electrode 122 and the electrode 124 . The material of the insulating layer 126 can be a dielectric material, such as a high-k material.

Please refer to FIG. 1 to FIG. 4 , the memory cell MC may further include a contact window 128 . The contact 128 can be used as a storage node contact. The contact window 128 is located between the capacitor 106 and the substrate 102 . The material of the contact window 128 is, for example, conductive material such as doped polysilicon.

Referring to FIG. 1 and FIG. 2 , the bit line structure 108 is located on the second surface S2 of the substrate 102 . The bitline structure 108 can include a bitline 130 and a contact 132 . The bit line 130 and the contact window 132 may be integrally formed or separate components. The bit line 130 is located on the second surface S2 of the substrate 102 . The material of the bit line 130 is, for example, a conductive material such as metal (eg, tungsten). The contact window 132 is located between the bit line 130 and the substrate 102 . The material of the contact window 132 is, for example, conductive material such as doped polysilicon or metal (eg, tungsten).

Referring to FIG. 1 and FIG. 2 , the capacitor 110 is located on the second surface S2 of the substrate 102 . The capacitor 110 can serve as a storage node of the memory cell MC. The capacitor 110 can be various capacitors (eg, pillar capacitors) suitable for DRAM. In some embodiments, the capacitor 110 may include an electrode 134, an electrode 136, and an insulating layer 138 (FIG. 2). The electrode 134 is located on the second surface S2 of the substrate 102 . The material of the electrode 134 is, for example, titanium, titanium nitride or a combination thereof. Electrode 136 is located on electrode 134 . The electrode 136 may have a single-layer structure or a multi-layer structure. In this embodiment, the electrode 136 can be a multi-layer structure including the electrode 136a and the electrode 136b, but the invention is not limited thereto. Electrode 136 a is located on electrode 134 . The material of the electrode 136a is, for example, titanium, titanium nitride or a combination thereof. Electrode 136b is located on electrode 136a. The material of the electrode 136 b is, for example, a doped semiconductor material, such as boron-doped silicon germanium or doped polysilicon. The insulating layer 138 is located between the electrode 134 and the electrode 136 . The material of the insulating layer 138 can be a dielectric material, such as a high dielectric constant material.

Please refer to FIG. 1 and FIG. 2 , the memory cell MC may further include a contact window 140 . The contact 140 can be used as a storage node contact. The contact window 140 is located between the capacitor 110 and the substrate 102 . The material of the contact window 140 is, for example, conductive material such as doped polysilicon.

Referring to FIG. 1 to FIG. 4 , the bit line structure 112 is located on the first surface S1 of the substrate 102 . The bit line structure 112 may include a bit line 142 and a contact 144 . The bit line 142 and the contact window 144 may be integrally formed or separate components. The bit line 142 is located on the first surface S1 of the substrate 102 . The material of the bit line 142 is, for example, a conductive material such as metal (eg, tungsten). The contact 144 is located between the bit line 142 and the substrate 102 . The material of the contact window 144 is, for example, conductive material such as doped polysilicon or metal (eg, tungsten).

As shown in FIG. 2 , capacitor 106 and bit line structure 108 may be located on one side of gate structure 104 , and capacitor 110 and bit line structure 112 may be located on the other side of gate structure 104 . In addition, the contact 128 and the contact 132 can be located on the same side of the gate structure 104 , and the contact 140 and the contact 144 can be located on the same side of the gate structure 104 . In addition, the contact window 128 and the contact window 140 may be located on different sides of the gate structure 104 , and the contact window 132 and the contact window 144 may be located on different sides of the gate structure 104 .

Referring to FIG. 3 and FIG. 4 , the top view shape of the bit line 142 can be straight ( FIG. 3 ) or meandering ( FIG. 4 ). In addition, in FIG. 3 and FIG. 4 , although the bit line 130 is not shown, the top view shape of the bit line 130 can refer to the top view shape of the bit line 142 in FIG. 3 and FIG. 4 . That is, the top view shape of the bit line 130 can be straight or zigzag.

Please refer to FIG. 2 , the memory cell MC may further include at least one of the dielectric layer 146 , the dielectric layer 148 , the dielectric layer 150 and the dielectric layer 152 . The dielectric layer 146 is located between the contact 128 and the bit line 142 . Dielectric layer 148 is located between capacitor 106 and bit line 142 and between capacitor 106 and dielectric layer 146 . The dielectric layer 150 is located between the contact window 140 and the bit line 130 . The dielectric layer 152 is located between the capacitor 110 and the bit line 130 and between the capacitor 110 and the dielectric layer 150 . The material of the dielectric layer 146 , the dielectric layer 148 , the dielectric layer 150 and the dielectric layer 152 is, for example, silicon nitride.

In addition, the DRAM structure 100 may further include other required dielectric layers (for isolation) and/or other required interconnection structures (for electrical connection), which are omitted here. illustrate.

In this embodiment, please refer to FIG. 3, if one-half of the minimum distance between components is set as F, the length ML of the memory cell MC is about 4F, and the width MW of the memory cell MC is about 2F, and The area of the memory cell MC is about 8F ² (=4F×2F). However, since the memory cell MC can have two bits (bit B1 and bit B2) (Fig. 1 and Fig. 2), the average bit size (bit size) of the memory cell MC is about 4F ² (=8F ² /2). In this way, the memory cell MC can have a smaller bit size, thereby increasing the bit density of the memory device. In addition, since the area of the memory cell MC is approximately 8F ² , the available areas of the capacitor 106 and the capacitor 110 on different surfaces of the substrate 102 are approximately 8F ² . That is, the capacitor 106 and the capacitor 110 may have larger areas. Thereby, the capacitance of the capacitor 106 and the capacitance of the capacitor 110 can be increased.

Based on the above embodiments, it can be seen that in the DRAM structure 100, the gate structure 104 penetrates the substrate 102, the capacitor 106 is located on the first surface S1 of the substrate 102, and the bit line structure 108 is located on the second surface S2 of the substrate 102. Above, the capacitor 110 is located on the second surface S2 of the substrate 102 , and the bit line structure 112 is located on the first surface S1 of the substrate 102 . Therefore, a single memory cell MC can have two bits, thereby increasing the bit density of the memory device. In addition, since the capacitor 106 and the capacitor 110 are located on different surfaces of the substrate 102 , it is beneficial to increase the area of the capacitor 106 and the area of the capacitor 110 . Thereby, the capacitance of the capacitor 106 and the capacitance of the capacitor 110 can be increased, thereby improving the electrical performance of the memory device. In addition, since the two bits (bit B1 and bit B2) in the memory cell MC share the gate structure 104 (that is, a single gate structure 104 can control two bits), the memory cells can be controlled simultaneously. Two bits in the MC are operated (for example, a read operation), thereby increasing the operation speed of the memory device.

To sum up, in the DRAM structure of the above embodiment, since the two bits in the memory cell share the gate structure, and the two capacitors in the memory cell are located on different surfaces of the substrate, it is possible to Effectively improve the bit density, electrical performance and operating speed of memory devices.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: Dynamic Random Access Memory Structure 102: Base 104:Gate structure 106,110: Capacitor 108,112: bit line structure 114: Isolation structure 116: Gate 118,126,146,148,150,152: dielectric layer 120: barrier layer 122, 124, 124a, 124b, 134, 136, 136a, 136b: electrodes 126,138: insulating layer 128,132,140,144: contact window 130,142: bit line B1, B2: bits C1, C2: channel area D1, D2: direction MC: memory cell ML: Length MW: Width S1: the first side S2: Second side

FIG. 1 is a three-dimensional schematic diagram of a DRAM structure according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view of a DRAM structure according to some embodiments of the present invention. FIG. 3 is a schematic top view of a DRAM structure according to some embodiments of the present invention. FIG. 4 is a schematic top view of a DRAM structure according to other embodiments of the present invention.

100: Dynamic Random Access Memory Structure

102: Base

104:Gate structure

106,110: Capacitor

108,112: bit line structure

116: Gate

118: dielectric layer

120: barrier layer

128,132,140,144: contact window

130,142: bit line

B1, B2: bits

C1, C2: channel area

D1, D2: direction

MC: memory cell

S1: the first side

S2: Second side

Claims (10)

A dynamic random access memory structure comprising at least one memory cell, wherein the memory cell comprises: a base having opposing first and second sides; a gate structure penetrating through the substrate; a first capacitor on the first side of the substrate; a first bitline structure located on the second side of the substrate; a second capacitor on the second side of the substrate; and The second bit line structure is located on the first surface of the substrate. The dynamic random access memory structure as claimed in item 1, wherein the base comprises: a first channel region between the first capacitor and the first bitline structure; and The second channel area is located between the second capacitor and the second bit line structure. The dynamic random access memory structure as described in claim item 2, wherein the memory cells further include: isolation structure, located in the substrate, wherein The first channel region is located on one side of the gate structure and between the gate structure and the isolation structure, and The second channel region is located on the other side of the gate structure and between the gate structure and the isolation structure. The dynamic random access memory structure as claimed in item 1, wherein the gate structure comprises: a gate in the substrate; and The dielectric layer is located between the gate and the substrate. The dynamic random access memory structure as claimed in item 4, wherein the top-view shape of the gate electrode includes strips or branches. The DRAM structure according to claim 4, wherein the dielectric layer surrounds the gate. The dynamic random access memory structure as described in claim 1, wherein the first capacitor and the first bit line structure are located on one side of the gate structure, and The second capacitor and the second bit line structure are located on the other side of the gate structure. The dynamic random access memory structure as described in claim 1, wherein The first bit line structure includes: a first bitline on the second side of the substrate; and a first contact located between the first bit line and the substrate, and The second bit line structure includes: a second bitline on the first side of the substrate; and The second contact window is located between the second bit line and the substrate. The DRAM structure according to claim 8, wherein the top-view shape of the first bit line and the top-view shape of the second bit line include a straight line or a zigzag shape. The dynamic random access memory structure as described in claim item 1, wherein the memory cell further includes: a first contact located between the first capacitor and the substrate; and The second contact window is located between the second capacitor and the substrate.

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