TWI789860B - Latch-up prevention circuitry, selection circuitries and method for preventing latch-up - Google Patents

Abstract

Various embodiments of selection circuitries and a method for preventing latch-up of a memory storage system are disclosed. The selection circuitry selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the selection circuitry selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the selection circuitry selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the selection circuitry selectively provide the maximum operational voltage signal to bulk （B） terminals of some of their transistors to prevent latch-up of these transistors. In some situations, the selection circuitry can dynamically adjust the maximum operational voltage signal to compensate for fluctuations in the maximum operational voltage signal.

Description

Latch-up prevention circuit, selection circuit and method for preventing latch-up

The present disclosure relates to a selection circuit and a method for preventing latch-up of a memory storage system.

Memory storage systems are electronic devices used to read and/or write electronic data. Memory storage systems include arrays of memory cells that may be implemented as volatile memory cells that require power to maintain their stored information, such as random-access memory (RAM) cells, Or a non-volatile memory unit, such as a read-only memory (ROM) unit, that maintains its stored information even without power. Electronic data can be read from and/or written into the memory cell array, which can be accessed through various control lines. The two basic operations performed by a memory device are " reading " and " writing ". In reading, the electronic data stored in the memory cell array is read out. In writing, the electronic data is written into in the memory cell array.

The selection circuit of the present disclosure is used for selectively providing the operable voltage signal to the selection circuit of the memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has a plurality of transistors. The switch circuit is configured to select an operable voltage signal from among a plurality of operable voltage signals, a maximum operable voltage signal among the plurality of operable voltage signals is selectively applied to the base terminals of the plurality of transistors. The latch-up prevention circuit is configured to dynamically adjust the maximum operable voltage signal to compensate fluctuations of the maximum operable voltage signal.

Another selection circuit of the present disclosure is used in a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has a plurality of transistors. The switch circuit is configured to provide an operable voltage signal selected from a plurality of operable voltage signals to the memory storage system. The latch-up prevention circuit has a first diode-connected transistor and a second diode-connected transistor. The latch-up prevention circuit is configured to apply a maximum operable voltage signal selected from the plurality of operable voltage signals to the first base terminal of the first diode-junction transistor and to the first base terminal of the second diode-junction transistor. second base terminal. The first diode-connected transistor is configured to obtain a first current from the first operable voltage signal to adjust the maximum operable voltage signal to compensate fluctuations of the maximum operable voltage signal during start-up. The second diode-connected transistor is configured to obtain a second current from the second operable voltage signal to adjust the maximum operable voltage signal to compensate fluctuations of the maximum operable voltage signal during startup.

The disclosed method for preventing latch-up of a memory storage system includes: applying a maximum operable voltage signal selected from a plurality of operable voltage signals to at least one transistor of the memory storage system by the memory storage system and at least one gate region applied to at least one transistor; and when the maximum operable voltage signal fluctuates below a first operable voltage signal among the plurality of operable voltage signals, by The memory storage system increases the maximum operable voltage signal.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include that additional features may be formed over the first feature and the second feature. An embodiment in which features are formed between such that a first feature may not be in direct contact with a second feature. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition does not in itself indicate a relationship between the various embodiments and arrangements described.

overview

Various embodiments of a memory storage system are disclosed herein. The memory storage can be configured to selectively select an operable voltage signal from a plurality of operable voltage signals to dynamically control various operating parameters. For example, a memory storage system can be configured to selectively select a maximum operable voltage signal from a plurality of operable voltage signals to maximize read/write speed. As another example, a memory storage system may be configured to selectively select a minimum operable voltage signal from a plurality of operable voltage signals to minimize power consumption. In addition, the memory storage system may be configured to selectively provide a maximum operable voltage signal to the bulk (B) terminals of some of its transistors to prevent latch-up of these transistors. In some cases, the memory storage system can be configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

Exemplary memory storage system

FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 1, memory storage system 100 selectively selects between a plurality of operable voltage signals to dynamically control operation. For example, memory storage system 100 may select an operable voltage signal from a plurality of operable voltage signals to configure memory storage system 100 to dynamically control (eg, minimize or maximize) multiple voltage signals from memory storage system 100. One or more of the operating parameters, such as power consumption and/or read/write speed. As shown in FIG. 1 , the memory storage system 100 includes a voltage generator circuit 102 , selection circuits 104.1˜104.x and a memory device 106 .

The voltage generator circuit 102 selectively provides the maximum operable voltage signal V _DDMAX to the selection circuits 104.1˜104.x from the operable voltage signal V ₁ to the operable voltage signal V _m according to the bias control signal 150 . For example, the maximum operable voltage signal V _DDMAX may represent the maximum operable voltage signal among the operable voltage signals V ₁ -V _m . In some cases, the maximum operable voltage signal among the operable voltage signals V ₁ -V _m is known empirically. In an exemplary embodiment, the voltage generator circuit 102 includes a plurality of switches to selectively provide the maximum operable voltage signal from among the operable voltage signals V ₁ -V _m as the maximum operable voltage signal V _DDMAX . In this exemplary embodiment, the bias control signal 150 includes one or more control bits, wherein various combinations of the one or more control bits correspond to various operable voltages among the operable voltage signals V ₁ -V _m Signal. In this exemplary embodiment, the bias control signal 150 can be set to a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V ₁ ˜V _m , so as to set the voltage generator circuit 102 from the operable Among the operating voltage signals V ₁ -V _m , the maximum operable voltage signal is selectively provided to the selection circuits 104.1 - 104. x as the maximum operable voltage signal V _DDMAX . In this exemplary embodiment, the combination of control bits activates (ie, closes) one or more of the plurality of switches to provide the maximum operable voltage signal from among the operable voltage signals V ₁ -V _m As the maximum operable voltage signal V _DDMAX , the remaining switches among the plurality of switches are simultaneously blocked (ie, opened).

In the exemplary embodiment shown in FIG. 1, the selection circuits 104.1~ 104.x selectively provide one of the operable voltage signals _V1 ~ _Vm as the operable voltage signal in response to the selection control signal 152 V _{DDM_INT.1˜V DDM_INT.x} to control one or more operating parameters of the memory device 106 . The selection control signal 152 can be set to various combinations of one or more control bits to selectively provide one of the operable voltage signals V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.x} , To dynamically control multiple operating parameters of the memory device 106 . For example, one or more control bits can be set as a first bit combination to select the minimum operable voltage signal from the operable voltage signals V ₁ ~V _m to dynamically control (eg, minimize) the memory Power consumption of device 106 . In this example, the minimum operational voltage signal causes less unwanted leakage in various transistors of the memory device 106 when compared to other operational voltage signals V ₁ -V _m . As another example, one or more control bits may be set to a second bit combination to select the maximum operable voltage signal from among the operable voltage signals V ₁ -V _m to dynamically control (eg, maximize) the memory The read/write speed of the bulk device 106. In some cases, selection control signal 152 may be toggled during operation of memory storage system 100 to dynamically set memory device 106 during operation to control one or more operating parameters. In this other example, when compared with other operable voltage signals among the operable voltage signals V ₁ -V _m , the maximum operable voltage signal can cause various transistors of the memory cells of the memory device 106 to operate more quickly. rate off and/or on. As another example, the selection control signal 152 can be set to a second bit combination to maximize the read/write speed of the memory device 106 and dynamically reset to a different bit combination during operation to reduce memory The read/write speed of the bulk device 106.

In an exemplary embodiment, the selection circuits 104.1~ 104.x include a plurality of switches to selectively provide one of the operable voltage signals V ₁ ~V _m as the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.x} . In this exemplary embodiment, the selection control signal 152 includes one or more control bits, wherein various combinations of the one or more control bits correspond to various operable voltage signals among the operable voltage signals V ₁ -V _m . In this exemplary embodiment, the selection control signal 152 can be set to a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V ₁ ~V _m to set the selection circuits 104.1 ~ 104.x , Selectively provide the maximum operable voltage signal from the operable voltage signals V ₁ ~V _m as the operable voltage signal V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.x} to the memory device 106. In this exemplary embodiment, the combination of control bits activates (ie, closes) one or more switches among the plurality of switches to provide the maximum operable voltage signal among the operable voltage signals V ₁ -V _m and is the maximum operable voltage signal V _DDMAX , simultaneously blocking (ie, opening) the remaining switches of the plurality of switches. In this exemplary embodiment, multiple switches may be implemented using transistors such as p-type metal-oxide-semiconductor (PMOS) transistors having The source terminal, drain terminal, gate terminal and base (B) terminal in the well area. As will be described in further detail below, the selection circuits 104.1-104.x provide the maximum operable voltage signal V _DDMAX from the voltage generator circuit 102 to the base (B) terminals of the transistors such that the source terminals formed at these transistors The parasitic diode between the (source; S) terminal and the well region is reverse biased, that is, non-conductive, to prevent latch-up of these transistors. In some cases, the maximum operable voltage signal V _DDMAX may fluctuate, for example, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. In these cases, the selection circuits 104.1˜104. x can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations in the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below.

The memory device 106 receives operable voltage signals V _{DDM_INT.1} -V _{DDM_INT.x} selectively selected from the operable voltage signals V ₁ -V _m . In the exemplary embodiment shown in FIG. 1, memory device 106 includes memory cells arranged in an array of m rows and n columns. In this exemplary embodiment, memory device 106 provides each of operable voltage signals V _{DDM_INT.1} -V _{DDM_INT.x} to m rows of the memory array as discussed in further detail below in FIG. 2A Corresponding rows therein and/or are provided to corresponding columns among n columns of the memory cell array as discussed in further detail below in FIG. 2B .

Exemplary Memory Devices That Can Be Implemented Within Exemplary Memory Storage Systems

FIG. 2A shows a block diagram of a first exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 2A, selection circuits 200.1-200. m selectively provide operable The voltage signals V _{DDM_INT.1˜V DDM_INT.m} are used to set the operation of the memory device 202 . Memory device 202 may represent an exemplary embodiment of memory device 106 as described above in FIG. 1 . In an exemplary embodiment, the selection circuits 200.1~200. m selectively provide the first operable voltage signal as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT. m} from a plurality of operable voltage signals to set the memory The memory device 202 dynamically controls (eg, minimizes) one or more operating parameters of the memory device 202 , such as power consumption and/or read/write speed. As another example, the selection circuits 200.1˜200. m selectively provide a second operable voltage signal from a plurality of operable voltage signals to configure the memory device 202 to dynamically control (for example, maximize) the memory device 202 One or more operational parameters for .

In the exemplary embodiment shown in FIG. 2A , the memory device 202 includes a memory array 204 . Although not shown in FIG. 2A , memory device 202 may include other electronic circuitry, such as sense amplifiers, column address decoders, and/or row address decoders, to provide some examples, without departing from the spirit of the present disclosure. The circumstances and scope will be apparent to those having ordinary knowledge in the relevant technical field. As shown in FIG. 2A , memory array 204 includes memory cells 210.1.1˜10. m . n arranged and arranged into an array of m rows and n columns. However, other configurations of the memory units 210.1.1˜210. m . n may not deviate from the spirit and scope of the present disclosure. In the exemplary embodiment shown in FIG. 2A, the memory cells 210.1.1~ 210.m.n are connected to corresponding wordlines (wordline; WL) and bits among the wordlines 212.1~ 212.n . Corresponding bitlines (bitlines; BL) among lines 214.1~bitlines 214.m. Word line 212.1~word line 212.n and/or bit line 214.1~bit line 214.m can be used to read the electronic data stored in the memory array 204 in the " read " mode of operation and/or in the " write " mode. Enter " operation mode to write electronic data into the memory array 204 . The " read " mode of operation and the " write " mode of operation represent conventional read and write operations and will not be described in further detail.

As shown in FIG. 2A, the selection circuits 200.1~ 200.m selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.m} to m of the memory units 210.1.1~ 210.m.n One or more corresponding rows for the row. For example, the selection circuit 200.1 selectively provides the operable voltage signal V _{DDM_INT.1} to the first row of the memory cells 210.1.1˜210.1.n, and the selection circuit 200.m provides the operable voltage signal V _{DDM_INT. m} is selectively provided to the m -th row of memory cells 210.m .1~ 210.m .n Although not shown in FIG. The corresponding operable voltage signals among V _{DDM_INT.1˜V DDM_INT.m} are selectively provided to more than one row among the m rows of memory cells 210.1.1˜210.m.n . In an exemplary embodiment, memory cells 210.m .1~ 210.m .n may be implemented using one or more transistors, such as one or more p-type metal oxide semiconductor (PMOS) transistors crystal, one or more n-type metal-oxide-semiconductor (n-type metal-oxide-semiconductor; NMOS) transistors, or any combination of PMOS transistors and NMOS transistors, without departing from the spirit and scope of this disclosure It will be apparent to those having ordinary knowledge in the relevant technical field. In this exemplary embodiment, the selection circuits 200.1~ 200.m can selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.m} to m pieces of the memory cells 210.1.1~ 210.m .n The one in the row corresponds to the base (B) terminal of the transistor in the row. The operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT. m} effectively makes the parasitic diode formed between the source (S) terminal and the well region of these transistors in this example reverse bias (that is, not conductive) to prevent latch-up, as discussed in further detail below in Figure 3.

2B shows a block diagram of a second exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 2B, selection circuits 220.1-220. n selectively provide operable The voltage signals V _{DDM_INT.1˜V DDM_INT.n} are used to set the operation of the memory device 222 . Memory device 222 may represent an exemplary embodiment of memory device 106 as described above in FIG. 1 . In an exemplary embodiment, the selection circuits 220.1~ 220.n selectively provide the first operable voltage signal as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.n} from a plurality of operable voltage signals to set the memory The memory device 222 dynamically controls (eg, minimizes) one or more of a plurality of operating parameters of the memory device 222 , such as power consumption and/or read/write speed. As another example, the selection circuits 220.1~ 220.n selectively provide a second operable voltage signal from a plurality of operable voltage signals to configure the memory device 222 to dynamically control (eg, maximize) the memory device 222 One or more operational parameters for .

In the exemplary embodiment shown in FIG. 2B , memory device 222 includes memory array 224 . Although not shown in FIG. 2B , memory device 222 may include other electronic circuitry, such as sense amplifiers, column address decoders, and/or row address decoders, to provide some examples, without departing from the spirit and scope of the present disclosure. where it will be apparent to those having ordinary knowledge in the relevant technical field. As shown in FIG. 2B , memory array 224 includes memory cells 226.1.1˜226. m . n arranged and arranged into an array of m rows and n columns. However, other configurations of the memory units 226.1.1˜226. m . n may not deviate from the spirit and scope of the present disclosure. In the exemplary embodiment shown in FIG. 2B, memory cells 226.1.1~ 226.m.n are connected to corresponding word lines (WL) and bit lines 214.1 among word lines 212.1~212.n. ~ Corresponding bit line (BL) among bit lines 214.m.

As shown in FIG. 2B, the selection circuits 220.1~220. m selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} to n columns among the memory cells 226.1.1~226. m .n One or more corresponding columns of . For example, the selection circuit 220.1 selectively provides the operable voltage signal V _{DDM_INT.1} to the first row of memory cells 226.1.1~226.m.1, and the selection circuit 220.n provides the operable voltage signal V _{DDM_INT . n} is selectively provided to the memory cells 226.1. n ~ 226. m . n of the nth column. Although not shown in FIG. 2B, each of the selection circuits 220.1~ 220.m can selectively provide its corresponding operable voltage signal among the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} to the memory Among the n columns of units 226.1.1~226. m . n , more than one column. In an exemplary embodiment, memory cells 226.m .1~ 226.m .n may be implemented using one or more transistors, such as one or more p-type metal oxide semiconductor (PMOS) transistors crystal, one or more n-type metal-oxide-semiconductor (NMOS) transistors, or any combination of PMOS transistors and NMOS transistors, without departing from the spirit and scope of this disclosure, it will be useful to the relevant technical field Usually the knower is obvious. In this exemplary embodiment, the selection circuits 220.1~ 220.n can selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} to m pieces of the memory cells 226.1.1~ 226.m .n The one in the row corresponds to the base (B) terminal of the transistor in the row. The operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} are effective such that, providing examples, the parasitic diodes formed between the source (S) terminals and the wells of these transistors are reverse biased (ie, not conduction) to prevent latch-up of these transistors, as discussed in further detail in Figure 3 below.

Exemplary Memory Units That Can Be Implemented in Exemplary Memory Devices

As described above in FIGS. 1 , 2A, and 2B, exemplary memory devices depicted therein, such as memory device 106 as described above in FIG. 1 , as described above in FIG. Memory device 202 and/or memory device 222 as described above in FIG. 2B , includes an array of memory cells such as memory cell 210.1.1 as described above in FIG. 2A to provide some examples ~210. m . n and/or memory cells 226.1.1~226. m . n as described above in FIG. 2B . The following discussion of FIG. 3 describes various embodiments of these memory cells. However, those of ordinary skill in the relevant art will recognize that without departing from the spirit and scope of the present disclosure, the teachings of the various embodiments of these memory cells, which will be described below, can be easily modified for any suitable volatile memory cells, such as any random access memory (RAM) cells, and/or any suitable non-volatile memory cells, such as any read only memory (ROM) cells. The RAM cells may be implemented as dynamic random-access memory (DRAM) cells, static random-access memory (SRAM) cells, and/or non-volatile random-access memory (non-volatile random-access memory) cells. memory; NVRAM) cells such as flash memory cells that provide instances. The ROM cells may be implemented as programmable read-only memory (programmable read-only memory; PROM) cells, one-time programmable ROM (OTP) cells, erasable programmable A read-only memory (erasable programmable read-only memory; EPROM) unit and/or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory; EEPROM) unit.

FIG. 3 shows a block diagram of an example static random access memory (SRAM) cell that may be implemented within an example memory device according to example embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 3, SRAM cell 300 may be used to implement one or more memory cells of memory device 106 as described above in FIG. One or more of the memory units 210.1.1~ 210.m.n of the body device 202 and/or the memory units 226.1.1 ~ 226.m.n of the memory device 222 as described above in FIG. 2B one or more of the . As shown in FIG. 3 , the SRAM cell 300 includes p-type metal-oxide-semiconductor (PMOS) transistors P1 and p-type metal-oxide-semiconductor transistors P2 and n-type metal-oxide-semiconductor (NMOS) transistors N1 - N4 .

In the exemplary embodiment shown in FIG. 3, the PMOS transistor P1 and the NMOS transistor N1 are configured to form the gate of the first logic inverter (INVERTER), and the PMOS transistor P2 and the NMOS transistor N2 are configured to configured to form a second logic inverter gate. The first logic inverter gate is cross-coupled with the second logic inverter gate as shown in FIG. 3 . For example, the input of the first logic inverter gate is coupled to the output of the second logic inverter gate, and the output of the first logic inverter gate is coupled to the second logic inverter gate input of. In this cross-coupled arrangement, the first logic inverter and the second logic inverter functionally cooperate to enhance the information stored in the SRAM cell 300 .

In the exemplary embodiment shown in FIG. 3, the information stored in the first logic inverter gate and the second logic inverter gate is between logical zero and logical one. cyclically convert between, such as the operable voltage signal V _{DDM_INT .} In an exemplary embodiment, the operable voltage signal V _{DDM_INT} represents one of the operable voltage signals V _{DDM_INT.1˜V DDM_INT.x} as described above in FIG. An exemplary embodiment of one of the voltage signals V _{DDM_INT.1˜V DDM_INT.m} and/or one of the operable voltage signals V _{DDM_INT.1˜V DDM_INT.n} as described in FIG. 2B above. In another exemplary embodiment, the first logic inverter and the second logic inverter receive the operable voltage signal V _{DDM — INT} from a selection circuit such as described above in FIG. 1 to provide some examples One of the selection circuits 104.1-104.x , one of the selection circuits 200.1-200.m as described above in FIG. 2A and/or in the selection circuits 220.1-220.n as described above in FIG. 2B one of.

During a " read " operation, NMOS transistor N3 and NMOS transistor N4 are enabled by asserting word line (WL) 350 . This activation of NMOS transistor N3 and NMOS transistor N4 couples the first logic inverter and the second logic inverter to bit line (BL) 352 . In an exemplary embodiment, word line 350 may represent one of word lines 212.1 through 212. n as described above in FIGS. 2A and 2B , and bit line 352 may represent one of word lines 212. One of the bit lines 214.1~214. m described in 2B. Thereafter, the data stored in the first logic inverter and the second logic inverter are transferred to the bit line (BL) 352 . Similarly, during a " write " operation, NMOS transistor N3 and NMOS transistor N4 are enabled by asserting word line 350 to couple the first logic inverter and the second logic inverter to the bit line 352. Thereafter, the state of the bit line 352 is transmitted to the first logic inverter and the second logic inverter to be stored as information in the first logic inverter and the second logic inverter.

In addition, as shown in FIG. 3 , the operational voltage signal V _{DDM_INT} is coupled to the first base (B) terminal of the PMOS transistor P1 and the second base (B) terminal of the PMOS transistor P2 . In the exemplary embodiment shown in FIG. 3, the PMOS transistor P1 is located in the first n-type well region in the p-type semiconductor substrate, and the PMOS transistor P2 is located in the second n-type well region in the p-type semiconductor substrate. area. In this exemplary embodiment, the operable voltage signal V _{DDM_INT} transfers charges from the base (B) terminal of the PMOS transistor P1 and the base (B) terminal of the PMOS transistor P2 to the first n-type well region and the first n-type well, respectively. the second n-type well region.

Exemplary selection circuitry within an exemplary memory storage system

As described above in FIG. 1, the selection circuits 104.1~ 104.x selectively provide one of the operable voltage signals V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.x} to control the memory One or more operating parameters of the body device 106. The following discussion of FIG. 4 describes an exemplary embodiment of selecting one of circuits 104.1-104.x .

FIG. 4 shows a block diagram of an exemplary selection circuit that may be implemented in an exemplary memory device according to exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 4, the selection circuit 400 selectively provides the operable voltage signal V _{DDM_INT} from the operable voltage signal V _DD and the operable voltage signal V _DDM to control one of the memory devices. or a plurality of operating parameters, such as memory device 106 to provide an example. In an exemplary embodiment, the operable voltage signal V _DDM and the operable voltage signal V _DD may represent exemplary embodiments of two of the operable voltage signals V ₁ -V _m as described above in FIG. 1 . In another exemplary embodiment, the operable voltage signal V _DD corresponds to an operable voltage signal distributed to other digital circuits communicatively coupled to the memory device, and the operable voltage signal V _DDM corresponds to an operable voltage signal distributed to the memory device. The operational voltage signal of the body device. In some cases, operable voltage signal V _DD is greater than operable voltage signal V _DDM ; however, in other cases, operable voltage signal V _DD may be less than operable voltage signal V _DDM . In the exemplary embodiment shown in FIG. 4 , the selection circuit 400 selects the greater of the operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} , so that the memory device 106 The read/write speed of the corresponding row of memory cells as described above in FIG. 2A and/or the corresponding column of memory cells as described above in FIG. 2B is maximized. Otherwise, the selection circuit 400 selects the smaller of the operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} , so as to memory the corresponding row of memory cells and/or the corresponding column of the memory device 106 The power consumption of the body unit is minimized.

Furthermore, as will be discussed in further detail below, the selection circuit 400 includes a plurality of switches to selectively provide the operable voltage signal V _DD or the operable voltage signal V _DDM as the operable voltage signal V _{DDM — INT} . And as will be discussed in further detail below, the selection circuit 400 provides the maximum operable voltage signal V _DDMAX to the base (B) terminals of the transistors of the plurality of switches such that the source (S) terminals of these transistors are connected to the wells The parasitic diodes between the regions are reverse biased (that is, non-conductive) to prevent latch-up of these transistors. In some cases, the maximum operable voltage signal V _DDMAX may fluctuate, for example, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. In these cases, the selection circuit 400 can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations in the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below. In the exemplary embodiment shown in FIG. 4 , the selection circuit 400 includes a switch circuit 402 and a latch-up prevention circuit 404 .

在處於第一邏輯準位（諸如提供實例的邏輯0）時啟動（亦即，閉合）PMOS電晶體P4及PMOS電晶體P5中的第一電晶體，及/或在處於第二邏輯準位（諸如提供實例的邏輯1）時阻斷（亦即開路）PMOS電晶體P4及PMOS電晶體P5中的第二電晶體。在此例示性實施例中,偏壓控制信號452及偏壓控制信號

表示差分偏壓控制信號，其中偏壓控制信號452為偏壓控制信號

的補充。在此例示性實施例中，PMOS電晶體P4及PMOS電晶體P5在啟動時選擇性地提供其對應可操作電壓信號V_DDM 及可操作電壓信號V_DD 作為可操作電壓信號V_{DDM_INT} 。並且，在此例示性實施例中，在阻斷時選擇性地禁止PMOS電晶體P4及PMOS電晶體P5提供其對應可操作電壓信號V_DDM 及可操作電壓信號V_DD 。此外，如圖4中所示出的PMOS電晶體P4及PMOS電晶體P5可實施為具有源極（S）端、汲極（drain；D）端、閘極（gate；G）端以及基極（B）端。如圖4中所示出，源極（S）端、汲極（D）端、基極（B）端形成於半導體基底的井區內。在圖4中所示出的例示性實施例中，開關電路402可將最大可操作電壓信號V_DDMAX 提供至PMOS電晶體P4及PMOS電晶體P5的基極（B）端，以使得形成於PMOS電晶體P4及PMOS電晶體P5的源極（S）端與n型井區之間的寄生二極體反向偏置（亦即，非導電），以防止閂鎖PMOS電晶體P4及PMOS電晶體P5。In the exemplary embodiment shown in FIG. 4, the switch circuit 402 selectively provides the operable voltage signal V _{DDM_INT} from the operable voltage signal V _DD and the operable voltage signal V _DDM to control one of the memory devices. or multiple operational parameters. As shown in FIG. 4 , the switch circuit 402 includes a p-type metal oxide semiconductor (PMOS) transistor P4 and a p-type metal oxide semiconductor transistor P5 . As shown in FIG. 4 , the PMOS transistor P4 and the PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM — INT} . In an exemplary embodiment, the bias control signal 452 and the bias control signal

A first of PMOS transistor P4 and PMOS transistor P5 is enabled (i.e., closed) when at a first logic level, such as logic 0 to provide an example, and/or at a second logic level ( A logic 1, such as to provide an example, blocks (ie, opens) the second of PMOS transistor P4 and PMOS transistor P5 . In this exemplary embodiment, bias control signal 452 and bias control signal

Represents a differential bias control signal, wherein the bias control signal 452 is a bias control signal

supplement. In this exemplary embodiment, the PMOS transistor P4 and the PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM — INT} during startup. Moreover, in this exemplary embodiment, the PMOS transistor P4 and the PMOS transistor P5 are selectively disabled from providing their corresponding operable voltage signal V _DDM and operable voltage signal V _DD when they are blocked. In addition, the PMOS transistor P4 and the PMOS transistor P5 shown in FIG. 4 may be implemented to have a source (S) terminal, a drain (drain; D) terminal, a gate (gate; G) terminal, and a base (B) end. As shown in FIG. 4 , the source (S) terminal, the drain (D) terminal, and the base (B) terminal are formed in the well region of the semiconductor substrate. In the exemplary embodiment shown in FIG. 4, the switch circuit 402 can provide the maximum operable voltage signal V _DDMAX to the base (B) terminals of the PMOS transistor P4 and the PMOS transistor P5, so that the PMOS The parasitic diodes between the source (S) terminals of transistor P4 and PMOS transistor P5 and the n-well region are reverse biased (i.e., non-conductive) to prevent latching of PMOS transistor P4 and PMOS transistor P5. Crystal P5.

In the exemplary embodiment shown in FIG. 4 , the latch-up prevention circuit 404 can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for fluctuations in the maximum operable voltage signal V _DDMAX . These fluctuations may be caused by unwanted electromagnetic coupling and/or leakage between various regions of the various transistors. As shown in FIG. 4 , the latch-up prevention circuit 404 includes a p-type metal-oxide-semiconductor (PMOS) transistor P6 and a p-type metal-oxide-semiconductor transistor P7 . In the exemplary embodiment shown in FIG. 4, PMOS transistor P6 and PMOS transistor P7 represent diode-connected transistors having their corresponding source (S) terminals coupled to their corresponding gate (G )end. During operation, the maximum operable voltage signal V _DDMAX is generally greater than or equal to the operable voltage signal V _DDM and the operable voltage signal V _DD . However, in some cases, the fluctuation of the maximum operable voltage signal V _DDMAX may make the maximum operable voltage signal V _DDMAX smaller than the operable voltage signal V _DDM and the operable voltage signal V _DD . In the exemplary embodiment shown in FIG. 4, the PMOS transistors P4, P5 are characterized in that the threshold voltage of the transistors P4, P5 is greater than the threshold voltage of the PMOS transistors P6, P7. For example, PMOS transistors P4 and P5 have a threshold voltage of about 0.7 volts, and PMOS transistors P6 and P7 have a threshold voltage of about 0.2 volts. When these fluctuations cause the maximum operable voltage signal V _DDMAX to be smaller than the operable voltage signal V _DDM and the operable voltage signal V _DD , the threshold voltage between the PMOS transistors P4 and P5 and the threshold voltages of the PMOS transistors P6 and P7 The difference makes the PMOS transistors P6 and P7 start. Under these circumstances, when the maximum operable voltage signal V _DDMAX is smaller than the operable voltage signal V _DDM and the operable voltage signal V _DD , the PMOS transistor P6 and the PMOS transistor P7 are activated by their corresponding threshold voltages (that is, closure). The PMOS transistor P6 obtains the current I _DD from the operable voltage signal V _DD to adjust (that is, increase) the maximum operable voltage signal V _DDMAX when starting up. Similarly, the PMOS transistor P7 obtains the current _IDDM from the operable voltage signal V _DDM when starting up, so as to adjust (ie, increase) the maximum operable voltage signal V _DDMAX . This adjustment of the maximum operable voltage signal V _DDMAX by the latch-up prevention circuit 404 ensures that the maximum operable voltage signal V _DDMAX is sufficient to prevent latch-up of the transistors P5 - P7 .

Exemplary Operation of Exemplary Memory Storage System

FIG. 5 shows a flow diagram of an exemplary operation of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. The present disclosure is not limited to this description of operations. Rather, other operable control procedures are within the scope and spirit of the present disclosure, as will be apparent to those of ordinary skill in the relevant art. The following discussion describes an exemplary operational flow 500 of a memory storage system, such as the memory storage system 100 or the memory storage system 500 provided as examples.

At operation 502 , the example operational flow 500 selects a maximum operable voltage signal from a plurality of operable voltage signals. In an exemplary embodiment, operation 502 may be performed by voltage generator circuit 102 as described above in FIG. 1 .

At operation 504, the exemplary operational flow 500 applies a maximum operable voltage signal, such as the maximum operable voltage signal V _DDMAX as described above, to at least one base (B) of at least one transistor of the memory storage system terminal, the memory storage system such as PMOS transistor P4, PMOS transistor P5, PMOS transistor P6 and PMOS transistor P7 as described above in FIG. At least one gate (G) terminal of a crystal, such as PMOS transistor P6 and PMOS transistor P7 as described above in FIG. 4 , of the memory storage system. In an exemplary embodiment, operation 504 may be performed by selecting circuits 104.1-104.x as described above in FIG. 1 , selecting circuits 200.1-200.m as described above in FIG. 2A , as described above in FIG. The described selection circuits 220.1-200. n and/or the selection circuit 400 as described above in FIG. 4 are performed.

At operation 506 , the example operational flow 500 adjusts (eg, increases) the maximum operational voltage signal when the maximum operational voltage signal fluctuates below a first operational voltage signal from the plurality of operational voltage signals. In an exemplary embodiment, operation 504 may be performed by selecting circuits 104.1-104.x as described above in FIG. 1 , selecting circuits 200.1-200.m as described above in FIG. 2A , as described above in FIG. The described selection circuits 220.1-200. n and/or the selection circuit 400 as described above in FIG. 4 are performed. In some cases, the maximum operable voltage signal may fluctuate. These fluctuations may be caused by unwanted electromagnetic coupling and/or leakage between various regions of the various transistors of the memory storage system. The exemplary operational flow 500 may cause current to be derived from the first operational voltage signal to increase the maximum operational voltage signal when the maximum operational voltage signal fluctuates below the first operational voltage signal.

in conclusion

The foregoing embodiments disclose a selection circuit for selectively providing an operable voltage signal to a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. A switching circuit having a plurality of transistors selects an operable voltage signal from among the operable voltage signals. The maximum operable voltage signal among the operable voltage signals is selectively applied to the base terminal of the transistor. The latch-up prevention circuit dynamically adjusts the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

In the foregoing specific implementation manner, the plurality of transistors include a first transistor and a second transistor. The first transistor is configured to selectively provide a first operable voltage signal from the plurality of operable voltage signals. The second transistor is configured to selectively provide a second operable voltage signal from the plurality of operable voltage signals. The maximum operable voltage signal is selectively applied to the first base terminal of the first transistor and the second base terminal of the second transistor.

In the foregoing specific implementation manners, the first transistor and the second transistor include p-type metal oxide semiconductor (PMOS) transistors.

In the foregoing embodiments, the first transistor is configured to selectively provide the first operable voltage signal in response to the bias control signal being at a first logic level. A second transistor configured to selectively provide the second operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different than the first logic level bit.

In the foregoing embodiments, the latch-up prevention circuit includes a first diode-junction transistor and a second diode-junction transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to a first operable voltage signal and a second operable voltage signal among the plurality of operable voltage signals. The first diode-connected transistor is configured to obtain a first current from said first operable voltage signal at start-up to adjust said maximum operable voltage signal to compensate for said maximum operable voltage signal. Said fluctuations. The second diode-connected transistor is configured to obtain a second current from the second operable voltage signal at start-up to adjust the maximum operable voltage signal to compensate for the maximum operable voltage signal of the fluctuations.

In the foregoing specific implementation manner, the first threshold voltage of the first transistor and the second threshold voltage of the second transistor are greater than the third threshold voltage and the third threshold voltage of the first diode-connected transistor. The second diode is connected to the fourth threshold voltage of the transistor.

In the foregoing specific implementation manner, when the maximum operable voltage signal is smaller than the first operable voltage signal, the first diode-connected transistor is set to The third threshold voltage of the crystal is turned on. When the maximum operable voltage signal is smaller than the second operable voltage signal, the second diode-connected transistor is configured to pass through the fourth peripheral of the second diode-connected transistor. limited voltage start.

The foregoing embodiments also disclose a selection circuit for a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. A switching circuit with a plurality of transistors provides an operable voltage signal selected from a plurality of operable voltage signals to the memory storage system. A latch-up prevention circuit having a first diode-junction transistor and a second diode-junction transistor applies a maximum operable voltage signal selected from a plurality of operable voltage signals to the first diode-junction transistor The first base terminal and the second diode are connected to the second base terminal of the transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to a second operable voltage signal and a third operable voltage signal among the plurality of operable voltage signals. The first diode-connected transistor obtains the first current from the second operable voltage signal to adjust the second operable voltage signal to compensate the fluctuation of the maximum operable voltage signal when starting. The second diode-connected transistor obtains a second current from the third operable voltage signal during start-up to adjust the second operable voltage signal, thereby compensating fluctuations of the maximum operable voltage signal.

In the foregoing embodiments, the latch-up prevention circuit is further configured to apply the maximum operable voltage signal to at least one base terminal of at least one transistor among the plurality of transistors.

In the foregoing embodiments, the second operable voltage signal is configured to reverse bias a parasitic diode located between the source terminal of the at least one transistor and the well region of the at least one transistor.

In the foregoing detailed description, at least one transistor includes a p-type metal oxide semiconductor (PMOS) transistor. The maximum operable voltage signal is configured to reverse bias the parasitic diode between the source terminal of the at least one transistor and the n-type well region of the at least one transistor.

In the foregoing specific implementation manners, the first diode-connected transistor and the second diode-connected transistor include a diode-connected p-type metal oxide semiconductor (PMOS) transistor.

In the foregoing specific implementation manner, the shutdown circuit is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from among the plurality of operable voltage signals, so as to switch the memory storage system maximizing read/write speed, or selectively providing a minimum operable voltage signal as the operable voltage signal from among the plurality of operable voltage signals to minimize power consumption of the memory storage system .

In the foregoing specific implementation manner, the first diode-connected transistor includes a first source terminal coupled to the second operable voltage signal, a first gate terminal coupled to the maximum operable voltage signal, and a first gate terminal coupled to the maximum operable voltage signal. connected to the first drain terminal of the maximum operable voltage signal. The second diode-connected transistor includes a second source terminal coupled to the third operable voltage signal, a second gate terminal coupled to the maximum operable voltage signal, and a second gate terminal coupled to the maximum operable voltage signal. The second drain terminal of the voltage signal.

In the foregoing embodiments, the first transistor among the plurality of transistors is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals. A second transistor among the plurality of transistors is configured to selectively provide a minimum operable voltage signal as the operable voltage signal from among the plurality of operable voltage signals.

In the foregoing embodiments, the first transistor is configured to selectively provide the maximum operable voltage signal in response to the bias control signal being at the first logic level. a second transistor configured to selectively provide the minimum operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different than the first logic level .

The foregoing detailed description further discloses a method for preventing latch-up of a memory storage system. The method applies the maximum operable voltage signal to at least one base region of at least one transistor of the memory storage system and to at least one gate region of the at least one transistor, and when the maximum operable voltage signal is within a plurality of The maximum operable voltage signal is increased when the first operable voltage signal fluctuates below the operable voltage signal.

In the foregoing specific implementation manner, the step of increasing includes: when the maximum operable voltage signal fluctuates below the first operable voltage signal, obtaining a current from the first operable voltage signal to increase the Maximum operable voltage signal.

In the foregoing specific implementation manner, the method for preventing latch-up of a memory storage system further includes: using the memory storage system to select an operable voltage signal from the plurality of operable voltage signals to dynamically control all Describe the operating parameters of the memory storage system.

In the foregoing specific implementation manner, the step of selecting the operable voltage signal includes: using the memory storage system to select the maximum operable voltage signal from the plurality of operable voltage signals, so as to save the memory The read/write speed of the memory storage system is maximized, or the minimum operable voltage signal is selected from the plurality of operable voltage signals, so as to minimize the power consumption of the memory storage system.

The foregoing detailed description refers to the accompanying drawings to illustrate exemplary embodiments consistent with the present disclosure. References to "exemplary embodiments" in the foregoing detailed description indicate that the described exemplary embodiments may include a particular feature, structure, or characteristic, but each exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same illustrative embodiment. In addition, any feature, structure or characteristic described in connection with an exemplary embodiment may be included independently or in any combination whether or not the features, structures or characteristics of other exemplary embodiments are explicitly described.

The foregoing detailed description is not meant to be limiting. Instead, the scope of the disclosure is defined only in terms of the following claims and their equivalents. It should be understood that the foregoing detailed description, rather than the following summary of the invention, is intended to be used to interpret the claims. The Abstract of the Invention section may set forth one or more, but not all, illustrative embodiments of the present disclosure, and thus is not intended to limit in any way the present disclosure and the following claims and their equivalents.

The illustrative embodiments described in the foregoing Detailed Description have been provided for purposes of illustration and are not intended to be limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments while remaining within the spirit and scope of the disclosure. The foregoing detailed description has been described in terms of functional building blocks to illustrate the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The embodiments of the present disclosure can be implemented in hardware, firmware, software or any combination thereof. Embodiments of the present disclosure can also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing circuit). For example, a machine-readable medium may include non-transitory machine-readable media such as read-only memory (ROM); random-access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; media. As another example, a machine-readable medium may comprise transitory machine-readable medium, such as an electrical, optical, acoustic, or other form of propagated signal (eg, carrier wave, infrared signal, digital signal, etc.). Additionally, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be understood that such descriptions are for convenience only, and that such actions are in fact caused by computing devices, processors, controllers, or other devices executing firmware, software, routines, instructions, and the like.

The foregoing detailed description fully discloses the general nature of this disclosure: others can easily, without departing from the spirit and scope of this disclosure, and without undue experimentation, by applying the understanding of those with ordinary knowledge in the relevant technical field. Modify and/or adapt such exemplary embodiments for various applications. Therefore, such adaptations and modifications are intended to come within the meaning and range of equivalents of these exemplary embodiments, based on the teaching and guidance presented herein. It should be understood that the words or phrases herein are for the purpose of description rather than limitation, such that the words or phrases in this specification should be interpreted by those of ordinary skill in the relevant art in light of the teachings herein.

:偏壓控制信號 502、504、506:操作 I_DD 、I_DDM 、:電流 N1~N3、N4:n型金屬氧化物半導體電晶體 P1、P2、P4、P5、P6、P7:p型金屬氧化物半導體電晶體 V₁ 、V_DD 、V_DDM 、V_{DDM_INT} 、V_{DDM_INT.1} 、V_{DDM_INT.m} 、V_{DDM_INT.n} 、V_{DDM_INT.x} 、V _m :可操作電壓信號 V_DDMAX :最大可操作電壓信號100, 500: memory storage system 102: voltage generator circuit 104.1, 104. x , 200.1~200. m , 220.1~220. n , 400: selection circuit 106, 202, 222: memory device 150: bias voltage control Signal 152: selection control signal 204, 224: memory array 210.1.1 ~ 210.m.n , 226.1.1~ 226.m.n : memory unit 212.1 ~ 212.n , 350: word line 214.1, 214.n m , 352: bit line 300: SRAM cell 402: switch circuit 404: latch-up prevention circuit 452,

: bias control signal 502, 504, 506: operation I _DD , I _DDM ,: current N1~N3, N4: n-type metal oxide semiconductor transistor P1, P2, P4, P5, P6, P7: p-type metal oxide Material semiconductor transistor V ₁ , V _DD , V _DDM , V _{DDM_INT} , V _{DDM_INT.1} , V _{DDM_INT. m} , V _{DDM_INT. n} , V _{DDM_INT. x} , V _m : operable voltage signal V _DDMAX : maximum operable voltage Signal

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. FIG. 2A shows a block diagram of a first exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. 2B shows a block diagram of a second exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. FIG. 3 shows a block diagram of an exemplary static random-access memory (SRAM) unit that may be implemented within an exemplary memory device according to disclosed exemplary embodiments. FIG. 4 shows a block diagram of an exemplary selection circuit that may be implemented in an exemplary memory device according to exemplary embodiments of the present disclosure. FIG. 5 shows a flow diagram of an exemplary operation of an exemplary memory storage system according to an exemplary embodiment of the present disclosure.

100:Memory storage system

102: Voltage generator circuit

104.1, 104.x : Selection circuit

106: Memory device

150: Bias voltage control signal

152: select control signal

V ₁ , V _{DDM_INT.1} , V _{DDM_INT. x} , V _m : operable voltage signals

V _DDMAX : Maximum operable voltage signal

Claims (10)

A latch-up prevention circuit for a memory storage system, comprising: a first transistor and a second transistor respectively configured to apply a first operable voltage signal selected from a plurality of operable voltage signals to all The first base terminal of the first transistor, the first drain terminal of the first transistor, the second base terminal of the second transistor, and the second drain terminal of the second transistor, wherein the The first transistor and the second transistor are respectively coupled to the second operable voltage signal and the third operable voltage signal among the plurality of operable voltage signals, wherein the first transistor is further configured to Obtaining a first current from the second operable voltage signal at startup to adjust the first operable voltage signal to compensate for fluctuations in the first operable voltage signal, and wherein the second transistor also Arranged to derive a second current from the third operable voltage signal at start-up to adjust the first operable voltage signal to compensate for the fluctuations in the first operable voltage signal. The latch-up prevention circuit as claimed in claim 1, wherein said first transistor is configured to be activated in response to said first operable voltage signal, wherein said first operable voltage signal is greater than said second operable voltage signal an operating voltage signal less than at least a first threshold voltage of said first transistor, and wherein said second transistor is configured to be activated in response to said first operational voltage signal, wherein said first operational voltage The signal is smaller than the third operable voltage signal by at least a second threshold voltage of the second transistor. The latch-up prevention circuit as claimed in claim 2, wherein when said first transistor is activated, it is configured to obtain said first current to increase said first operable voltage signal, and wherein said second transistor is set to obtain said first flow from a second source region to a second drain region when said second transistor is activated. two currents to increase the first operable voltage signal. A method for preventing latch-up of a memory storage system comprising: applying, by the memory storage system, a first operable voltage signal selected from a plurality of operable voltage signals to a first diode-junction transistor the first base terminal of the first diode-junction transistor, the first drain terminal of the first diode-junction transistor, the second base terminal of the second diode-junction transistor, and the second drain terminal of the second diode-junction transistor extreme; by activating the first diode-connected transistor to adjust the first operable voltage signal to compensate for fluctuations in the first operable voltage signal, so that the memory storage system obtains information from multiple a first current of a second operable voltage signal among two operable voltage signals; and adjusting the first operable voltage signal by activating the second diode junction transistor to compensate for the first operable voltage signal The voltage signal fluctuates, so that the memory storage system obtains a second current from a third operable voltage signal among the plurality of operable voltage signals. The method according to claim 4, wherein the step of obtaining the first current comprises: activating the first diode junction transistor in response to the first operable voltage signal, wherein the first operable voltage a signal less than the second operable voltage signal by at least a first threshold voltage of the first transistor; and wherein the step of obtaining the second current comprises: activating the second diode-junction transistor in response to the first operable voltage signal, wherein the first operable voltage signal is smaller than the third operable voltage signal by at least a second transistor of the second transistor. 2. Threshold voltage. The method according to claim 5, wherein the step of obtaining the first current further comprises: obtaining the current from the first source region to the first drain region when the first diode junction transistor is activated said first current to increase said first operable voltage signal, and wherein said step of obtaining said second current comprises: obtaining said second source region to said second current when said second diode junction transistor is activated The second current in the two drain regions increases the first operable voltage signal. A latch-up prevention circuit for a memory storage system, comprising: a transistor configured to apply a first operable voltage signal selected from a plurality of operable voltage signals to a base terminal of the transistor and the The drain terminal of the transistor, wherein the transistor is coupled to a second operable voltage signal among the plurality of operable voltage signals, and wherein the transistor is also configured to obtain a signal from the second operable voltage signal. A current of the voltage signal is manipulated to adjust the first operable voltage signal to compensate for fluctuations in the first operable voltage signal. The latch-up prevention circuit of claim 7, wherein the transistor is configured to be activated in response to the first operable voltage signal, wherein the first operable voltage signal is greater than the second operable voltage signal signal small at least the transistor's threshold voltage. The latch-up prevention circuit of claim 8, wherein said transistor is configured to obtain said current from a source region to a drain region to increase said first operable voltage signal when activated. A selection circuit for selectively providing an operable voltage signal to a memory storage system, comprising: a switch circuit having a plurality of transistors configured to select the operable voltage signal from among a plurality of operable voltage signals , the switch circuit is configured to provide the operable voltage signal to the memory storage system, a maximum operable voltage signal among the plurality of operable voltage signals is selectively applied to the plurality of transistors a base terminal of the transistor and a drain terminal of the transistor; and a latch-up prevention circuit configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

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