TWI789183B - Checker and checking method for processor circuit - Google Patents

Abstract

The present disclosure provides a checker and a checking method for a processor circuit. The checking method includes: determining whether a data cache send a data refill request under a branch prediction executing status for obtaining a first result; determining whether data requested by the data refill request is wrote into a register and calculated under the branch prediction executing status for obtaining a second result; and determining whether the processor circuit has a vulnerability according to the first result and the second result.

Description

Detector and detection method for processor circuit

The present invention relates to a detector and a detection method, in particular to a detector and a detection method used in a processor circuit.

In conventional processor architectures, functions of out-of-order execution and branch prediction are introduced to improve instruction processing performance. However, processors with out-of-order execution and branch prediction functions have information security loopholes, which are easy to be attacked by hackers and steal their data. Among them, the specter attack (spectre attack) is a fairly common attack mode.

In order to avoid being attacked by the Specter vulnerability, the existing solutions mainly include: (1) use a software solution to turn off the branch prediction function; or (2) insert a barrier instruction (barrier instruction) in the program segment that has information security concerns. However, such solutions will seriously affect the performance of the processor.

The object of the present invention is to provide a detection method for a processor circuit. The processor circuit includes an out-of-order execution (out-of-order execution) and a branch prediction (branch prediction) unit. The detection method includes: judging whether the data cache is in Branch Prediction Execution Status Send a data backfill request in the state to obtain the first judgment result; judge whether the data required by the data backfill request is written into the temporary register and calculated in the branch prediction execution state to obtain the second judgment result; and according to the first judgment As a result and the second judgment result, it is judged whether the processor circuit has an attack vulnerability.

The present invention further provides a detector for a processor circuit. The processor circuit includes an out-of-order execution and branch prediction unit, and the detector includes a first detection module, a second detection module, and a judgment module. The first detection module is used for judging whether the data cache of the processor circuit sends a data backfill request in the state of branch prediction execution, so as to obtain a first judging result. The second detection module is used for judging whether the data required by the data backfill request is written into the temporary register of the processor circuit under the execution state of the branch prediction and operated, so as to obtain the second judging result. The judging module is used for judging whether the processor circuit has an attack vulnerability according to the first judging result and the second judging result.

1: detector

11: The first detection module

13: Second detection module

15: Judgment module

2: detector

21: The first detection module

23: The second detection module

25: Judgment module

7: Lower layer memory

8: Processor circuit

81: Out-of-order execution and branch prediction unit

811:Reorder buffer

83: scratchpad

85: Data cache

850: Data backfill request

851:MSHR

852: data

87: Memory access unit

89: Operation unit

9: Processor circuit

91: Out-of-order execution and branch prediction unit

93: scratchpad

95:Data cache

950: Data backfill request

952: data

S301~S304: steps

S401~S406: steps

Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Figure 1A is a block diagram of a detector of some embodiments of the present invention.

Figure IB is a block diagram of a detector of some embodiments of the invention.

Figure 2A is a block diagram of a detector of some embodiments of the present invention.

Figure 2B is a block diagram of a detector of some embodiments of the present invention.

Fig. 3 is a flow chart of the detection method of some embodiments of the present invention.

Fig. 4 is a flow chart of the detection method of some embodiments of the present invention.

Embodiments of the invention are discussed in more detail below. However, it should be understood that the The invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only and do not limit the scope of the invention.

Please refer to FIG. 1A , which is a block diagram of a detector 1 according to some embodiments of the present invention. The detector 1 is used to detect whether a processor circuit 9 has an attack vulnerability (for example: ghost attack, spectre attack). In some embodiments, the processor circuit 9 includes: an out-of-order execution and branch prediction unit 91 , a register 93 and a data cache 95 . The out-of-order execution and branch prediction unit 91 is used for decoding instructions and executing the decoded instructions in an out-of-order manner. The out-of-order execution and branch prediction unit 91 has the function of branch prediction, and can record the state of branch prediction, such as: branch prediction execution state (branch prediction unlocked state) and branch prediction unexecuted state (branch prediction unlocked state).

In some embodiments, the detector 1 includes a first detection module 11 , a second detection module 13 and a judgment module 15 . Specifically, the first detection module 11 is used to judge whether the data cache 95 of the processor circuit 9 sends a data refill request (data refill request) in the state of branch prediction execution, so as to obtain a first judgment result. The second detection module 13 is used for judging whether one of the data required by the data backfill request is written into the register 93 of the processor circuit 9 in the state of branch prediction execution and operated to obtain a second judging result. The judging module 15 is used for judging whether the processor circuit 9 has an attack vulnerability according to the first judging result and the second judging result.

Please refer to FIG. 1B. In some embodiments, when the first detection module 11 determines that the data cache 95 of the processor circuit 9 sends a data backfill request 950 under the branch prediction execution state, the second detection module 13 further judges Whether the data requested by the data backfill request 950 is written into the register 93 of the processor circuit 9 and operated on in the branch prediction execution state. When the second detection module 13 judges that one of the data 952 required by the data backfill request 950 is in the state of branch prediction execution After being written into the temporary register 93 of the processor circuit 9 and calculated, the judgment module 15 judges that the processor circuit 9 may have an attack vulnerability according to the detection results of the first detection module 11 and the second detection module 13 .

In some embodiments, when: (1) the first detection module 11 determines that the data cache 95 of the processor circuit 9 has not sent any data backfill request in the branch prediction execution state; (2) when the second detection module 13. Judging that the data 952 required by the data backfill request 950 has not been written into the temporary register 93 of the processor circuit 9 in the state of branch prediction execution; or (3) when the second detection module 13 judges that the data 952 is not in the state of branch prediction execution state is calculated, then the judging module 15 judges that the processor circuit 9 may not have an attack vulnerability according to the detection results of the aforementioned first detection module 11 and the second detection module 13 .

In particular, in some embodiments, the aforementioned processor circuits and detectors may include hardware circuits, elements of processor circuits (such as out-of-order execution and branch prediction units, registers, and data caches) and detectors. The components of the device (the first detection module, the second detection module and the judgment module) transmit data and signals through electrical connections. In some embodiments, the signal and data transmission among the aforementioned processor circuit, detector and components can also be simulated by software (eg Electronic Design Automation, EDA).

Please refer to FIG. 2A , which is a block diagram of a detector 2 according to some embodiments of the present invention. The detector 2 is used to detect whether a processor circuit 8 has an attack vulnerability. In some embodiments, the processor circuit 8 includes: an out-of-order execution and branch prediction unit 81, a register 83, a data cache 85, a memory access unit (load-store unit) 87, and an operation Unit 89. The out-of-order execution and branch prediction unit 81 is used for decoding instructions and executing the decoded instructions in an out-of-order manner. The out-of-order execution and branch prediction unit 81 has the function of branch prediction, and can record the branch prediction state (for example: branch prediction execution state and branch prediction non-execution state) in a rearrangement Reorder buffer (reorder buffer) 811. The data cache 85 has a miss status holding register (MSHR) 851 .

In some embodiments, the detector 2 includes a first detection module 21 , a second detection module 23 and a judgment module 25 . Specifically, the first detection module 21 is used to determine that a cache miss occurs in the data cache 85 of the processor circuit 8 in the state of branch prediction execution. Due to a cache miss, a data backfill request may be generated. The first detection module 21 is used to determine whether the MSHR 851 of the data cache 85 sends a message to the lower-level memory 7 (for example: second-level cache L2 cache, bus-connected memory, etc.) in the state of branch prediction execution. The data backfill request is used to obtain a first judgment result.

The second detection module 23 is used to determine whether the memory access unit 87 writes one of the data required by the data backfill request to the temporary register 83 under the branch prediction execution state and whether the operation unit 89 stores the data under the branch prediction execution state. Get the data of the temporary register 83 to obtain a second judgment result. The judging module 25 is used for judging whether the processor circuit 8 has an attack vulnerability according to the first judging result and the second judging result.

Please refer to FIG. 2B. In some embodiments, when the first detection module 21 judges that a cache miss occurs in the data cache 85 of the processor circuit 8 in the state of branch prediction execution, and judges that the data cache of the processor circuit 8 85 sends a data backfill request 850 under the branch prediction execution state, then the second detection module 23 further judges whether the data required by the data backfill request 850 is written into the register 83 of the processor circuit 8 under the branch prediction execution state and is computed.

Furthermore, when the second detection module 23 judges that the memory access unit 87 is in the branch prediction execution state, one of the data 852 required by the data backfill request 850 is written from the data cache 85 to the temporary register of the processor circuit 8 83, and the judging operation unit 89 accesses the data 852 of the temporary register 83 under the branch prediction execution state, then the judging module 85 is based on the aforementioned first detecting module 81 and The detection result of the second detection module 83 determines that the processor circuit 8 may have an attack vulnerability.

In some embodiments, when: (1) the first detection module 21 determines that the data cache 85 of the processor circuit 8 has not sent any data backfill request in the branch prediction execution state; (2) when the second detection module 23 Judging that the data 852 required by the data backfill request 850 has not been written into the temporary register 83 of the processor circuit 8 by the memory access unit 87 in the branch prediction execution state; or (3) when the second detection module 23 judges the data 852 is not accessed by the computing unit 89 in the branch prediction execution state, then the judging module 85 judges that the processor circuit 8 may not have an attack vulnerability according to the detection results of the aforementioned first detection module 81 and the second detection module 83 .

In some embodiments, in addition to the reordering buffer 811, the out-of-order execution and branch prediction unit 81 of the processor circuit 8 may further include: an instruction fetch/branch prediction (instruction fetch/branch prediction) unit, an instruction decoding (instruction decode) unit and register renaming, dispatch and instruction retirement (register renaming/dispatch/retire) unit.

It should be specially noted that whether the aforementioned various operations are performed in the branch prediction execution state can be determined according to the data of the reordering buffer 851 at the time point of operation execution. In addition, in some embodiments, the aforementioned processor circuits, detectors, and lower-layer memory may include hardware circuits, elements of processor circuits (such as: out-of-order execution and branch prediction units, registers, data caches, memory access unit, computing unit), components of the detector (the first detection module, the second detection module and the judgment module) and the lower layer memory to transmit data and signals through electrical connection. In some embodiments, the aforementioned processor circuit, detector, lower-level memory, and signal and data transmission between components can also be simulated by software (eg: EDA).

Some embodiments of the present invention include a detection method for a processor circuit, the flowchart of which is shown in FIG. 3 . The processor circuit includes an out-of-order execution and branch prediction unit. These The detection method of the embodiment is implemented by a detector (such as the detector of the aforementioned embodiment), and the detailed operation of the method is as follows. Firstly, step S301 is executed to determine whether a data cache of the processor circuit sends a data backfill request in a branch prediction execution state, so as to obtain a first determination result. If the first judgment result is no, step S304 is executed to judge that the processor circuit has no attack vulnerability. If the first judgment result is yes, then step S302 is executed to judge whether a data required by the data backfill request is written into a register and operated in the branch prediction execution state to obtain a second judgment result. If the second judgment result is negative, step S304 is executed. If the second judgment result is yes, execute step S303 to judge that the processor circuit has an attack vulnerability.

Some embodiments of the present invention include a detection method for a processor circuit, the flowchart of which is shown in FIG. 4 . The processor circuit includes an out-of-order execution and branch prediction unit. The detection methods of these embodiments are implemented by a detector (such as the detector of the aforementioned embodiments), and the detailed operation of the method is as follows. Firstly, step S401 is executed to determine whether a cache miss occurs in a data cache of the processor circuit in a branch prediction execution state. If not, repeat step S401.

If the result of step S401 is yes, execute step S402 to determine whether one of the data caches, MSHR, sends a data backfill request to the lower-level memory in the state of branch prediction execution, so as to obtain a first determination result. If the first determination result is negative, step S406 is executed to determine that the processor circuit has no attack vulnerability. If the first judgment result is yes, step S403 is executed to judge whether a memory access unit of the processor circuit writes the data required by the data backfill request from the data cache into the register in the state of branch prediction execution. If not, step S406 is executed to determine that the processor circuit has no attack vulnerability.

If the result of step S403 is yes, step S404 is executed to determine whether an operation unit of the processor circuit is accessing the data of the temporary register in the state of branch prediction execution, so as to obtain a second determination result. If the second judgment result is no, execute step S406, and judge that the processor circuit does not have Attack vulnerabilities. If the second judgment result is yes, execute step S405 to judge that the processor circuit has an attack vulnerability.

In summary, the detector and detection method for processor circuits provided by the present invention can determine whether a specific attack operation mode (for example: Specter vulnerability attack mode) may exist through the detection steps, so as to facilitate subsequent adjustment and modification of the processor circuit.

The above description briefly presents the features of some embodiments of the present invention, so that those skilled in the art of the present invention can more fully understand various aspects of the content of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily use the content of the present invention as a basis to design or modify other processes and structures to achieve the same purpose and/or achieve the same as the embodiment here The advantages. Those with ordinary knowledge in the technical field of the present invention should understand that these equivalent embodiments still belong to the spirit and scope of the present invention, and various changes, substitutions and changes can be made without departing from the spirit and scope of the present invention. .

2: detector

21: The first detection module

23: The second detection module

25: Judgment module

7: Lower layer memory

8: Processor circuit

81: Out-of-order execution and branch prediction unit

811:Reorder buffer

83: scratchpad

85: Data cache

850: Data backfill request

851:MSHR

852: data

87: Memory access unit

89: Operation unit

Claims (9)

A detection method for a processor circuit, the processor circuit includes an out-of-order execution (out-of-order execution) and branch prediction (branch prediction) unit and an operation unit, the detection method includes: judging a data block Whether to send a data backfill request in a branch prediction execution state to obtain a first judgment result, wherein, the branch prediction execution state is recorded by the out-of-order execution and branch prediction unit, and the data backfill request is used to send sending from the lower layer memory of the data cache; judging whether a data required by the data backfill request is written into a temporary register and operated by the operation unit in the branch prediction execution state, so as to obtain a second judging result; And according to the first judgment result and the second judgment result, it is judged whether the processor circuit has an attack vulnerability. The detection method according to claim 1, wherein the data backfill request is sent when the first judgment result is that the data cache is in the branch prediction execution state, and the second judgment result is that the data is in the branch prediction execution state When the state is written into the register and operated, it is judged that the processor circuit has an attack vulnerability. The detection method as described in Claim 1 further includes: judging that a cache miss occurs in the data cache in the branch prediction execution state. The detection method as described in claim 3, wherein the step of judging whether the data cache sends the data backfill request in the branch prediction execution state further includes: judging a miss state holding register of the data cache ( miss status holding register (MSHR) whether to send the data backfill request in the branch prediction execution state to obtain the first judgment result. A detector for a processor circuit comprising an out-of-order execution and branch prediction unit and an arithmetic unit, the detector comprising: a first detector A module for: judging whether a data cache of the processor circuit sends a data backfill request in a branch prediction execution state to obtain a first judgment result, wherein the branch prediction execution state is determined by the out-of-order The execution and branch prediction unit records that the data backfill request is used to send to a lower layer memory of the data cache; a second detection module is used to: determine whether the data requested by the data backfill request is in the branch prediction It is written into a temporary register of the processor circuit in the execution state and is operated by the arithmetic unit to obtain a second judgment result; and a judgment module is used for: according to the first judgment result and the second judgment As a result, it is judged whether or not the processor circuit has an attack vulnerability. The detector according to claim 5, wherein the data backfill request is sent when the first judgment result is that the data cache is in the branch prediction execution state, and the second judgment result is that the data is in the branch prediction execution state When the state is written into the temporary register and operated, the judging module judges that the processor circuit has an attack vulnerability. The detector according to claim 5, wherein the first detection module is further used for: judging that a cache miss (cache miss) occurs in the data cache in the execution state of the branch prediction. The detector according to claim 7, wherein the first detection module is further used to: determine whether a miss status holding register (miss status holding register, MSHR) of the data cache is executed in the branch prediction In this state, the data backfill request is sent to the lower memory to obtain the first judgment result. The detector as described in claim 5, wherein the second detection module is further used to: determine whether the data required by the data backfill request is written into the register from the data cache in the branch prediction execution state ; and judging whether the data in the register is operated in the branch prediction execution state, so as to obtain the second judging result.

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