TWI789068B - Calculation method of expansion and contraction value of circuit board and hole forming method of multilayer circuit board - Google Patents
Calculation method of expansion and contraction value of circuit board and hole forming method of multilayer circuit board Download PDFInfo
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- 238000004364 calculation method Methods 0.000 title claims abstract description 59
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本發明涉及一種電路板的漲縮值的計算方法及電路板的孔洞成形方法,特別是一種適用於多層電路板的漲縮值的計算方法及多層電路板的孔洞成形方法。 The invention relates to a method for calculating the expansion and contraction value of a circuit board and a method for forming holes in the circuit board, in particular to a method for calculating the expansion and contraction value of a multilayer circuit board and a method for forming holes in the multilayer circuit board.
現有常見的多層電路板,是由多片芯板相互壓合而成,各個芯板之間會有彼此電性連通的相關線路,且多層電路板通常會有至少一個電鍍通孔(Plated Through Hole,PTH)或是俗稱的導通孔(via)。電鍍通孔或是俗稱的導通孔的成形方式是:先於多層電路板形成貫穿孔,再於貫穿孔中電鍍導電層。 Existing common multilayer circuit boards are formed by pressing multiple core boards together. There are related circuits electrically connected to each other between each core board, and multilayer circuit boards usually have at least one plated through hole (Plated Through Hole). , PTH) or commonly known as the conduction hole (via). The forming method of the plated through hole or commonly known as the via hole is: first forming the through hole in the multi-layer circuit board, and then electroplating the conductive layer in the through hole.
如圖1所示,隨著各個芯板上的線路的線徑變小,貫穿孔的孔徑也隨之縮小,為此,利用現有的多層電路板P的相關製造流程,容易發生貫穿孔H超出芯板預定設置有貫穿孔的容許誤差範圍R的問題(業界俗稱偏破),此問題可能會導致芯板中的線路被破壞等,從而導致多層電路板的製造良率下降的問題。 As shown in Figure 1, as the wire diameter of the circuit on each core board becomes smaller, the aperture diameter of the through hole is also reduced accordingly. The core board is predetermined to be provided with the problem of the allowable error range R of the through hole (commonly known as partial break in the industry). This problem may lead to damage to the circuit in the core board, which will lead to the problem of a decline in the manufacturing yield of the multilayer circuit board.
本發明公開一種電路板的漲縮值的計算方法及多層電路板的孔洞成形方法,主要用以改善現有的漲縮值計算方式及多層電路板的孔洞成形方法,容易出現貫穿孔超出芯板原本預設位置的問題,從而導致多層電路板的製造良率下降的問題。 The invention discloses a method for calculating the expansion and shrinkage value of a circuit board and a hole forming method for a multilayer circuit board, which are mainly used to improve the existing calculation method for the expansion and contraction value and the hole forming method for a multilayer circuit board, and it is easy for through holes to exceed the original core board. The problem of the preset position leads to the problem of a decrease in the manufacturing yield of the multilayer circuit board.
本發明的其中一實施例公開一種電路板的漲縮值的計算方法,其用以供一電路板成型設備的一處理器執行,以使電路板成型設備在對一多層芯板組進行鑽孔前,計算出多層芯板組的一漲縮值,多層芯板組由相互疊合設置的多個芯板構成,多層芯板組被電路板成型設備鑽孔後,將成為一多層電路板,各個芯板具有四個標記單元,多層芯板組的任一個標記單元於一縱向方向不與任一個標記單元完全重疊,縱向方向與各個芯板的法線方向平行;電路板的漲縮值的計算方法包含:一掃描步驟:控制一掃描裝置對多層芯板組進行掃描,以取得各個芯板的各個標記單元的一標記座標;一邊角座標計算步驟:利用各個芯板所對應的四個標記座標及各個芯板相對應的一芯板資訊,計算出各個芯板的四個邊角座標;芯板資訊至少包含一芯板尺寸;一重心座標計算步驟:利用各個芯板的四個邊角座標,計算出各個芯板的一重心座標;一平均重心座標計算步驟:利用多個重心座標計算出一平均重心座標;一基準邊角座標計算步驟:利用平均重心座標及一電路板標準尺寸資訊,計算出四個基準邊角座標;其中,四個基準邊角座標通過四條虛擬線段相連接後,能構成一基準矩形;一容許範圍界定:以各個基準邊角座標為中心,並以一預設容許值為半徑界定出四個初始容許範圍;一調整步驟:調整平均重心座標及四個基準邊角座標,以取得一優化重心座標及四個優化邊角座標;其中,四個優化邊角座標通過四條虛擬線段相連接後,能構成一優化四邊形;優化四邊形與基準矩形於X軸方向的變形量及優化四邊形與基準矩形於Y軸方向的變形量,都不大於一容許變形量;其中,以各個優化邊角座標為中心,並以預設容許值為半徑能界定出的四個優化容許範圍,而落在各個優化容許範圍內的初始邊角座標的總數,不小於落在各個初始容許範圍內的初始邊角座標的總數;一計算步驟:利用基準矩形及優化四邊形計算出多層芯板組的一變形量。 One embodiment of the present invention discloses a method for calculating the expansion and contraction value of a circuit board, which is used for execution by a processor of a circuit board forming equipment, so that the circuit board forming equipment is drilling a multi-layer core board group Before the hole, calculate the expansion and contraction value of the multi-layer core board group. The multi-layer core board group is composed of multiple core boards stacked on each other. After the multi-layer core board group is drilled by the circuit board forming equipment, it will become a multi-layer circuit. Each core board has four marking units, and any marking unit of the multilayer core board group does not completely overlap any marking unit in a longitudinal direction, and the longitudinal direction is parallel to the normal direction of each core board; the expansion and contraction of the circuit board The calculation method of the value includes: a scanning step: controlling a scanning device to scan the multi-layer core board group to obtain a marking coordinate of each marking unit of each core board; a corner coordinate calculation step: using four corresponding to each core board A mark coordinate and a core board information corresponding to each core board, calculate the four corner coordinates of each core board; the core board information includes at least one core board size; a center of gravity coordinate calculation step: use the four Corner coordinates, calculate a center of gravity coordinates of each core board; an average center of gravity coordinates calculation step: use a plurality of center of gravity coordinates to calculate an average center of gravity coordinates; a reference corner coordinates calculation step: use the average center of gravity coordinates and a circuit board standard Size information, calculate four reference corner coordinates; Among them, the four reference corner coordinates can form a reference rectangle after being connected by four virtual line segments; A preset allowable value defines four initial allowable ranges for the radius; an adjustment step: adjust the average center of gravity coordinates and four reference corner coordinates to obtain an optimized center of gravity coordinates and four optimized corner coordinates; wherein, the four optimized After the corner coordinates are connected by four virtual line segments, an optimized quadrilateral can be formed; the deformation amount of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation amount of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than an allowable deformation amount ; Among them, taking each optimized corner coordinate as the center and taking the preset allowable value as the radius to define four optimized allowable ranges, and the total number of initial corner coordinates falling within each optimized allowable range is not less than The total number of initial corner coordinates within each initial allowable range; a calculation step: calculate a deformation amount of the multi-layer core board group by using the reference rectangle and the optimized quadrilateral.
本發明的其中一實施例公開一種多層電路板的孔洞成形方法,其包含:一準備步驟:準備一多層芯板組,多層芯板組由相互疊合設置的多個芯板構成,任一個標記單元於一縱向方向不與任一個標記單元完全重疊,縱向方向與第一芯板的一表面的一法線相互平行;一掃描步驟:控制一掃描裝置對多層芯板組進行掃描,以取得各個芯板的各個標記單元的一標記座標;一邊角座標計算步驟:利用各個芯板所對應的四個標記座標及各個芯板相對應的一芯板資訊,計算出各個芯板的四個邊角座標;芯板資訊至少包含一芯板尺寸;一重心座標計算步驟:利用各個芯板的四個邊角座標,計算出各個芯板的一重心座標;一平均重心座標計算步驟:利用多個重心座標計算出一平均重心座標;一基準邊角座標計算步驟:利用平均重心座標及一電路板標準尺寸資訊,計算出四個基準邊角座標;其中,四個基準邊角座標通過四條虛擬線段相連接後,能構成一基準矩形;一容許範圍界定:以各個基準邊角座標為中心,並以一預設容許值為半徑界定出四個初始容許範圍;一調整步驟:調整平均重心座標及四個基準邊角座標,以取得一優化重心座標及四個優化邊角座標;其中,四個優化邊角座標通過四條虛擬線段相連接後,能構成一優化四邊形;優化四邊形與基準矩形於X軸方向的變形量及優化四邊形與基準矩形於Y軸方向的變形量,都不大於一容許變形量;其中,以各個優化邊角座標為中心,並以預設容許值為半徑能界定出的四個優化容許範圍,而落在各個優化容許範圍內的初始邊角座標的總數,不小於落在各個初始容許範圍內的初始邊角座標的總數;一計算步驟:利用基準矩形及優化四邊形計算出多層芯板組的一變形量。 One embodiment of the present invention discloses a method for forming a hole in a multilayer circuit board, which includes: a preparation step: preparing a multilayer core board group, the multilayer core board group is composed of a plurality of core boards stacked on each other, any one The marking unit does not completely overlap with any marking unit in a longitudinal direction, and the longitudinal direction is parallel to a normal line of a surface of the first core board; a scanning step: controlling a scanning device to scan the multi-layer core board group to obtain A mark coordinate of each mark unit of each core board; a corner coordinate calculation step: use four mark coordinates corresponding to each core board and a core board information corresponding to each core board to calculate the four sides of each core board Angle coordinates; core board information includes at least one core board size; a center of gravity coordinate calculation step: use the four corner coordinates of each core board to calculate a center of gravity coordinate of each core board; an average center of gravity coordinate calculation step: use multiple The center of gravity coordinates calculate an average center of gravity coordinate; a reference corner coordinate calculation step: use the average center of gravity coordinates and a circuit board standard size information to calculate four reference corner coordinates; wherein, the four reference corner coordinates pass through four virtual line segments After being connected, a standard rectangle can be formed; one allowable range definition: take the coordinates of each reference corner as the center, and define four initial allowable ranges with a preset allowable value as the radius; one adjustment step: adjust the average center of gravity coordinates and Four reference corner coordinates, to obtain an optimized center of gravity coordinates and four optimized corner coordinates; wherein, after the four optimized corner coordinates are connected by four virtual line segments, an optimized quadrilateral can be formed; the optimized quadrilateral and the reference rectangle are at X The amount of deformation in the axial direction and the amount of deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than an allowable amount of deformation; where the coordinates of each optimized corner are the center, and the radius can be defined by the preset allowable value Four optimization allowable ranges, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range; a calculation step: using the reference rectangle and optimized quadrilateral calculation A deformation amount of the multi-layer core board group.
綜上,本發明的電路板的漲縮值的計算方法及多層電路板的孔洞成形方法,可以大幅地降低貫穿孔超出芯板原本預設位置的問題的發生機率,而可有效地提升多層電路板的製造良率。 To sum up, the method for calculating the expansion and contraction value of the circuit board and the hole forming method for the multi-layer circuit board of the present invention can greatly reduce the occurrence probability of the problem that the through hole exceeds the original preset position of the core board, and can effectively improve the multi-layer circuit board. board manufacturing yield.
為能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,但是此等說明與附圖僅用來說明本發明,而非對本發明的保護範圍作任何的限制。 In order to further understand the characteristics and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention, but these descriptions and drawings are only used to illustrate the present invention, rather than to make any statement on the scope of protection of the present invention. limit.
P:多層電路板 P: multilayer circuit board
H:貫穿孔 H: through hole
R:容許誤差範圍 R: allowable error range
S11~S18:流程步驟 S11~S18: Process steps
SX1~SX10:流程步驟 SX1~SX10: process steps
100:多層芯板組 100: multi-layer core board group
111、112、113、114:標記單元 111, 112, 113, 114: marking unit
121、122、123、124:標記單元 121, 122, 123, 124: marking unit
131、132、133、134:標記單元 131, 132, 133, 134: marking unit
141、142、143、144:標記單元 141, 142, 143, 144: marking unit
A1:線路區 A1: Line area
A2:非線路區 A2: Non-line area
11、12、13、14:芯板 11, 12, 13, 14: core board
11A、12A、13A、14A:寬側面 11A, 12A, 13A, 14A: wide side
B1、B2、B3、B4:虛擬矩形 B1, B2, B3, B4: virtual rectangles
C1:虛擬軸線 C1: virtual axis
C2:虛擬軸線 C2: virtual axis
Z:邊框 Z: border
C11、C12、C13、C14:邊角座標 C11, C12, C13, C14: corner coordinates
C21、C22、C23、C24:邊角座標 C21, C22, C23, C24: corner coordinates
C31、C32、C33、C34:邊角座標 C31, C32, C33, C34: corner coordinates
C41、C42、C43、C44:邊角座標 C41, C42, C43, C44: corner coordinates
G1、G2、G3、G4:重心座標 G1, G2, G3, G4: Coordinates of center of gravity
AVG:平均重心座標 AVG: average center of gravity coordinates
FVG:優化重心座標 FVG: Optimize the center of gravity coordinates
SG1、SG2、SG3、SG4:基準邊角座標 SG1, SG2, SG3, SG4: base corner coordinates
TR1、TR2、TR3、TR4:初始容許範圍 TR1, TR2, TR3, TR4: initial tolerance range
FG1、FG2、FG3、FG4:優化邊角座標 FG1, FG2, FG3, FG4: Optimize corner coordinates
FR1、FR2、FR3、FR4:優化容許範圍 FR1, FR2, FR3, FR4: Optimized tolerance range
圖1為習知的多層電路板的局部示意圖。 FIG. 1 is a partial schematic diagram of a conventional multilayer circuit board.
圖2為本發明的電路板的漲縮值的計算方法的流程示意圖。 Fig. 2 is a schematic flowchart of the calculation method of the expansion and contraction value of the circuit board of the present invention.
圖3為本發明的電路板的漲縮值的計算方法中的多層芯板組的示意圖。 Fig. 3 is a schematic diagram of a multi-layer core board group in the method for calculating the expansion and contraction value of a circuit board according to the present invention.
圖4為本發明的電路板的漲縮值的計算方法中的多層芯板組的分解示意圖。 Fig. 4 is an exploded schematic view of the multi-layer core board group in the method for calculating the expansion and contraction value of the circuit board according to the present invention.
圖5為掃描裝置掃描本發明的多層芯板組後得到的影像。 FIG. 5 is an image obtained by a scanning device after scanning the multi-layer core board assembly of the present invention.
圖6為處理器執行本發明的電路板的漲縮值的計算方法的掃描步驟及邊角座標計算步驟的示意圖。 6 is a schematic diagram of a processor executing the scanning step and the corner coordinate calculation step of the method for calculating the expansion and contraction value of the circuit board of the present invention.
圖7為處理器執行本發明的電路板的漲縮值的計算方法的重心座標計算步驟、平均重心座標計算步驟、基準邊角座標計算步驟及容許範圍界定步驟的示意圖。 7 is a schematic diagram of a processor executing the steps of calculating the center of gravity coordinates, calculating the average center of gravity coordinates, calculating the reference corner coordinates and defining the allowable range of the calculation method for the expansion and contraction value of the circuit board of the present invention.
圖8為處理器執行本發明的電路板的漲縮值的調整步驟的示意圖。 FIG. 8 is a schematic diagram of the adjustment steps of the expansion and contraction value of the circuit board performed by the processor according to the present invention.
圖9為本發明的多層電路板的孔洞成形方法。 FIG. 9 is a method for forming a hole in a multilayer circuit board of the present invention.
於以下說明中,如有指出請參閱特定圖式或是如特定圖式所示,其僅是用以強調於後續說明中,所述及的相關內容大部份出現於該特定圖式中,但不限制該後續說明中僅可參考所述特定圖式。 In the following description, if it is pointed out that please refer to the specific drawing or as shown in the specific drawing, it is only used to emphasize in the subsequent description, most of the relevant content mentioned appears in the specific drawing, It is not intended, however, to limit the ensuing description to only those particular drawings referred to.
請一併參閱圖2至圖5,本發明的電路板的漲縮值的計算方法,用以供一電路板成型設備的一處理器執行,以使電路板成型設備在對一 多層芯板組進行鑽孔前,計算出多層芯板組的一漲縮值,多層芯板組由相互疊合設置的多個芯板構成,各個芯板具有四個標記單元,多層芯板組的任一個標記單元於一縱向方向(例如是圖3中的Z軸方向)不與任一個標記單元完全重疊,縱向方向與多層芯板組的一表面的一法線相互平行。 Please refer to Fig. 2 to Fig. 5 together, the calculation method of the expansion and contraction value of the circuit board of the present invention is used for a processor of a circuit board molding equipment to execute, so that the circuit board molding equipment is Before the multi-layer core board group is drilled, calculate the expansion and shrinkage value of the multi-layer core board group. The multi-layer core board group is composed of multiple core boards stacked on each other. Any marking unit in a longitudinal direction (such as the Z-axis direction in FIG. 3 ) does not completely overlap with any marking unit, and the longitudinal direction is parallel to a normal line of a surface of the multilayer core board assembly.
電路板的漲縮值的計算方法包含:一掃描步驟S11:控制一掃描裝置(例如是X光掃描設備)對多層芯板組進行掃描,以取得各個芯板的各個標記單元的一標記座標;一邊角座標計算步驟S12:利用各個芯板所對應的四個標記座標及各個芯板相對應的一芯板資訊,計算出各個芯板的四個邊角座標;芯板資訊至少包含一芯板尺寸;一重心座標計算步驟S13:利用各個芯板的四個邊角座標,計算出各個芯板的一重心座標;一平均重心座標計算步驟S14:利用多個重心座標計算出一平均重心座標;一基準邊角座標計算步驟S15:利用平均重心座標及一電路板標準尺寸資訊,計算出四個基準邊角座標;其中,四個基準邊角座標通過四條虛擬線段相連接後,能構成一基準矩形;一容許範圍界定步驟S16:以各個基準邊角座標為中心,並以一預設容許值為半徑界定出四個初始容許範圍;一調整步驟S17:調整平均重心座標及四個基準邊角座標,以取得一優化重心座標FVG及四個優化邊角座標;其中,四個優化邊角座標通過四條虛擬線段相連接後,能構成一優化四邊形;優化四邊形與基準矩形於X軸方向的變形量及優化四邊形與基準矩形於Y軸方向的變形量,都不大於一容許變形量;其中,以各個優化邊角座標FVG為中心,並以預設容許值為 半徑能界定出的四個優化容許範圍,而落在各個優化容許範圍內的初始邊角座標的總數,不小於落在各個初始容許範圍內的初始邊角座標的總數;一計算步驟S18:利用基準矩形及優化四邊形計算出多層芯板組的一變形量(即漲縮值)。 The calculation method of the expansion and contraction value of the circuit board includes: a scanning step S11: controlling a scanning device (such as X-ray scanning equipment) to scan the multi-layer core board group to obtain a marking coordinate of each marking unit of each core board; Calculation step S12 of corner coordinates: use the four marked coordinates corresponding to each core board and a core board information corresponding to each core board to calculate the four corner coordinates of each core board; the core board information includes at least one core board Size; a center of gravity coordinate calculation step S13: use the four corner coordinates of each core plate to calculate a center of gravity coordinate of each core plate; an average center of gravity coordinate calculation step S14: use multiple center of gravity coordinates to calculate an average center of gravity coordinate; Calculation step S15 of a reference corner coordinate: using the average center of gravity coordinates and a standard size information of a circuit board to calculate four reference corner coordinates; where the four reference corner coordinates are connected by four virtual line segments to form a reference Rectangle; an allowable range defining step S16: taking the coordinates of each reference corner as the center, and defining four initial allowable ranges with a preset allowable value as a radius; an adjustment step S17: adjusting the average center of gravity coordinates and the four reference corners Coordinates, to obtain an optimized center of gravity coordinates FVG and four optimized corner coordinates; wherein, after the four optimized corner coordinates are connected by four virtual line segments, an optimized quadrilateral can be formed; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction The amount of deformation and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than a permissible deformation; among them, each optimized corner coordinate FVG is the center, and the preset allowable value is Radius can define four optimized allowable ranges, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range; a calculation step S18: using A deformation amount (namely expansion and contraction value) of the multi-layer core board group is calculated from the reference rectangle and the optimized quadrilateral.
如圖3至圖5所示,多層芯板組100例如可以是包含4個芯板,各個芯板的尺寸是大致相同。需說明的是,於此僅是為利說明,而以多層芯板組100僅包含4個芯板為例,在實際應用中,多層芯板組100例如可以是包含10層以上的芯板,亦即,多層芯板組100所包含的芯板的數量,可以是大於2層以上。關於多層芯板組100所包含的多個芯板彼此間相互固定的方式,於此不加以限制。
As shown in FIG. 3 to FIG. 5 , the multi-layer
各個芯板11、12、13、14的其中一個寬側面11A、12A、13A、14A可以是分別具有一非線路區A1及一線路區A2,線路區A1上可以是形成有至少一線路,各個線路區A1中的線路即為俗稱的PCB Layout。芯板11的線路區A1設置有四個標記單元111、112、113、114,且四個標記單元111、112、113、114是大致設置於一虛擬矩形B3的四個邊角;芯板12的線路區A1設置有四個標記單元121、122、123、124,且四個標記單元121、122、123、124是大致設置於一虛擬矩形B4的四個邊角;同理,芯板13的四個標記單元131、132、133、134是大致設置於虛擬矩形B1的四個邊角,芯板14的四個標記單元141、142、143、144是大致設置於虛擬矩形B2的四個邊角。各個虛擬矩形B1、B2、B3、B4的外型可以是各個芯板的外型的等比例縮小,且不同的虛擬矩形B1、B2、B3、B4的外型是芯板的外型以不同的比例縮小而成。
One of the
如圖4及圖5所示,在掃描裝置掃描多層芯板組100後得到的影像中,分屬於不同芯板11、12、13、14的各個標記單元111~114、121~124、131~134、141~144彼此間是不相互重疊地設置,也就是說,在掃
描裝置掃描多層芯板組100後得到的影像,各個標記單元111~114、121~124、131~134、141~144是彼此錯位地設置。
As shown in Figures 4 and 5, in the image obtained after the scanning device scans the multi-layer
在實際應用中,在掃描裝置掃描多層芯板組100後得到的掃描影像中,芯板11、13所包含的標記單元111~114、131~134可以是大致位於同一虛擬軸線C1上,芯板12、14所包含的標記單元121~124、141~144可以是大致位於另一虛擬軸線C2上,且標記單元111~114、131~134在虛擬軸線C1上是彼此不相互重疊,且標記單元121~124、141~144在虛擬軸線C2上是彼此不相互重疊。需特別強調的是,於圖5中所示的邊框Z及所有標記單元的位置,都僅是用來顯示多層芯板組100於掃描影像中的邊線的大致位置,而邊框Z及所有標記單元的位置不代表多層芯板組100於掃描影像中真實的情況。
In practical applications, in the scanning image obtained after the scanning device scans the multi-layer
在實際應用中,各個標記單元可以是不貫穿芯板的結構,而各個標記單元可以是在製造芯板的線路區域中的線路的過程中,一併製造而成。當然,在特殊的應用中,各個標記單元也可以是貫穿芯板的穿孔。 In practical applications, each marking unit may be a structure that does not penetrate the core board, and each marking unit may be manufactured together during the process of manufacturing the circuit in the circuit area of the core board. Of course, in special applications, each marking unit can also be a perforation through the core board.
所述掃描裝置不以X光掃描裝置為限,任何具有穿透光的掃描裝置,都屬於在此所指的掃描裝置可以應用的範圍,或者,任何可以用來掃描多層芯板組100,以取的各個標記單元的座標的掃描裝置,也都屬於本發明所指的掃描裝置可應用的範圍。
The scanning device is not limited to the X-ray scanning device, any scanning device with penetrating light belongs to the applicable scope of the scanning device referred to here, or any scanning device that can be used to scan the multi-layer
請一併參閱圖5及圖6,於掃描步驟S11及邊角座標計算步驟S12中,處理器可以是利用各個芯板的四個標記單元座標111、112、113、114(121~124、131~134、141~144),及各個芯板的實際尺寸資料,據以計算出各個芯板的四個邊角座標C11、C12、C13、C14(C21~C24、C31~C34、C41~C44)。舉例來說,處理器可以是將四個標記單元座標111、112、113、114(121~124、131~134、141~144)放大預定比例,據以得到四個邊角座標C11、C12、C13、C14(C21~C24、C31~C34、C41~C44)。需說明
的,圖6是以誇張的呈現方式,來顯示各個芯板的變形狀況,而圖6並非代表實際情況;另外,為利清楚說明本發明的各個流程步驟的內容,於圖6至圖8中,各個座標是以圓形、菱形、三角形、方形、五邊形的圖案作為標示。
Please refer to FIG. 5 and FIG. 6 together. In the scanning step S11 and the corner coordinate calculation step S12, the processor can use the four marking unit coordinates 111, 112, 113, 114 (121~124, 131 ~134, 141~144), and the actual size data of each core board, based on which the four corner coordinates C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board are calculated . For example, the processor can enlarge the
如圖7所示,處理器取得各個芯板的四個邊角座標C11、C12、C13、C14(C21~C24、C31~C34、C41~C44)後,處理器執行重心座標計算步驟S13時,可以是將各個芯板的四個邊角座標C11、C12、C13、C14(C21~C24、C31~C34、C41~C44)的所有X軸座標加總後取平均值,以取得重心座標G1(G2、G3、G4)的X軸座標值,並將各個芯板的四個邊角座標C11、C12、C13、C14(C21~C24、C31~C34、C41~C44)的所有Y軸座標加總後取平均值,以取得重心座標G1(G2、G3、G4)的Y軸座標值。 As shown in Figure 7, after the processor obtains the four corner coordinates C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board, when the processor executes the center of gravity coordinate calculation step S13, It can be the average of all the X-axis coordinates of the four corner coordinates C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board and then take the average value to obtain the center of gravity coordinate G1( G2, G3, G4) X-axis coordinate values, and sum up all Y-axis coordinates of the four corner coordinates C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board Then take the average value to obtain the Y-axis coordinate value of the center of gravity coordinate G1 (G2, G3, G4).
處理器取得各個芯板的重心座標G1(G2、G3、G4)後,處理器執行平均重心座標計算步驟S4時,則可以是將所有重心座標G1、G2、G3、G4的X軸座標加總後取平均值,以取得平均重心座標AVG的X軸座標值,並將所有重心座標G1、G2、G3、G4的Y軸座標加總後取平均值,以取得平均重心座標AVG的Y軸座標值。處理器計算出平均重心座標AVG後,可以是利用電路板標準尺寸資訊中的電路板的長度及寬度等資料,以平均重心座標AVG為中心,計算出四個基準邊角座標SG1、SG2、SG3、SG4,而四個基準邊角座標SG1、SG2、SG3、SG4能相互連線據以構成所述基準矩形RE。處理器計算出四個基準邊角座標SG1、SG2、SG3、SG4後,處理器可以分別以各個基準邊角座標SG1、SG2、SG3、SG4為中心,並以預定容許值為半徑界定出四個初始容許範圍TR1、TR2、TR3、TR4。 After the processor obtains the center-of-gravity coordinates G1 (G2, G3, G4) of each core board, when the processor executes the average center-of-gravity coordinate calculation step S4, the X-axis coordinates of all the center-of-gravity coordinates G1, G2, G3, and G4 can be summed Then take the average value to obtain the X-axis coordinate value of the average center-of-gravity coordinate AVG, and sum up the Y-axis coordinates of all center-of-gravity coordinates G1, G2, G3, and G4 and then take the average value to obtain the Y-axis coordinate value of the average center-of-gravity coordinate AVG value. After the processor calculates the average center of gravity coordinate AVG, it can use the length and width of the circuit board in the standard size information of the circuit board to calculate the four reference corner coordinates SG1, SG2, and SG3 with the average center of gravity coordinate AVG as the center. , SG4, and the four reference corner coordinates SG1, SG2, SG3, SG4 can be connected with each other to form the reference rectangle RE. After the processor calculates the four reference corner coordinates SG1, SG2, SG3, SG4, the processor can respectively take each reference corner coordinate SG1, SG2, SG3, SG4 as the center, and define four Initial allowable ranges TR1, TR2, TR3, TR4.
當處理器界定出四個初始容許範圍TR1、TR2、TR3、TR4後,處理器將執行調整步驟S17。處理器執行調整步驟S17時,處理器可以是先判斷各個初始容許範圍TR1、TR2、TR3、TR4內所包含的邊角座標的 數量、各個基準邊角座標SG1、SG2、SG3、SG4與其所相鄰的各個邊角座標的直線距離等,據以決定使平均重心座標AVG及四個基準邊角座標SG1、SG2、SG3、SG4向哪一個方向移動,從而使各個初始容許範圍TR1、TR2、TR3、TR4內可以涵蓋到最多數量的邊角座標。 After the processor defines four initial allowable ranges TR1 , TR2 , TR3 , TR4 , the processor will execute the adjustment step S17 . When the processor executes the adjustment step S17, the processor may first determine the corner coordinates included in each initial allowable range TR1, TR2, TR3, TR4 Quantity, each reference corner coordinates SG1, SG2, SG3, SG4 and the straight-line distance of each adjacent corner coordinates, etc., according to which the average center of gravity coordinate AVG and the four reference corner coordinates SG1, SG2, SG3, SG4 Which direction to move, so that each initial allowable range TR1, TR2, TR3, TR4 can cover the maximum number of corner coordinates.
更具體來說,如圖7所示,當處理器執行完容許範圍界定步驟S16後,假設位於圖中左上角的初始容許範圍TR1內,僅包含了三個邊角座標C11、C21、C31,而其中一個邊角座標C41是落在初始容許範圍TR1外,且位於圖中左下角的初始容許範圍TR4內,僅包含了三個邊角座標C14、C24、C34,而邊角座標C44不位於初始容許範圍TR4內。圖中的另外兩個初始容許範圍TR2、TR3內則分別包含了相鄰的四個邊角座標C12、C22、C32、C42及C13、C23、C33、C43。 More specifically, as shown in FIG. 7, after the processor executes the allowable range defining step S16, it is assumed that the initial allowable range TR1 located in the upper left corner of the figure contains only three corner coordinates C11, C21, and C31. One of the corner coordinates C41 falls outside the initial allowable range TR1, and is located in the initial allowable range TR4 in the lower left corner of the figure. It only includes three corner coordinates C14, C24, and C34, and the corner coordinate C44 is not located Within the initial allowable range TR4. The other two initial allowable ranges TR2 and TR3 in the figure respectively include four adjacent corner coordinates C12, C22, C32, C42 and C13, C23, C33, C43.
在此情況下,處理器執行調整步驟S17時,可以是調整位於圖中的左上角及左下角的兩個基準邊角座標SG1、SG4,基準邊角座標SG1、SG4被調整後,相應的初始容許範圍TR1、TR4將同步被調整,而處理器在調整各初始容許範圍TR1、TR4的位置後,將會判斷各個初始容許範圍TR1、TR4內所包含的邊角座標的數量,且處理器還會判斷調整後的四個基準邊角座標,所構成的矩形與基準矩形RE分別於X軸及Y軸的變形量是否不大於容許變形量,若是處理器判斷部分的基準邊角座標移動後,可以使調整後的初始容許範圍涵蓋到更多的邊角座標,但調整後的四個基準邊角座標所構成的矩形,與基準矩形RE於X軸及Y軸的變形量大於容許變形量,則處理器將會調整未被調整的基準邊角座標,據以在提升各個初始容許範圍所涵蓋的邊角座標的數量的情況下,仍使調整後的四個基準邊角座標所構成的矩形,與基準矩形RE分別於X軸及Y軸的變形量都不大於容許變形量。 In this case, when the processor executes the adjustment step S17, it may adjust the two reference corner coordinates SG1 and SG4 located in the upper left corner and the lower left corner in the figure. After the reference corner coordinates SG1 and SG4 are adjusted, the corresponding initial The allowable ranges TR1 and TR4 will be adjusted synchronously, and after the processor adjusts the position of each initial allowable range TR1 and TR4, it will judge the number of corner coordinates contained in each initial allowable range TR1 and TR4, and the processor will also It will judge whether the deformation of the rectangle formed by the adjusted four reference corner coordinates and the reference rectangle RE on the X-axis and Y-axis is not greater than the allowable deformation amount. If the processor judges that the reference corner coordinates of the part are moved, The adjusted initial allowable range can cover more corner coordinates, but the deformation of the rectangle formed by the adjusted four reference corner coordinates and the reference rectangle RE on the X-axis and Y-axis is greater than the allowable deformation. Then the processor will adjust the unadjusted reference corner coordinates, so that while increasing the number of corner coordinates covered by each initial allowable range, the rectangle formed by the adjusted four reference corner coordinates will still be , and the deformation amount of the reference rectangle RE on the X-axis and the Y-axis is not greater than the allowable deformation amount.
承上,在實際應用中,於圖7所示的情況中,處理器可以是先計算各個邊角座標與相鄰的初始容許範圍分別於X軸及Y軸的一橫向距 離及一縱向距離,再依據各個邊角座標所對應的橫向距離及縱向距離,決定至少一個邊角座標於X軸及Y軸的移動距離。具體來說,如圖7所示,處理器於調整步驟S17中,可以是先計算不位於初始容許範圍TR1、TR4內的邊角座標C41、C44與相應的初始容許範圍TR1、TR4於X軸及Y軸的差值,並計算其餘的各個邊角座標與相鄰的初始容許範圍於X軸及Y軸的差值,而後,處理器即可判斷在調整初始容許範圍TR1、TR4,以使初始容許範圍TR1、TR4涵蓋邊角座標C41、C44的情況下,其他的邊角座標是否會離開相鄰的初始容許範圍,藉此,決定要如何調整各個基準邊角座標。 Bearing in mind, in practical applications, in the situation shown in Figure 7, the processor may first calculate a lateral distance between each corner coordinate and the adjacent initial allowable range on the X-axis and the Y-axis and a vertical distance, and then determine the moving distance of at least one corner coordinate on the X-axis and the Y-axis according to the horizontal distance and the vertical distance corresponding to each corner coordinate. Specifically, as shown in FIG. 7, in the adjustment step S17, the processor may first calculate the corner coordinates C41, C44 that are not within the initial allowable range TR1, TR4 and the corresponding initial allowable range TR1, TR4 on the X-axis and the Y-axis, and calculate the difference between the other corner coordinates and the adjacent initial allowable ranges on the X-axis and Y-axis, and then the processor can determine whether to adjust the initial allowable range TR1, TR4, so that When the initial allowable ranges TR1 and TR4 cover the corner coordinates C41 and C44, whether other corner coordinates will deviate from the adjacent initial allowable ranges is used to determine how to adjust each reference corner coordinate.
也就是說,在圖7所示的情況下,處理器例如可以是先嘗試調整位於圖中左上角及左下角的基準邊角座標SG1、SG4,而不調整位於圖中右上角及右下角的基準邊角座標SG2、SG3,據以使位於圖中左上角的初始容許範圍TR1、TR4調整後,分別能夠涵蓋相鄰的四個邊角座標C11、C21、C31、C41及C14、C24、C34、C44;假設處理器在僅調整位於圖中的兩個基準邊角座標SG1、SG4後,判斷調整後的兩個基準邊角座標SG1、SG4及兩個未調整的基準邊角座標SG2、SG3所共同構成的矩形,與基準矩形RE於X軸及Y軸的變形量,超出了容許變形範圍,則處理器將會調整位於圖中右上角及右下角的兩個基準邊角座標SG2、SG3,據以使兩個基準邊角座標SG2、SG3所對應的初始容許範圍TR2、TR3,在仍然可以涵蓋相鄰的四個邊角座標的情況下調整位置,直到調整後的四個基準邊角座標所構成的矩形,與基準矩形RE於X軸及Y軸的變形量,都符合容許變形範圍為止。當處理器判定調整後的各個初始容許範圍涵蓋了更多的相鄰的邊角座標,且調整後的四個基準邊座標所構成的矩形,與基準矩形RE於X軸及Y軸的變形量,都符合容許變形範圍時,調整後的各個基準邊角座標即為所述優化邊角座標FG1、FG2、FG3、FG4,而調整位置後的各個初始容許範圍則為所述優化容許範圍FR1、FR2、FR3、FR4,四個優化邊角座標FG1、FG2、 FG3、FG4的連線所構成的矩形RE2則為所述優化四邊形。 That is to say, in the situation shown in FIG. 7, the processor may, for example, first try to adjust the reference corner coordinates SG1 and SG4 located in the upper left corner and lower left corner of the figure, without adjusting the coordinates SG1 and SG4 located in the upper right corner and lower right corner of the figure. The reference corner coordinates SG2 and SG3 are adjusted to cover the four adjacent corner coordinates C11, C21, C31, C41 and C14, C24 and C34 respectively after adjusting the initial allowable range TR1 and TR4 in the upper left corner of the figure , C44; assuming that the processor only adjusts the two reference corner coordinates SG1 and SG4 in the figure, and then judges the adjusted two reference corner coordinates SG1 and SG4 and the two unadjusted reference corner coordinates SG2 and SG3 If the deformation of the rectangle formed together with the reference rectangle RE on the X-axis and Y-axis exceeds the allowable deformation range, the processor will adjust the two reference corner coordinates SG2 and SG3 located in the upper right corner and lower right corner of the figure , so that the initial allowable ranges TR2 and TR3 corresponding to the two datum corner coordinates SG2 and SG3 adjust the position while still covering the four adjacent corner coordinates until the adjusted four datum corners The rectangle formed by the coordinates and the deformation amount of the reference rectangle RE on the X-axis and the Y-axis all meet the allowable deformation range. When the processor determines that each initial allowable range after adjustment covers more adjacent corner coordinates, and the rectangle formed by the adjusted four reference side coordinates is different from the deformation of the reference rectangle RE on the X-axis and Y-axis , all conform to the allowable deformation range, the adjusted reference corner coordinates are the optimized corner coordinates FG1, FG2, FG3, FG4, and the initial allowable ranges after the adjusted positions are the optimized allowable ranges FR1, FR2, FR3, FR4, four optimized corner coordinates FG1, FG2, The rectangle RE2 formed by the connection of FG3 and FG4 is the optimized quadrilateral.
需說明的是,處理器執行調整步驟S17時,也可以是先在不改變基準矩形的外型情況下調整四個基準邊角座標SG1、SG2、SG3、SG4(例如是使四個基準邊角座標SG1、SG2、SG3、SG4同時於X軸方向平移、使四個基準邊角座標SG1、SG2、SG3、SG4同時於Y軸方向平移、使四個基準邊角座標SG1、SG2、SG3、SG4以平均重心座標AVG為中心進行旋轉),以嘗試使四個初始容許範圍TR1、TR2、TR3、TR4所涵蓋的相鄰的邊角座標的數量提升,若是處理器嘗試後,無法使四個初始容許範圍TR1、TR2、TR3、TR4所涵蓋的相鄰的邊角座標的數量提升,則處理器才再嘗試單獨地調整至少一個基準邊角座標SG1、SG2、SG3、SG4。 It should be noted that, when the processor executes the adjustment step S17, the four reference corner coordinates SG1, SG2, SG3, and SG4 can also be adjusted without changing the appearance of the reference rectangle (for example, to make the four reference corners The coordinates SG1, SG2, SG3, and SG4 are simultaneously translated in the X-axis direction, so that the four reference corner coordinates SG1, SG2, SG3, and SG4 are simultaneously translated in the Y-axis direction, so that the four reference corner coordinates SG1, SG2, SG3, and SG4 Rotate around the average center of gravity coordinate AVG) to try to increase the number of adjacent corner coordinates covered by the four initial allowable ranges TR1, TR2, TR3, and TR4. If the processor tries, it cannot make the four initial When the number of adjacent corner coordinates covered by the allowable ranges TR1 , TR2 , TR3 , TR4 increases, the processor tries to adjust at least one reference corner coordinate SG1 , SG2 , SG3 , SG4 individually.
請參閱圖9,其顯示為本發明的多層電路板的孔洞成型方法的流程示意圖。本發明的多層電路板的孔洞成形方法,包含以下步驟:一準備步驟SX1:準備一多層芯板組,多層芯板組由相互疊合設置的多個芯板構成,任一個標記單元於一縱向方向(例如是圖3中的Z軸方向)不與任一個標記單元完全重疊,縱向方向與多層芯板組的一表面(例如是第一芯板11的寬側面11A)的一法線相互平行;一掃描步驟SX2:控制一掃描裝置對多層芯板組進行掃描,以取得各個芯板的各個標記單元的一標記座標;一邊角座標計算步驟SX3:利用各個芯板所對應的四個標記座標及各個芯板相對應的一芯板資訊,計算出各個芯板的四個邊角座標;芯板資訊至少包含一芯板尺寸;一重心座標計算步驟SX4:利用各個芯板的四個邊角座標,計算出各個芯板的一重心座標;一平均重心座標計算步驟SX5:利用多個重心座標計算出一平均重心座標;
一基準邊角座標計算步驟SX6:利用平均重心座標及一電路板標準尺寸資訊,計算出四個基準邊角座標;其中,四個基準邊角座標通過四條虛擬線段相連接後,能構成一基準矩形;一容許範圍界定步驟SX7:以各個基準邊角座標為中心,並以一預設容許值為半徑界定出四個初始容許範圍;一調整步驟SX8:調整平均重心座標及四個基準邊角座標,以取得一優化重心座標及四個優化邊角座標;其中,四個優化邊角座標通過四條虛擬線段相連接後,能構成一優化四邊形;優化四邊形與基準矩形於X軸方向的變形量及優化四邊形與基準矩形於Y軸方向的變形量,都不大於一容許變形量;其中,以各個優化邊角座標為中心,並以預設容許值為半徑能界定出的四個優化容許範圍,而落在各個優化容許範圍內的初始邊角座標的總數,不小於落在各個初始容許範圍內的初始邊角座標的總數;一計算步驟SX9:利用基準矩形及優化四邊形計算出多層芯板組的一變形量(即漲縮值);一成形步驟SX10:控制一孔洞成形設備(例如是雷射穿孔設備),依據變形量及一電路板孔洞位置資訊,於多層芯板組形成至少一孔洞,以使多層芯板組成為一多層電路板。
Please refer to FIG. 9 , which is a schematic flow chart of the hole forming method of the multilayer circuit board of the present invention. The method for forming a hole in a multilayer circuit board of the present invention includes the following steps: a preparation step SX1: prepare a multilayer core board group, the multilayer core board group is composed of a plurality of core boards stacked on each other, and any marking unit is placed on a The longitudinal direction (for example, the Z-axis direction in FIG. 3 ) does not completely overlap with any marking unit, and the longitudinal direction and a normal line of a surface of the multilayer core board group (for example, the
本實施例的掃描步驟SX2、邊角座標計算步驟SX3、重心座標計算步驟SX4、平均重心座標計算步驟SX5、基準邊角座標計算步驟SX6、容許範圍界定SX7及調整步驟SX8,與前述掃描步驟S2、邊角座標計算步驟S3、重心座標計算步驟S4、平均重心座標計算步驟S5、基準邊角座標計算步驟S6、容許範圍界定S7及調整步驟S8相同,於此不再贅述。 The scanning step SX2, corner coordinate calculation step SX3, center-of-gravity coordinate calculation step SX4, average center-of-gravity coordinate calculation step SX5, reference corner coordinate calculation step SX6, allowable range definition SX7, and adjustment step SX8 in this embodiment are similar to the aforementioned scanning step S2 , calculation step S3 of corner coordinates, step S4 of calculation of center of gravity coordinates, step S5 of calculation of average center of gravity coordinates, step S6 of calculation of reference corner coordinates, definition of allowable range S7 and step S8 of adjustment are the same, and will not be repeated here.
於所述成型步驟SX10中,可以是依據需求利用孔洞成型設備,於多層芯板組形成貫穿孔或是盲孔,於此不加以限制。 In the forming step SX10 , hole forming equipment may be used to form through holes or blind holes in the multi-layer core board according to requirements, and no limitation is imposed here.
綜上所述,本發明的電路板的漲縮值的計算方法及多層電路板的孔洞成形方法,可以更好地計算出電路板的漲縮值,藉此,可以大幅降低相關孔洞成形設備於多層芯板組上形成盲孔或是貫穿孔時,發生偏破等問題的機率。 In summary, the method for calculating the expansion and contraction value of the circuit board and the hole forming method for the multi-layer circuit board of the present invention can better calculate the expansion and contraction value of the circuit board, thereby greatly reducing the cost of related hole forming equipment. When blind holes or through holes are formed on the multi-layer core board group, the probability of problems such as partial breakage will occur.
以上所述僅為本發明的較佳可行實施例,非因此侷限本發明的專利範圍,故舉凡運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的保護範圍內。 The above descriptions are only preferred feasible embodiments of the present invention, and do not limit the patent scope of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the scope of protection of the present invention. .
S11~S18:流程步驟 S11~S18: Process steps
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